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/gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/
H A Dstats.txt11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/
H A Dstats.txt11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/
H A Dstats.txt11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/
H A Dstats.txt11960:c7bf1b698ccd Wed Mar 29 19:14:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/x86/isa/
H A Dspecialize.isa4575:d0017efdfa02 Thu Jun 14 16:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Implement a handful more instructions and differentiate macroops based on the operand types they expect.
/gem5/src/arch/power/
H A DSConscript9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change.
H A Disa_traits.hh9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change.
/gem5/src/base/
H A Dhostinfo.cc9142:e9b713df4e1d Mon Aug 06 19:52:00 EDT 2012 Steve Reinhardt <steve.reinhardt@amd.com> str: add an overloaded startswith() utility method
for various string types and use it in a few places.
H A Drefcnt.hh3877:2432a50b7d25 Wed Dec 27 13:52:00 EST 2006 Nathan Binkert <binkertn@umich.edu> No need to use NULL, just use 0
The result of operator= cannot be an l-value
/gem5/src/sim/
H A Dclocked_object.cc11424:e07fd01651f3 Tue Apr 05 11:52:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> power: Add support for power models

This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Finally, the thermal model is updated to use the power usage as input.
/gem5/src/arch/x86/
H A Dpagetable.hh12457:b9b7bdb5a8ac Sat Jan 06 02:52:00 EST 2018 Gabe Black <gabeblack@google.com> x86, mem: Get rid of PageTableOps::getBasePtr.

Pass this constant into the page table constructor.

Change-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb
Reviewed-on: https://gem5-review.googlesource.com/7345
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
/gem5/src/systemc/channel/
H A Dsc_clock.cc12878:97fdce181f51 Wed Jun 13 21:52:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add some deprecated features to sc_clock.*.

Add in two deprecated typedefs, and a deprecated constructor. These
are necessary to get the regressions to build.

Change-Id: Id8320a67c680acbca0abaee9898158ffd2678d67
Reviewed-on: https://gem5-review.googlesource.com/11183
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/configs/common/
H A DHMC.py11292:5d1d5bf9c178 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> configs: Fix inheritance of HMCSystem and cleanup spacing

Minor fix to ensure the HMCSystem can actually be instantiated
(SimObject cannot be created). Also address some spacing issues.
H A Dcpu2000.py6028:137a2b89eed4 Wed Apr 15 03:52:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> configs: Allow M5_CPU2000 env var to set CPU2K binary path.
It would be nice to have a more comprehensive mechanism
but this is a big improvement over manually editing the script.
/gem5/src/arch/alpha/
H A Disa.cc13614:52c5311db96b Mon Nov 19 21:28:00 EST 2018 Gabe Black <gabeblack@google.com> alpha: Stop using architecture specific register types.

Change-Id: I4052000014c9f6f9ecefd3f37e58595c61599484
Reviewed-on: https://gem5-review.googlesource.com/c/14461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/arm/
H A Dpmu.hh13638:76cb1cecc057 Thu Jan 31 04:52:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Allow ArmPPI usage for PMU

Differently from ArmSPIs, ArmPPI interrupts need to be instantiated by
giving a ThreadContext pointer in the ArmPPIGen::get() method. Since the
PMU is registering the ThreadContext only at ISA startup time, ArmPPI
generation in deferred until the PMU has a non NULL pointer.

Change-Id: I17daa6f0e355363b8778d707b440cab9f75aaea2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16204
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/dev/net/
H A Dethertap.cc11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default

Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
/gem5/src/mem/
H A DSimpleMemory.py9823:c8dd3368c6ba Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add an internal packet queue in SimpleMemory

This patch adds a packet queue in SimpleMemory to avoid using the
packet queue in the port (and thus have no involvement in the flow
control). The port queue was bound to 100 packets, and as the
SimpleMemory is modelling both a controller and an actual RAM, it
potentially has a large number of packets in flight. There is
currently no limit on the number of packets in the memory controller,
but this could easily be added in a follow-on patch.

As a result of the added internal storage, the functional access and
draining is updated. Some minor cleaning up and renaming has also been
done.

The memtest regression changes as a result of this patch and the stats
will be updated.
H A DAbstractMemory.py9835:cc7a7fc71c42 Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Change AbstractMemory defaults to match the common case

This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.
/gem5/src/python/pybind11/
H A Devent.cc12041:52b3b120dbc0 Wed May 10 05:57:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> python: Fix PyEvent reference counting bug

The current implementation of reference counting for PyEvents only
partially works. The native object is currently kept alive while it is
in the event queue. However, if the Python object goes out of scope,
the Python side of this object is garbage collected which leaves a
"dangling" native object. This results in confusing error messages
where PyBind is unable to find the Python implementation of an event
when it is triggered.

Implement reference counting using the generalized reference counting
API instead.

Change-Id: I4e8e04abc4f61dff238d718065f5371e73b38ab3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3222
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Dcore.cc12011:1279b1d30ccd Fri May 05 19:52:00 EDT 2017 Gabe Black <gabeblack@google.com> misc: Expose the listener loopbackOnly function to python.

Change-Id: Ibb405af54a46a93706a6f476b5314491e84be0c8
Reviewed-on: https://gem5-review.googlesource.com/3081
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/tests/configs/
H A Darm_generic.py9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig

This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.
H A Dx86_generic.py9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig

This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.
H A Dalpha_generic.py9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig

This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.
/gem5/src/mem/protocol/
H A DSConscript9219:258753d3bc47 Wed Sep 12 15:52:00 EDT 2012 Jason Power <power.jg@gmail.com> Ruby: Modify Scons so that we can put .sm files in extras
Also allows for header files which are required in slicc generated
code to be in a directory other than src/mem/ruby/slicc_interface.

Completed in 110 milliseconds

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