History log of /gem5/src/arch/power/SConscript
Revision Date Author Comments
# 12222:6db0fc7407a5 15-Oct-2017 Gabe Black <gabeblack@google.com>

scons: Stop generating inc.d in the isa parser.

Generating dependency/build product information in the isa parser breaks scons
idea of how a build is supposed to work. Arm twisting it into working forced
a lot of false dependencies which slowed down the build.

Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca
Reviewed-on: https://gem5-review.googlesource.com/5081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 11320:42ecb523c64a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.


# 11176:741b3059946e 25-Oct-2015 Boris Shingarov <shingarov@labware.com>

power: Implement Remote GDB


# 10196:be0e1724eb39 09-May-2014 Curtis Dunham <Curtis.Dunham@arm.com>

arch: teach ISA parser how to split code across files

This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.

The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.

Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.

Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.

Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.


# 9384:877293183bdf 07-Jan-2013 Andreas Sandberg <Andreas.Sandberg@arm.com>

arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.


# 9057:f5ee56466b91 05-Jun-2012 Ali Saidi <Ali.Saidi@ARM.com>

ISA: Back-out NoopMachInst as a StaticInstPtr change.


# 9040:cdfe09f9bdee 04-Jun-2012 Gabe Black <gblack@eecs.umich.edu>

ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.

This eliminates a use of the ExtMachInst type outside of the ISAs.


# 9022:bb25e7646c41 25-May-2012 Gabe Black <gblack@eecs.umich.edu>

ISA: Make the decode function part of the ISA's decoder.


# 8792:1c0812bae427 13-Nov-2011 Gabe Black <gblack@eecs.umich.edu>

Power: Add a stubbed out stacktrace.cc


# 8772:a5a83fc04972 30-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Remove the last references to FULL_SYSTEM from POWER.


# 8759:e9455f81588f 16-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

Power: Add a stub implementation for vtophys in SE and FS.


# 8745:575cab0db076 09-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Build the Interrupt objects in SE mode.


# 8335:9228e00459d4 02-Jun-2011 Nathan Binkert <nate@binkert.org>

scons: rename TraceFlags to DebugFlags


# 7506:e76cc0ca16cc 22-Jul-2010 Timothy M. Jones <tjones1@inf.ed.ac.uk>

Power: Provide a utility function to copy registers from one thread context
to another in the Power ISA.


# 6691:cd68b6ecd68d 27-Oct-2009 Timothy M. Jones <tjones1@inf.ed.ac.uk>

POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.