Searched hist:2015 (Results 651 - 675 of 1505) sorted by relevance
/gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/ | ||
H A D | simerr | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/ | ||
H A D | simerr | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/ | ||
H A D | simerr | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/ | ||
H A D | simerr | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/ | ||
H A D | simerr | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/ | ||
H A D | simerr | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/ | ||
H A D | simerr | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/ | ||
H A D | simerr | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/src/mem/ | ||
H A D | mem_checker.hh | 11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions. |
H A D | drampower.cc | 11229:1b9331fd8966 Wed Nov 25 13:52:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Fix search-replace issues in DRAMPower wrapper license Fix a number of unintentional insertions of 'const'. |
/gem5/src/arch/x86/isa/insts/x87/control/ | ||
H A D | save_and_restore_x87_environment.py | 10899:b8b8ad2c72dd Sat Jul 04 11:43:00 EDT 2015 Nikos Nikoleris <nikos.nikoleris@gmail.com> x86: Adjust the size of the values written to the x87 misc registers All x87 misc registers are implemented in an array of 64 bit values but in real hardware the size of some of these registers is smaller. Previsouly all 64 bits where incorrectly set and then later read. To ensure correctness we mask the value in setMiscRegNoEffect to write only the valid bits. Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
/gem5/src/mem/ruby/common/ | ||
H A D | TypeDefines.hh | 11061:25b53a7195f7 Sat Aug 29 11:19:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate type uint64 and int64 These types are being replaced with uint64_t and int64_t. 11049:dfb0aa3f0649 Wed Aug 19 11:02:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: reverts to changeset: bf82f1f7b040 11031:3815437cb231 Fri Aug 14 20:28:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate type uint64 and int64 These types are being replaced with uint64_t and int64_t. 11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system. |
/gem5/tests/quick/se/70.twolf/ | ||
H A D | test.py | 10752:62b24818c8c6 Thu Mar 19 04:06:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> tests: Recategorise regressions based on run time This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long. Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | pseudo.isa | 10696:b5e5068fcb26 Mon Feb 16 03:32:00 EST 2015 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Merge ISA files with pseudo instructions This changeset moves the pseudo instructions used to signal unknown instructions and unimplemented instructions to the same source files as the decoder fault. |
/gem5/src/arch/generic/ | ||
H A D | tlb.cc | 10687:276da6265ab8 Wed Feb 11 10:23:00 EST 2015 Andreas Sandberg <Andreas.Sandberg@ARM.com> sim: Move the BaseTLB to src/arch/generic/ The TLB-related code is generally architecture dependent and should live in the arch directory to signify that. |
/gem5/src/dev/i2c/ | ||
H A D | bus.cc | 11262:3aeb879a66e6 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move i2c functionality to src/dev/i2c/ |
/gem5/src/dev/pci/ | ||
H A D | device.cc | 11260:bedcc64f6145 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move existing PCI device functionality to src/dev/pci Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing devices to use the new header location. This also renames the PCIDEV debug flag to have a capitalization that is consistent with the PCI host and other devices. |
/gem5/src/mem/ruby/structures/ | ||
H A D | PersistentTable.cc | 11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system. |
/gem5/src/sim/ | ||
H A D | fd_entry.cc | 10930:ddc3d96d6313 Fri Jul 24 03:25:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> base: refactor process class (specifically FdMap and friends) This patch extends the previous patch's alterations around fd_map. It cleans up some of the uglier code in the process file and replaces it with a more concise C++11 version. As part of the changes, the FdMap class is pulled out of the Process class and receives its own file. |
/gem5/configs/example/ | ||
H A D | memcheck.py | 11053:62544e45c0f4 Fri Aug 21 07:03:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Add explicit Cache subclass and make BaseCache abstract Open up for other subclasses to BaseCache and transition to using the explicit Cache subclass. 10887:279efb97ec99 Fri Jul 03 10:14:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Remove redundant is_top_level cache parameter This patch takes the final step in removing the is_top_level parameter from the cache. With the recent changes to read requests and write invalidations, the parameter is no longer needed, and consequently removed. This also means that asymmetric cache hierarchies are now fully supported (and we are actually using them already with L1 caches, but no table-walker caches, connected to a shared L2). 10720:67b3e74de9ae Mon Mar 02 04:00:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Move crossbar default latencies to subclasses This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden. 10705:c6cb94a14fea Mon Feb 16 03:35:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> config: Add memcheck stress test This is a rather unfortunate copy of the memtest.py example script, that actually stresses the system with true sharing as opposed to the false sharing of the MemTest. To do so it uses TrafficGen instances to generate the reads/writes, and MemCheckerMonitor combined with the MemChecker to check the validity of the read/written values. As a bonus, this script also enables the addition of prefetchers, and the traffic is created to have a mix of random addresses and linear strides. We use the TaggedPrefetcher since the packets do not have a request with a PC. At the moment the code is almost identical to the memtest.py script, and no effort has been made to factor out the construction of the tree. The challenge is that the instantiation and connection of the testers and monitors is done as part of the tree building. |
/gem5/src/arch/sparc/ | ||
H A D | SparcNativeTrace.py | 10663:fae54a666162 Sun Jan 25 07:22:00 EST 2015 Ali Saidi <Ali.Saidi@ARM.com> cpu: Put all CPU instruction tracers in a single file |
/gem5/src/arch/x86/ | ||
H A D | X86NativeTrace.py | 10663:fae54a666162 Sun Jan 25 07:22:00 EST 2015 Ali Saidi <Ali.Saidi@ARM.com> cpu: Put all CPU instruction tracers in a single file |
/gem5/src/dev/arm/ | ||
H A D | FlashDevice.py | 10801:049eb85e8ea2 Thu Apr 23 13:37:00 EDT 2015 Rene de Jong <rene.dejong@arm.com> arm, dev: Add a NAND flash timing model This adds a NAND flash timing model. This model takes the number of planes into account and is ultimately intended to be used as a high-level performance model for any device using flash. To access the memory, use either readMemory or writeMemory. To make use of the model you will need an interface model such as UFSHostDevice, which is part of a separate patch. At the moment the flash device is part of the ARM device tree since the only use if the UFSHostDevice, and that in turn relies on the ARM GIC. |
H A D | NoMali.py | 10916:5c76426fd9ee Tue Jul 07 05:03:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Add a device model that uses the NoMali model Add a simple device shim that interfaces with the NoMali model library. The gem5 side of the interface supports Mali T60x/T62x/T760 GPUs. This device model pretends to be a Mali GPU, but doesn't render anything and executes in zero time. |
H A D | UFSHostDevice.py | 10802:876341add7be Thu Apr 23 13:37:00 EDT 2015 Rene de Jong <rene.dejong@arm.com> arm, dev: Add a UFS device This patch introduces a UFS host controller and a UFS device. More information about the UFS standard can be found at the JEDEC site: http://www.jedec.org/standards-documents/results/jesd220 Note that the model does not implement the complete standard, and as such is not an actual implementation of UFS. The following SCSI commands are implemented: inquiry, read, read capacity, report LUNs, start/stop, test unit ready, verify, write, format unit, send diagnostic, synchronize cache, mode select, mode sense, request sense, unmap, write buffer and read buffer. This is sufficient for usage with Linux and Android. To interact with this model a kernel version 3.9 or above is needed. |
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