Searched hist:2011 (Results 726 - 750 of 897) sorted by relevance

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/gem5/src/arch/power/
H A Disa.hh7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/arch/power/isa/
H A Doperands.isa8449:4be49ad47c74 Tue Jul 05 19:52:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Define operand types with a ctype directly.
/gem5/src/arch/sparc/
H A Dregisters.hh8342:77d12d8f7971 Thu Jun 09 01:34:00 EDT 2011 Korey Sewell <ksewell@umich.edu> sparc: compilation fixes for inorder
Add a few constants and functions that the InOrder model wants for SPARC.
* * *
sparc: add eaComp function
InOrder separates the address generation from the actual access so give
Sparc that functionality
* * *
sparc: add control flags for branches
branch predictors and other cpu model functions need to know specific information
about branches, so add the necessary flags here
H A Dtlb.hh8751:a6c772fef2f1 Thu Oct 13 04:37:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Remove the last checks of FULL_SYSTEM.
8749:ca2ae1194e11 Mon Oct 10 03:38:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Let the TLB have friends in FS mode.
8748:01be402c5bf1 Mon Oct 10 03:31:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
7878:d3e6ebcccabf Fri Feb 04 00:47:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
H A Dvtophys.cc8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/arch/x86/linux/
H A Dlinux.hh8600:b0d7c64ada19 Sun Oct 23 01:30:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: implement MAP_FIXED option to mmap()
/gem5/src/cpu/simple/
H A DAtomicSimpleCPU.py7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
/gem5/src/python/m5/
H A Dproxy.py8459:b8c3c20d0385 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Config: Add support for a Self.all proxy object
H A Dsimulate.py8296:be7f03723412 Thu May 12 14:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: move code that loops over all stats into python
8245:a9d06c894afe Wed Apr 20 21:45:00 EDT 2011 Nathan Binkert <nate@binkert.org> fix some build problems from prior changesets
8234:a08c5fb4cd89 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> python: cleanup python code so stuff doesn't automatically happen at startup
this allows things to be overridden at startup (e.g. for tests)
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/sim/
H A Deventq.hh8581:56f97760eadd Thu Sep 22 21:59:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor. I
forget exactly why, but this made life easier when implementing
multi-queue support.

Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8186:d54b7775a6b0 Tue Mar 29 19:36:00 EDT 2011 Korey Sewell <ksewell@umich.edu> sim: typecast Tick to UTick for eventQ assert
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
H A Dvptr.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/tests/configs/
H A Dsimple-atomic-mp-ruby.py7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
H A Do3-timing-mp.py8631:8c038d4cd210 Thu Dec 01 03:15:00 EST 2011 Chander Sudanthi <chander.sudanthi@arm.com> O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.
8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
H A Do3-timing.py8631:8c038d4cd210 Thu Dec 01 03:15:00 EST 2011 Chander Sudanthi <chander.sudanthi@arm.com> O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.
8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
/gem5/src/arch/arm/
H A DArmTLB.py8756:cce8cf3906ca Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ARM: Turn on the page table walker on ARM in SE mode.
H A Dutility.cc8782:10c9297e14d5 Wed Nov 02 04:25:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
8286:abc8ab4ddd93 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for loading the a bootloader and configuring parameters for it
8208:45331a355c38 Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

This change fixes a small bug in the arm copyRegs() code where some registers
wouldn't be copied if the processor was in a mode other than MODE_USER.
Additionally, this change simplifies the way the O3 switchCpu code works by
utilizing TheISA::copyRegs() to copy the required context information
rather than the adhoc copying that goes on in the CPU model. The current code
makes assumptions about the visibility of int and float registers that aren't
true for all architectures in FS mode.
8178:6ea95d4e79e3 Thu Mar 24 14:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.
H A Dutility.hh8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
8300:eb279d6e08a2 Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified. Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
8206:c3090dc00ddf Mon Apr 04 12:42:00 EDT 2011 William Wang <William.Wang@arm.com> ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
8178:6ea95d4e79e3 Thu Mar 24 14:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.
H A Dmiscregs.cc8550:8ac6c1fa657f Tue Sep 13 01:06:00 EDT 2011 Chander Sudanthi<Chander.Sudanthi@ARM.com> CP15 c15: enable execution with accesses to c15 registers

Previously, coprocessor accesses to CP15 c15 would fault. This patch
enables accesses but prints out a warning, as the registers are not implemented.
8549:7cff2156c998 Tue Sep 13 01:06:00 EDT 2011 Daniel Johnson <daniel.johnson@arm.com> ARM: Implement numcpus bits in L2CTLR register.
8058:a259ab86cabf Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Adds dummy support for a L2 latency miscreg.
7853:69aae4379062 Tue Jan 18 17:30:00 EST 2011 Matt Horsnell <Matt.Horsnell@ARM.com> ARM: The ARM decoder should not panic when decoding undefined holes is arch.

This can abort simulations when the fetch unit runs ahead and speculatively
decodes instructions that are off the execution path.
/gem5/src/mem/cache/
H A DSConscript8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
/gem5/src/mem/cache/tags/
H A DSConscript8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
/gem5/src/mem/ruby/network/simple/
H A DSwitch.hh8259:36987780169e Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: moved network config params

Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of
the top-level parent network object and to only those networks that actually
use those parameters.
/gem5/src/dev/x86/
H A DSouthBridge.py8323:fd20dcf1a9aa Mon May 23 17:29:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams()
is the practice of appending to SimObjectVectors which have
already been assigned as children. This practice sidesteps the
assignment operation for those appended SimObjects, which is
where parent/child relationships are typically established.

This patch reworks the config scripts that use append() on
SimObjectVectors, which all happen to be in the x86 system
configuration. At some point in the future, I hope to make
SimObjectVectors immutable (by deriving from tuple rather than
list), at which time this patch will be necessary for correct
operation. For now, it just avoids some of the warning
messages that get printed in adoptOrphanParams().
/gem5/src/arch/sparc/isa/
H A Dbase.isa8738:66bf413b0d5b Fri Sep 30 03:27:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Use the new FullSystem constant where possible.
8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
8565:d9b69f03e7af Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Remove #if FULL_SYSTEMs from the ISA description.
/gem5/src/arch/alpha/
H A Dutility.hh8780:89e0822462a1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.
8300:eb279d6e08a2 Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified. Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/alpha/isa/
H A Dmem.isa8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.
8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations.
8406:87c3641f5bed Sun Jun 19 21:43:00 EDT 2011 Korey Sewell <ksewell@umich.edu> alpha: fix warn_once for prefetches

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