Searched hist:2011 (Results 151 - 175 of 897) sorted by relevance
/gem5/src/kern/ | ||
H A D | operatingsystem.cc | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/arch/arm/insts/ | ||
H A D | branch.hh | 8146:18368caa8489 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Identify branches as conditional or unconditional and direct or indirect. |
/gem5/src/arch/power/insts/ | ||
H A D | condition.hh | 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
H A D | misc.hh | 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/arch/arm/ | ||
H A D | interrupts.hh | 8518:9c87727099ce Fri Aug 19 16:08:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com> Fix bugs due to interaction between SEV instructions and O3 pipeline SEV instructions were originally implemented to cause asynchronous squashes via the generateTCSquash() function in the O3 pipeline when updating the SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system that would lead to a pipeline either going inactive indefinitely or not being able to commit squashed instructions. Fixed SEV instructions to behave like interrupts and cause synchronous sqaushes inside the pipeline, eliminating the race conditions. Also fixed up the semantics of the WFE instruction to behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1 or unmasked interrupts are pending. 8285:c38905a6fa32 Wed May 04 21:38:00 EDT 2011 Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> ARM: Implement WFE/WFI/SEV semantics. 8245:a9d06c894afe Wed Apr 20 21:45:00 EDT 2011 Nathan Binkert <nate@binkert.org> fix some build problems from prior changesets 7847:0c6613ad8f18 Tue Jan 18 17:30:00 EST 2011 Min Kyu Jeong <minkyu.jeong@arm.com> O3: Fixes fetch deadlock when the interrupt clears before CPU handles it. When this condition occurs the cpu should restart the fetch stage to fetch from the original execution path. Fault handling in the commit stage is cleaned up a little bit so the control flow is simplier. Finally, if an instruction is being used to carry a fault it isn't executed, so the fault propagates appropriately. |
/gem5/src/base/ | ||
H A D | refcnt.hh | 8221:8b5f900233ee Wed Apr 13 12:32:00 EDT 2011 Nathan Binkert <nate@binkert.org> refcnt: Update doxygen comments 8220:d9f19c39ddba Wed Apr 13 12:32:00 EDT 2011 Nathan Binkert <nate@binkert.org> refcnt: Inline comparison functions 7866:31a04e5ac4be Sun Jan 23 00:48:00 EST 2011 Nathan Binkert <nate@binkert.org> refcnt: Change things around so that we handle constness correctly. To use a non const pointer: typedef RefCountingPtr<Foo> FooPtr; To use a const pointer: typedef RefCountingPtr<const Foo> ConstFooPtr; 7810:3a790012d6ed Mon Jan 03 15:31:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> RefCount: Fix reference counting pointer == and != with a T* on the left. These operators were expecting a const T& instead of a const T*, and were not being picked up and used by gcc in the right places as a result. Apparently no one used these operators before. A unit test which exposed these problems, verified the solution, and checks other basic functionality is on the way. |
/gem5/src/mem/ruby/network/ | ||
H A D | Network.py | 8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch. 8260:f113f73dd494 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: removed the unused network-wide latency param 8259:36987780169e Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: moved network config params Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of the top-level parent network object and to only those networks that actually use those parameters. 8257:7226aebb77b4 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: convert links & switches to first class C++ SimObjects This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. |
H A D | Network.cc | 8645:89929730804b Sat Dec 31 19:44:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Shuffle some of the included files This patch adds and removes included files from some of the files so as to organize remove some false dependencies and include some files directly instead of transitively. 8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch. 8260:f113f73dd494 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: removed the unused network-wide latency param 8259:36987780169e Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: moved network config params Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of the top-level parent network object and to only those networks that actually use those parameters. 8255:73089f793a0a Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: moved topology to the top network directory Moved the Topology class to the top network directory because it is shared by both the simple and Garnet networks. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7904:6f5299ff8260 Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> MOESI_hammer: Added full-bit directory support |
/gem5/src/mem/slicc/ | ||
H A D | util.py | 8453:82fc1267d3bb Tue Jul 05 21:30:00 EDT 2011 Nathan Binkert <nate@binkert.org> slicc: cleanup slicc code and make it less verbose |
H A D | parser.py | 8454:fad37c6670a6 Tue Jul 05 21:30:00 EDT 2011 Nathan Binkert <nate@binkert.org> slicc: add a protocol statement and an include statement All protocols must specify their name The include statement allows any file to include another file. 8453:82fc1267d3bb Tue Jul 05 21:30:00 EDT 2011 Nathan Binkert <nate@binkert.org> slicc: cleanup slicc code and make it less verbose 8452:3f2c329e9046 Tue Jul 05 21:30:00 EDT 2011 Nathan Binkert <nate@binkert.org> grammar: better encapsulation of a grammar and parsing This makes it possible to use the grammar multiple times and use the multiple instances concurrently. This makes implementing an include statement as part of a grammar possible. 8156:9a6a02a235f1 Fri Mar 18 15:12:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> SLICC: Remove external_type for structures In SLICC, in order to define a type a data type for which it should not generate any code, the keyword external_type is used. For those data types for which code should be generated, the keyword structure is used. This patch eliminates the use of keyword external_type for defining structures. structure key word can now have an optional attribute external, which would be used for figuring out whether or not to generate the code for this structure. Also, now structures can have functions as well data members in them. 8155:099771c7725d Fri Mar 18 15:12:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> SLICC: Remove the keyword wake_up_dependents In order to add stall and wait facility for protocols, a keyword wake_up_dependents was introduced. This patch removes the keyword, instead this functionality is now implemented as function call. 8154:f3d1493787d4 Fri Mar 18 15:12:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> SLICC: Remove the keyword wake_up_all_dependents In order to add stall and wait facility for protocols, a keyword wake_up_all_dependents was introduced. This patch removes the keyword, instead this functionality is now implemented as function call. 8086:bf0335d98250 Wed Feb 23 19:41:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: automate permission setting This patch integrates permissions with cache and memory states, and then automates the setting of permissions within the generated code. No longer does one need to manually set the permissions within the setState funciton. This patch will faciliate easier functional access support by always correctly setting permissions for both cache and memory states. 7922:7532067f818e Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: support to stallAndWait the mandatory queue By stalling and waiting the mandatory queue instead of recycling it, one can ensure that no incoming messages are starved when the mandatory queue puts signficant of pressure on the L1 cache controller (i.e. the ruby memtester). 7839:9e556fb25900 Mon Jan 17 19:46:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Change interface between coherence protocols and CacheMemory The purpose of this patch is to change the way CacheMemory interfaces with coherence protocols. Currently, whenever a cache controller (defined in the protocol under consideration) needs to carry out any operation on a cache block, it looks up the tag hash map and figures out whether or not the block exists in the cache. In case it does exist, the operation is carried out (which requires another lookup). As observed through profiling of different protocols, multiple such lookups take place for a given cache block. It was noted that the tag lookup takes anything from 10% to 20% of the simulation time. In order to reduce this time, this patch is being posted. I have to acknowledge that the many of the thoughts that went in to this patch belong to Brad. Changes to CacheMemory, TBETable and AbstractCacheEntry classes: 1. The lookup function belonging to CacheMemory class now returns a pointer to a cache block entry, instead of a reference. The pointer is NULL in case the block being looked up is not present in the cache. Similar change has been carried out in the lookup function of the TBETable class. 2. Function for setting and getting access permission of a cache block have been moved from CacheMemory class to AbstractCacheEntry class. 3. The allocate function in CacheMemory class now returns pointer to the allocated cache entry. Changes to SLICC: 1. Each action now has implicit variables - cache_entry and tbe. cache_entry, if != NULL, must point to the cache entry for the address on which the action is being carried out. Similarly, tbe should also point to the transaction buffer entry of the address on which the action is being carried out. 2. If a cache entry or a transaction buffer entry is passed on as an argument to a function, it is presumed that a pointer is being passed on. 3. The cache entry and the tbe pointers received __implicitly__ by the actions, are passed __explicitly__ to the trigger function. 4. While performing an action, set/unset_cache_entry, set/unset_tbe are to be used for setting / unsetting cache entry and tbe pointers respectively. 5. is_valid() and is_invalid() has been made available for testing whether a given pointer 'is not NULL' and 'is NULL' respectively. 6. Local variables are now available, but they are assumed to be pointers always. 7. It is now possible for an object of the derieved class to make calls to a function defined in the interface. 8. An OOD token has been introduced in SLICC. It is same as the NULL token used in C/C++. If you are wondering, OOD stands for Out Of Domain. 9. static_cast can now taken an optional parameter that asks for casting the given variable to a pointer of the given type. 10. Functions can be annotated with 'return_by_pointer=yes' to return a pointer. 11. StateMachine has two new variables, EntryType and TBEType. EntryType is set to the type which inherits from 'AbstractCacheEntry'. There can only be one such type in the machine. TBEType is set to the type for which 'TBE' is used as the name. All the protocols have been modified to conform with the new interface. |
/gem5/util/ | ||
H A D | find_copyrights.py | 8333:c1a07ecb6619 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> copyright: Add code for finding all copyright blocks and create a COPYING file The end of the COPYING file was generated with: % python ./util/find_copyrights.py configs src system tests util Update -C command line option to spit out COPYING file |
H A D | style.py | 8583:d182a475a668 Sat Sep 24 11:12:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> style.py: don't die on empty files 8326:8b0eee09deaf Wed May 25 00:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> style: Make the style hook work in directories other than the root. 8238:d8ec0a7b3f0c Sun Apr 17 17:21:00 EDT 2011 Nathan Binkert <nate@binkert.org> style: fix all_regions code and remove bogus region type 8237:b83e07b4541d Sun Apr 17 16:57:00 EDT 2011 Nathan Binkert <nate@binkert.org> style: remove extra debugging print 8228:59d3bfa85f16 Fri Apr 15 13:43:00 EDT 2011 Nathan Binkert <nate@binkert.org> style: add sort_includes to the style hook 8227:f3aaa2470b5a Fri Apr 15 13:43:00 EDT 2011 Nathan Binkert <nate@binkert.org> style: move style verifiers into classes 8226:bca419132437 Fri Apr 15 13:43:00 EDT 2011 Nathan Binkert <nate@binkert.org> style: add a user interface wrapper class makes things work both with mercurial and stand alone with stdio 7834:7107a2f3e53a Thu Jan 13 03:30:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Style checker: Fix a couple bugs in style.py. 7828:817c662677d1 Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> style: prevent the style hook from aborting uncleanly because of an exception 7827:49b7d40ee88a Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> style: clean up style hook code a bit I've renamed the check_whitespace operation to check_style. You're going to need to change your .hg/hgrc file. While you're at it, add a pre-qrefresh hook please. |
/gem5/src/mem/cache/prefetch/ | ||
H A D | pif.cc | 13825:90e5b4dfeaff Mon Feb 25 08:30:00 EST 2019 Ivan Pizarro <ivan.pizarro@metempsy.com> mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | pif.hh | 13825:90e5b4dfeaff Mon Feb 25 08:30:00 EST 2019 Ivan Pizarro <ivan.pizarro@metempsy.com> mem-cache: Proactive Instruction Fetch Implementation Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM. Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/mem/ruby/profiler/ | ||
H A D | AddressProfiler.hh | 8608:02d7ac5fb855 Thu Nov 03 23:46:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove some unused typedefs This patch removes some of the unused typedefs. It also moves some of the typedefs from Global.hh to TypeDefines.hh. The patch also eliminates the file NodeID.hh. 8174:e21f6e70169e Tue Mar 22 07:41:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove CacheMsg class from SLICC The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object. 8165:5955406f7ed0 Sat Mar 19 19:34:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Convert CacheRequestType to RubyRequestType This patch converts CacheRequestType to RubyRequestType so that both the protocol dependent and independent code makes use of the same request type. 8164:b043c0efa024 Sat Mar 19 19:34:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Convert AccessModeType to RubyAccessMode This patch converts AccessModeType to RubyAccessMode so that both the protocol dependent and independent code uses the same access mode. |
/gem5/src/base/stats/ | ||
H A D | text.hh | 8514:57c96df312a1 Fri Aug 19 16:08:00 EDT 2011 Thomas Grass <Thomas.Grass@ARM.com> Stats: Add a sparse histogram stat object. 8296:be7f03723412 Thu May 12 14:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: move code that loops over all stats into python 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
H A D | output.hh | 8514:57c96df312a1 Fri Aug 19 16:08:00 EDT 2011 Thomas Grass <Thomas.Grass@ARM.com> Stats: Add a sparse histogram stat object. 8338:4d1005f78496 Tue Jun 07 03:24:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> gcc 4.0: Add some virtual destructors to make gcc 4.0 happy. 8296:be7f03723412 Thu May 12 14:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: move code that loops over all stats into python 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/arch/x86/isa/ | ||
H A D | includes.isa | 8738:66bf413b0d5b Fri Sep 30 03:27:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Use the new FullSystem constant where possible. 8556:2afd82e84d95 Mon Sep 19 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts. 8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7969:068f061e57a8 Sun Feb 13 20:45:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Put the result used for flags in an intermediate variable. Using the destination register directly causes the ISA parser to treat it as a source even if none of the original bits are used. 7965:f4c89fe1246b Sun Feb 13 20:42:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Define fault objects to carry debug messages. These faults can panic/warn/warn_once, etc., instead of instructions doing that themselves directly. That way, instructions can be speculatively executed, and only if they're actually going to commit will their fault be invoked and the panic, etc., happen. |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | data.isa | 8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands. By using an underscore, the "." is still available and can unambiguously be used to refer to members of a structure if an operand is a structure, class, etc. This change mostly just replaces the appropriate "."s with "_"s, but there were also a few places where the ISA descriptions where handling the extensions themselves and had their own regular expressions to update. The regular expressions in the isa parser were updated as well. It also now looks for one of the defined type extensions specifically after connecting "_" where before it would look for any sequence of characters after a "." following an operand name and try to use it as the extension. This helps to disambiguate cases where a "_" may legitimately be part of an operand name but not separate the name from the type suffix. Because leaving the "_" and suffix on the variable name still leaves a valid C++ identifier and all extensions need to be consistent in a given context, I considered leaving them on as a breadcrumb that would show what the intended type was for that operand. Unfortunately the operands can be referred to in code templates, the Mem operand in particular, and since the exact type of Mem can be different for different uses of the same template, that broke things. 8305:a624d67b642c Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Generate condition code setting code based on which codes are set. This change further eliminates cases where condition codes were being read just so they could be written without change because the instruction in question was supposed to preserve them. This is done by creating the condition code code based on the input rather than just doing a simple substitution. 8304:16911ff780d3 Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Construct the predicate test register for more instruction programatically. If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before. 8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. 8302:9f23d01421de Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Remove the saturating (Q) condition code from the renamed register. Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit. 8301:858384f3af1c Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Break up condition codes into normal flags, saturation, and simd. This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags. 8285:c38905a6fa32 Wed May 04 21:38:00 EDT 2011 Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> ARM: Implement WFE/WFI/SEV semantics. 8205:7ecbffb674aa Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Cleanup implementation of ITSTATE and put important code in PCState. Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects. 8203:78b9f056d58a Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Tag appropriate instructions as IsReturn 7858:ee6641d7c713 Tue Jan 18 17:30:00 EST 2011 Matt.Horsnell <Matt.Horsnell@arm.com> O3: Fix itstate prediction and recovery. Any change of control flow now resets the itstate to 0 mask and 0 condition, except where the control flow alteration write into the cpsr register. These case, for example return from an iterrupt, require the predecoder to recover the itstate. As there is a window of opportunity between the return from an interrupt changing the control flow at the head of the pipe and the commit of the update to the CPSR, the predecoder needs to be able to grab the ITstate early. This is now handled by setting the forcedItState inside a PCstate for the control flow altering instruction. That instruction will have the correct mask/cond, but will not have a valid itstate until advancePC is called (note this happens to advance the execution). When the new PCstate is copy constructed it gets the itstate cond/mask, and upon advancing the PC the itstate becomes valid. Subsequent advancing invalidates the state and zeroes the cond/mask. This is handled in isolation for the ARM ISA and should have no impact on other ISAs. Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details. |
/gem5/src/mem/ruby/system/ | ||
H A D | SConscript | 8641:4d3ecac1abec Tue Dec 13 14:49:00 EST 2011 Nathan Binkert <nate@binkert.org> gcc: fix unused variable warnings from GCC 4.6.1 8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled. 8439:559ef3da5dac Fri Jul 01 17:29:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Commit files missing from previous commit The previous commit on functional access support in Ruby did not have some of the files required. This patch adds those files to the repository. 8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch. 8191:777459f7c61f Thu Mar 31 20:17:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: Add new object called WireBuffer to mimic a Wire. This is a substitute for MessageBuffers between controllers where you don't want messages to actually go through the Network, because requests/responses can always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered) because you are, after all, going through a network with contention. For systems where you model multiple controllers that are very tightly coupled and do not actually go through a network, it is a pain to have to write a coherence protocol to account for mixed up request/response orderings despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real MessageBuffers when messages do in fact go over a network. |
/gem5/src/dev/alpha/ | ||
H A D | backdoor.cc | 8789:a8b63a0ee14c Sun Nov 13 05:05:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in dev. 8741:491297d019f3 Fri Sep 30 03:29:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Remove System::platform and Platform::intrFrequency. In order for a system object to work in SE mode and FS mode, it has to either always require a platform object even in SE mode, or get rid of the requirement all together. Making SE mode carry around unnecessary/unused bits of FS seems less than ideal, so I decided to go with the second option. The platform pointer in the System class was used for exactly one purpose, a path for the Alpha Linux system object to get to the real time clock and read its frequency so that it could short cut the loops_per_jiffy calculation. There was also a copy and pasted implementation in MIPS, but since it was only there because it was there in Alpha I still count that as one use. This change reverses the mechanism that communicates the RTC frequency so that the Tsunami platform object pushes it up to the AlphaSystem object. This is slightly less specific than it could be because really only the AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform class was no longer necessary (and unimplemented on anything but Alpha) it was eliminated. After this change, a platform will need to have a system, but a system won't have to have a platform. 8739:925f15f96322 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the devices in SE mode. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
/gem5/configs/common/ | ||
H A D | Benchmarks.py | 8643:2f18d1ab589f Thu Dec 15 00:43:00 EST 2011 Anthony Gutierrez <atgutier@umich.edu> ARM: Update config files for Android/BBench images available on website. 8528:1f95c9a0bb2f Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add some MP regressions and clean up the disk images and kernels a bit 8212:134bd699967a Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Include IDE/CF controller by default in PBX model. Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38 8088:ac1bd3d1aa54 Thu Feb 24 05:14:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Configs: Explicitly import env in Benchmarks.py env was being implicitly imported into Benchmarks.py through SysPaths.py. This change brings it in explicitly in the file where it's used. 7869:e9edb137c872 Wed Feb 02 21:03:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Change how the default disk image gets set up. The disk image to use was always being forced to a particular value. This change changes what disk image is selected as the default based on the architecture being built. In the future, a more sophisticated system might be used that selected a path based on certain rules instead of relying on one off file names. |
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | RubySlicc_ComponentMapping.hh | 8608:02d7ac5fb855 Thu Nov 03 23:46:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove some unused typedefs This patch removes some of the unused typedefs. It also moves some of the typedefs from Global.hh to TypeDefines.hh. The patch also eliminates the file NodeID.hh. 8602:836f8fad4a4c Fri Oct 28 14:00:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Reorganize mapping of components In RubySlicc_ComponentMapping.hh, certain '#define's have been used for mapping MachineType to GenericMachineType. These '#define's are being eliminated and the code will now be generated by SLICC instead. Also are being eliminated some of the unused functions from RubySlicc_ComponentMapping.sm. 8485:7a9a7f2a3d46 Wed Aug 03 19:25:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove files and includes not in use 8456:5204873afc05 Wed Jul 06 21:45:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: added generic dma machine 8132:b0ecadb07742 Thu Mar 17 20:08:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: minor bugfix, line did not adhere to some macro usage conventions. |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | mem.isa | 8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1. And by "everything" I mean all the quick regressions. 8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason. 8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations. 8207:cad97f04eb91 Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix bug in MicroLdrNeon templates for initiateAcc(). 8205:7ecbffb674aa Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Cleanup implementation of ITSTATE and put important code in PCState. Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects. 8203:78b9f056d58a Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Tag appropriate instructions as IsReturn 8140:7449084b1612 Thu Mar 17 20:20:00 EDT 2011 Matt Horsnell <Matt.Horsnell@arm.com> ARM: Fix RFE macrop. This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes. 8072:128afe2b3a35 Wed Feb 23 16:10:00 EST 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> ARM: NEON instruction templates modified to set the predicate flag to false when needed. 7848:cc5e64f8423f Tue Jan 18 17:30:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for moving predicated false dest operands from sources. |
/gem5/src/arch/mips/ | ||
H A D | tlb.cc | 8767:e575781f71b8 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. 8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1. And by "everything" I mean all the quick regressions. 8575:02332ce6d7da Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Use inheritance to consolidate class definitions. 8573:be51bef13962 Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Consolidate TLB related faults. Pass in a bool to indicate if the fault is from a store instead of having two different classes. The classes were also misleadingly named since loads are also processed by the DTB but should return ITB faults since they aren't stores. The TLB may be returning the wrong fault in this case, but I haven't looked at it closely. 8570:ea93f18eead8 Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Consolidate the two AddressErrorFault variants. 8568:83f728db3332 Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Get rid of cruft in the fault classes. Get rid of Fault classes left over from when this file was copied from Alpha, and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of the old IntegerOverflowFault stub. The Integer version is what's actually in the manual, but the Arithmetic version had the implementation. 8567:d154cd83c353 Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Add constructors to the fault classes. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
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