Searched hist:14195 (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/cpu/pred/ | ||
| H A D | ltage.cc | 13433:fd8c49bea81f Fri Nov 09 18:12:00 EST 2018 Pau Cabre <pau.cabre@metempsy.com> cpu: Fix LTAGE max number of allocations on update The LTAGE paper states that only one TAGE entry can be allocated when updating Change-Id: I6cfb4d80ce835e93d4bf5099ef88a7d425abaddd Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14195 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/o3/ | ||
| H A D | fetch.hh | 14195:c5efdb3319aa Sat Aug 17 04:32:00 EDT 2019 Gabe Black <gabeblack@google.com> cpu: Move the instruction port into o3's fetch stage. That's where it's used, and that avoids having to pass it around using the top level getInstPort accessor. Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | cpu.hh | 14195:c5efdb3319aa Sat Aug 17 04:32:00 EDT 2019 Gabe Black <gabeblack@google.com> cpu: Move the instruction port into o3's fetch stage. That's where it's used, and that avoids having to pass it around using the top level getInstPort accessor. Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | cpu.cc | 14195:c5efdb3319aa Sat Aug 17 04:32:00 EDT 2019 Gabe Black <gabeblack@google.com> cpu: Move the instruction port into o3's fetch stage. That's where it's used, and that avoids having to pass it around using the top level getInstPort accessor. Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | fetch_impl.hh | 14195:c5efdb3319aa Sat Aug 17 04:32:00 EDT 2019 Gabe Black <gabeblack@google.com> cpu: Move the instruction port into o3's fetch stage. That's where it's used, and that avoids having to pass it around using the top level getInstPort accessor. Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> |
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