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/gem5/src/arch/arm/tracers/
H A Dtarmac_record.hh12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_base.hh12641:4c67bbebe381 Wed Mar 14 13:25:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace-based simulation

A new InstTracer (TarmacParser) has been implemented. This tracer is
parsing a pre-existing Tarmac trace file [1] while gem5 is running; it
is comparing execution data together with trace data and it is dumping
differences.
This allows to use Tarmac format as a glue between heterogeneous
simuators speaking the same Tarmac language.

Kudos to Giacomo Gabrielli for writing the original tracer.

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_record_v8.hh12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_base.cc12641:4c67bbebe381 Wed Mar 14 13:25:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace-based simulation

A new InstTracer (TarmacParser) has been implemented. This tracer is
parsing a pre-existing Tarmac trace file [1] while gem5 is running; it
is comparing execution data together with trace data and it is dumping
differences.
This allows to use Tarmac format as a glue between heterogeneous
simuators speaking the same Tarmac language.

Kudos to Giacomo Gabrielli for writing the original tracer.

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_tracer.hh12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_tracer.cc12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/gpu-compute/
H A Dcl_driver.hh13995:5d459168a680 Tue Aug 28 10:13:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> sim-se: change syscall function signature

The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.

With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.

This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.

Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/mem/cache/prefetch/
H A Dspatio_temporal_memory_streaming.cc13786:860c780d9f30 Thu Mar 07 10:13:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the STeMS prefetcher

Reference:
Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and
Babak Falsafi. 2009. Spatio-temporal memory streaming.
In Proceedings of the 36th annual international symposium on
Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80.

Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dspatio_temporal_memory_streaming.hh13786:860c780d9f30 Thu Mar 07 10:13:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the STeMS prefetcher

Reference:
Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and
Babak Falsafi. 2009. Spatio-temporal memory streaming.
In Proceedings of the 36th annual international symposium on
Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80.

Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dsignature_path_v2.cc13624:3d8220c2d41d Thu Dec 13 05:38:00 EST 2018 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Updated version of the Signature Path Prefetcher

This implementation is based in the description available in:
Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy,
Chris Wilkerson, and Zeshan Chishti. 2016.
Path confidence based lookahead prefetching.
In The 49th Annual IEEE/ACM International Symposium on Microarchitecture
(MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages.

Change-Id: I4b8b54efef48ced7044bd535de9a69bca68d47d9
Reviewed-on: https://gem5-review.googlesource.com/c/14819
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/mem/ruby/common/
H A DSet.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
6163:92318648212f Mon May 11 13:38:00 EDT 2009 Polina Dudnik <pdudnik@gmail.com> ruby: decommission code

1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory
6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/sim/
H A Dsyscall_desc.cc13995:5d459168a680 Tue Aug 28 10:13:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> sim-se: change syscall function signature

The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.

With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.

This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.

Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
13557:fc33e6048b25 Sat Oct 13 03:54:00 EDT 2018 Gabe Black <gabeblack@google.com> cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
11994:211df6a05c5e Tue May 02 13:56:00 EDT 2017 Alexandru Dutu <alexandru.dutu@amd.com> syscall_emul: Argument retrieval bug fix

This commit fixes a stack-buffer underflow
by fixing the way the array is indexed.

Change-Id: I44400e2b99a2f8e1f48f673cd110b9dcd6480a72
Reviewed-on: https://gem5-review.googlesource.com/3040
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
11877:5ea85692a53e Mon Jul 20 10:15:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> syscall_emul: [patch 13/22] add system call retry capability

This changeset adds functionality that allows system calls to retry without
affecting thread context state such as the program counter or register values
for the associated thread context (when system calls return with a retry
fault).

This functionality is needed to solve problems with blocking system calls
in multi-process or multi-threaded simulations where information is passed
between processes/threads. Blocking system calls can cause deadlock because
the simulator itself is single threaded. There is only a single thread
servicing the event queue which can cause deadlock if the thread hits a
blocking system call instruction.

To illustrate the problem, consider two processes using the producer/consumer
sharing model. The processes can use file descriptors and the read and write
calls to pass information to one another. If the consumer calls the blocking
read system call before the producer has produced anything, the call will
block the event queue (while executing the system call instruction) and
deadlock the simulation.

The solution implemented in this changeset is to recognize that the system
calls will block and then generate a special retry fault. The fault will
be sent back up through the function call chain until it is exposed to the
cpu model's pipeline where the fault becomes visible. The fault will trigger
the cpu model to replay the instruction at a future tick where the call has
a chance to succeed without actually going into a blocking state.

In subsequent patches, we recognize that a syscall will block by calling a
non-blocking poll (from inside the system call implementation) and checking
for events. When events show up during the poll, it signifies that the call
would not have blocked and the syscall is allowed to proceed (calling an
underlying host system call if necessary). If no events are returned from the
poll, we generate the fault and try the instruction for the thread context
at a distant tick. Note that retrying every tick is not efficient.

As an aside, the simulator has some multi-threading support for the event
queue, but it is not used by default and needs work. Even if the event queue
was completely multi-threaded, meaning that there is a hardware thread on
the host servicing a single simulator thread contexts with a 1:1 mapping
between them, it's still possible to run into deadlock due to the event queue
barriers on quantum boundaries. The solution of replaying at a later tick
is the simplest solution and solves the problem generally.
/gem5/src/arch/arm/isa/insts/
H A Damo64.isa14150:1391e94a7b95 Fri Jul 05 13:21:00 EDT 2019 Jordi Vaquero <jordi.vaquero@metempsy.com> arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func

CAS/CASP atomic instruction implementation
This change includes:
+ Instructions decode
+ new amo64.isa file where CAS/CASP main functional code is implemented
+ mem64.isa include Execute/complete/initiatie skeletons,
contructor and declarator
+ Added TypedAtomic function for pair register CASP instruction

Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19811
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/src/cpu/pred/
H A Dmultiperspective_perceptron.cc14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A Dmultiperspective_perceptron.hh14034:937e704c6807 Wed Feb 13 18:23:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/system/arm/dt/platforms/
H A Dvexpress_gem5_v1_base.dtsi12761:effd14bda656 Wed Jun 06 13:28:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> system-arm: Split the VExpress_GEM5_V1 base dts

With the introduction of the new DPU model, we need different
variations of the VExpress_GEM5_V1 platform. This splits the platform
dtsi file into a separate file for the base platform and the
HDLCD-based platform. This matches the hierarchy in RealView.py.

Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11035
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/src/base/stats/
H A Dtext.hh14205:197360deaa20 Wed Jun 26 13:58:00 EDT 2019 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add support for hierarchical stats

This change makes the stat system aware of the hierarchical nature of
stats. The aim is to achieve the following goals:

* Make the SimObject hierarchy explicit in the stat system (i.e.,
get rid of name() + ".foo"). This makes stat naming less fragile
and makes it possible to implement hierarchical formats like
XML/HDF5/JSON in a clean way.

* Make it more convenient to split stats into a separate
struct/class that can be bound to a SimObject. This makes the
namespace cleaner and makes stat accesses a bit more obvious.

* Make it possible to build groups of stats in C++ that can be used
in subcomponents in a SimObject (similar to what we do for
checkpoint sections). This makes it easier to structure large
components.

* Enable partial stat dumps. Some of our internal users have been
asking for this since a full stat dump can be large.

* Enable better stat access from Python.

This changeset implements solves the first three points by introducing
a class (Stats::Group) that owns statistics belonging to the same
object. SimObjects inherit from Stats::Group since they typically have
statistics.

New-style statistics need to be associated with a parent group at
instantiation time. Instantiation typically sets the name and the
description, other parameters need to be set by overriding
Group::regStats() just like with legacy stats. Simple objects with
scalar stats can typically avoid implementing regStats() altogether
since the stat name and description are both specified in the
constructor.

For convenience reasons, statistics groups can be merged into other
groups. This means that a SimObject can create a stat struct that
inherits from Stats::Group and merge it into the parent group
(SimObject). This can make the code cleaner since statistics tracking
gets grouped into a single object.

Stat visitors have a new API to expose the group structure. The
Output::beginGroup(name) method is called at the beginning of a group
and the Output::endGroup() method is called when all stats, and
sub-groups, have been visited. Flat formats (e.g., the text format)
typically need to maintain a stack to track the full path to a stat.

Legacy, flat, statistics are still supported after applying this
change. These stats don't belong to any group and stat visitors will
not see a Output::beginGroup(name) call before their corresponding
Output::visit() methods are called.

Change-Id: I9025d61dfadeabcc8ecf30813ab2060def455648
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19368
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
6126:5f32f9e3c65a Wed Apr 22 13:25:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: remove simplescalar compatibility for printing
4085:4df21265d806 Wed Feb 21 13:15:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Fix majory brokenness in my previous MySQL commit, basically
this is just a shuffling around of code and fixes to make
stuff commit properly
/gem5/src/arch/arm/kvm/
H A DBaseArmKvmCPU.py14212:c0575e785e98 Tue Aug 13 05:37:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arm,kvm: Fix python imports from global namespace

Change-Id: I31bd3563c2427efd7e520f714b1ca6f480fa4e85
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
H A DArmV8KvmCPU.py14212:c0575e785e98 Tue Aug 13 05:37:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arm,kvm: Fix python imports from global namespace

Change-Id: I31bd3563c2427efd7e520f714b1ca6f480fa4e85
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dmove.py5934:367ac7cae7b5 Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make rdcr use merge and the mov to control register instructions use the right operand size.
5931:d42d507ccdb1 Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the mov to debug register intructions.
5928:410d14f82f13 Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a few bugs with the segment register instructions in real mode.
Fix a few instances where the register form of zext was used where zexti was
intended. Also get rid of the 64 bit only rip relative addressed version since
64 bit and real mode are mutually exclusive.
5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop.
/gem5/src/base/filters/
H A Dbase.hh14264:f150b10dd048 Tue May 14 13:38:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Make Bloom Filter counting by default

Since a boolean bool filter is a saturating bloom filter with a
single bit per entry, generalize them by using SatCounter instead
of int for the filter entries.

Change-Id: I7f54e28d54de5671e0770b02ed9161735e6bd339
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18877
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dblock_bloom_filter.cc14264:f150b10dd048 Tue May 14 13:38:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Make Bloom Filter counting by default

Since a boolean bool filter is a saturating bloom filter with a
single bit per entry, generalize them by using SatCounter instead
of int for the filter entries.

Change-Id: I7f54e28d54de5671e0770b02ed9161735e6bd339
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18877
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dmulti_bit_sel_bloom_filter.cc14264:f150b10dd048 Tue May 14 13:38:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Make Bloom Filter counting by default

Since a boolean bool filter is a saturating bloom filter with a
single bit per entry, generalize them by using SatCounter instead
of int for the filter entries.

Change-Id: I7f54e28d54de5671e0770b02ed9161735e6bd339
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18877
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/mem/cache/compressors/
H A Dbdi.cc13944:5000533e6b81 Wed Jun 13 10:39:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create BDI Compressor

Implement Base-Delta-Immediate compression, as described in
'Base-Delta-Immediate Compression: Practical Data Compression
for On-Chip Caches'

Change-Id: I7980c340ab53a086b748f4b2108de4adc775fac8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11412
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/arch/x86/linux/
H A Dlinux.hh11759:deaf82fd2e7c Thu Dec 15 13:16:00 EST 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add support for x86 statfs system calls
11386:94c09b607a84 Thu Mar 17 13:29:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: move mmapGrowsDown() to LiveProcess

The mmapGrowsDown() method was a static method on the OperatingSystem
class (and derived classes), which worked OK for the templated syscall
emulation methods, but made it hard to access elsewhere. This patch
moves the method to be a virtual function on the LiveProcess method,
where it can be overridden for specific platforms (for now, Alpha).

This patch also changes the value of mmapGrowsDown() from being false
by default and true only on X86Linux32 to being true by default and
false only on Alpha, which seems closer to reality (though in reality
most people use ASLR and this doesn't really matter anymore).

In the process, also got rid of the unused mmap_start field on
LiveProcess and OperatingSystem mmapGrowsUp variable.
11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags
11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.

Completed in 74 milliseconds

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