112761Sandreas.sandberg@arm.com/* 212761Sandreas.sandberg@arm.com * Copyright (c) 2015-2017 ARM Limited 312761Sandreas.sandberg@arm.com * All rights reserved 412761Sandreas.sandberg@arm.com * 512761Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 612761Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 712761Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 812761Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 912761Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1012761Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1112761Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1212761Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1312761Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1412761Sandreas.sandberg@arm.com * this software without specific prior written permission. 1512761Sandreas.sandberg@arm.com * 1612761Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712761Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812761Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912761Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012761Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112761Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212761Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312761Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412761Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512761Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612761Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712761Sandreas.sandberg@arm.com * 2812761Sandreas.sandberg@arm.com * Authors: Andreas Sandberg 2912761Sandreas.sandberg@arm.com */ 3012761Sandreas.sandberg@arm.com 3112761Sandreas.sandberg@arm.com/ { 3212761Sandreas.sandberg@arm.com arm,hbi = <0x0>; 3312761Sandreas.sandberg@arm.com arm,vexpress,site = <0xf>; 3412761Sandreas.sandberg@arm.com interrupt-parent = <&gic>; 3512761Sandreas.sandberg@arm.com #address-cells = <2>; 3612761Sandreas.sandberg@arm.com #size-cells = <2>; 3712761Sandreas.sandberg@arm.com 3812761Sandreas.sandberg@arm.com gic: interrupt-controller@2c001000 { 3912761Sandreas.sandberg@arm.com compatible = "gem5,gic", "arm,gic-400"; 4012761Sandreas.sandberg@arm.com #interrupt-cells = <3>; 4112761Sandreas.sandberg@arm.com #address-cells = <0>; 4212761Sandreas.sandberg@arm.com interrupt-controller; 4312761Sandreas.sandberg@arm.com reg = <0 0x2c001000 0 0x1000>, 4412761Sandreas.sandberg@arm.com <0 0x2c002000 0 0x1000>, 4512761Sandreas.sandberg@arm.com <0 0x2c004000 0 0x2000>, 4612761Sandreas.sandberg@arm.com <0 0x2c006000 0 0x2000>; 4712761Sandreas.sandberg@arm.com interrupts = <1 9 0xf04>; 4812761Sandreas.sandberg@arm.com }; 4912761Sandreas.sandberg@arm.com 5012761Sandreas.sandberg@arm.com 5112761Sandreas.sandberg@arm.com timer { 5212761Sandreas.sandberg@arm.com compatible = "arm,cortex-a15-timer", 5312761Sandreas.sandberg@arm.com "arm,armv7-timer"; 5412761Sandreas.sandberg@arm.com interrupts = <1 13 0xf08>, 5512761Sandreas.sandberg@arm.com <1 14 0xf08>, 5614114Schunchenhsu@google.com <1 11 0xf08>, 5714114Schunchenhsu@google.com <1 10 0xf08>; 5812761Sandreas.sandberg@arm.com clocks = <&osc_sys>; 5912761Sandreas.sandberg@arm.com clock-names="apb_pclk"; 6012761Sandreas.sandberg@arm.com }; 6112761Sandreas.sandberg@arm.com 6212761Sandreas.sandberg@arm.com pci { 6312761Sandreas.sandberg@arm.com compatible = "pci-host-ecam-generic"; 6412761Sandreas.sandberg@arm.com device_type = "pci"; 6512761Sandreas.sandberg@arm.com #address-cells = <0x3>; 6612761Sandreas.sandberg@arm.com #size-cells = <0x2>; 6712761Sandreas.sandberg@arm.com #interrupt-cells = <0x1>; 6812761Sandreas.sandberg@arm.com 6912761Sandreas.sandberg@arm.com reg = <0x0 0x30000000 0x0 0x10000000>; 7012761Sandreas.sandberg@arm.com 7112761Sandreas.sandberg@arm.com ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x00010000>, 7212761Sandreas.sandberg@arm.com <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 7312761Sandreas.sandberg@arm.com 7412761Sandreas.sandberg@arm.com interrupt-map = <0x000000 0x0 0x0 0 &gic 0 68 1>, 7512761Sandreas.sandberg@arm.com <0x000800 0x0 0x0 0 &gic 0 69 1>, 7612761Sandreas.sandberg@arm.com <0x001000 0x0 0x0 0 &gic 0 70 1>, 7712761Sandreas.sandberg@arm.com <0x001800 0x0 0x0 0 &gic 0 71 1>; 7812761Sandreas.sandberg@arm.com 7912761Sandreas.sandberg@arm.com interrupt-map-mask = <0x001800 0x0 0x0 0x0>; 8012761Sandreas.sandberg@arm.com dma-coherent; 8112761Sandreas.sandberg@arm.com }; 8212761Sandreas.sandberg@arm.com 8312761Sandreas.sandberg@arm.com kmi@1c060000 { 8412761Sandreas.sandberg@arm.com compatible = "arm,pl050", "arm,primecell"; 8512761Sandreas.sandberg@arm.com reg = <0x0 0x1c060000 0x0 0x1000>; 8612761Sandreas.sandberg@arm.com interrupts = <0 12 4>; 8712761Sandreas.sandberg@arm.com clocks = <&v2m_clk24mhz>, <&osc_smb>; 8812761Sandreas.sandberg@arm.com clock-names = "KMIREFCLK", "apb_pclk"; 8912761Sandreas.sandberg@arm.com }; 9012761Sandreas.sandberg@arm.com 9112761Sandreas.sandberg@arm.com kmi@1c070000 { 9212761Sandreas.sandberg@arm.com compatible = "arm,pl050", "arm,primecell"; 9312761Sandreas.sandberg@arm.com reg = <0x0 0x1c070000 0x0 0x1000>; 9412761Sandreas.sandberg@arm.com interrupts = <0 13 4>; 9512761Sandreas.sandberg@arm.com clocks = <&v2m_clk24mhz>, <&osc_smb>; 9612761Sandreas.sandberg@arm.com clock-names = "KMIREFCLK", "apb_pclk"; 9712761Sandreas.sandberg@arm.com }; 9812761Sandreas.sandberg@arm.com 9912761Sandreas.sandberg@arm.com uart0: uart@1c090000 { 10012761Sandreas.sandberg@arm.com compatible = "arm,pl011", "arm,primecell"; 10112761Sandreas.sandberg@arm.com reg = <0x0 0x1c090000 0x0 0x1000>; 10212761Sandreas.sandberg@arm.com interrupts = <0 5 4>; 10312761Sandreas.sandberg@arm.com clocks = <&osc_peripheral>, <&osc_smb>; 10412761Sandreas.sandberg@arm.com clock-names = "uartclk", "apb_pclk"; 10512761Sandreas.sandberg@arm.com }; 10612761Sandreas.sandberg@arm.com 10712761Sandreas.sandberg@arm.com rtc@1c170000 { 10812761Sandreas.sandberg@arm.com compatible = "arm,pl031", "arm,primecell"; 10912761Sandreas.sandberg@arm.com reg = <0x0 0x1c170000 0x0 0x1000>; 11012761Sandreas.sandberg@arm.com interrupts = <0 4 4>; 11112761Sandreas.sandberg@arm.com clocks = <&osc_smb>; 11212761Sandreas.sandberg@arm.com clock-names = "apb_pclk"; 11312761Sandreas.sandberg@arm.com }; 11412761Sandreas.sandberg@arm.com 11512761Sandreas.sandberg@arm.com v2m_clk24mhz: clk24mhz { 11612761Sandreas.sandberg@arm.com compatible = "fixed-clock"; 11712761Sandreas.sandberg@arm.com #clock-cells = <0>; 11812761Sandreas.sandberg@arm.com clock-frequency = <24000000>; 11912761Sandreas.sandberg@arm.com clock-output-names = "v2m:clk24mhz"; 12012761Sandreas.sandberg@arm.com }; 12112761Sandreas.sandberg@arm.com 12212761Sandreas.sandberg@arm.com 12312761Sandreas.sandberg@arm.com v2m_sysreg: sysreg@1c010000 { 12412761Sandreas.sandberg@arm.com compatible = "arm,vexpress-sysreg"; 12512761Sandreas.sandberg@arm.com reg = <0 0x1c010000 0x0 0x1000>; 12612761Sandreas.sandberg@arm.com gpio-controller; 12712761Sandreas.sandberg@arm.com #gpio-cells = <2>; 12812761Sandreas.sandberg@arm.com }; 12912761Sandreas.sandberg@arm.com 13012761Sandreas.sandberg@arm.com vio@1c130000 { 13112761Sandreas.sandberg@arm.com compatible = "virtio,mmio"; 13212761Sandreas.sandberg@arm.com reg = <0 0x1c130000 0x0 0x1000>; 13312761Sandreas.sandberg@arm.com interrupts = <0 42 4>; 13412761Sandreas.sandberg@arm.com }; 13512761Sandreas.sandberg@arm.com 13612761Sandreas.sandberg@arm.com vio@1c140000 { 13712761Sandreas.sandberg@arm.com compatible = "virtio,mmio"; 13812761Sandreas.sandberg@arm.com reg = <0 0x1c140000 0x0 0x1000>; 13912761Sandreas.sandberg@arm.com interrupts = <0 43 4>; 14012761Sandreas.sandberg@arm.com }; 14112761Sandreas.sandberg@arm.com 14212761Sandreas.sandberg@arm.com dcc { 14312761Sandreas.sandberg@arm.com compatible = "arm,vexpress,config-bus"; 14412761Sandreas.sandberg@arm.com arm,vexpress,config-bridge = <&v2m_sysreg>; 14512761Sandreas.sandberg@arm.com 14612761Sandreas.sandberg@arm.com osc_pxl: osc@5 { 14712761Sandreas.sandberg@arm.com compatible = "arm,vexpress-osc"; 14812761Sandreas.sandberg@arm.com arm,vexpress-sysreg,func = <1 5>; 14912761Sandreas.sandberg@arm.com freq-range = <23750000 1000000000>; 15012761Sandreas.sandberg@arm.com #clock-cells = <0>; 15112761Sandreas.sandberg@arm.com clock-output-names = "oscclk5"; 15212761Sandreas.sandberg@arm.com }; 15312761Sandreas.sandberg@arm.com 15412761Sandreas.sandberg@arm.com osc_smb: osc@6 { 15512761Sandreas.sandberg@arm.com compatible = "arm,vexpress-osc"; 15612761Sandreas.sandberg@arm.com arm,vexpress-sysreg,func = <1 6>; 15712761Sandreas.sandberg@arm.com freq-range = <20000000 50000000>; 15812761Sandreas.sandberg@arm.com #clock-cells = <0>; 15912761Sandreas.sandberg@arm.com clock-output-names = "oscclk6"; 16012761Sandreas.sandberg@arm.com }; 16112761Sandreas.sandberg@arm.com 16212761Sandreas.sandberg@arm.com osc_sys: osc@7 { 16312761Sandreas.sandberg@arm.com compatible = "arm,vexpress-osc"; 16412761Sandreas.sandberg@arm.com arm,vexpress-sysreg,func = <1 7>; 16512761Sandreas.sandberg@arm.com freq-range = <20000000 60000000>; 16612761Sandreas.sandberg@arm.com #clock-cells = <0>; 16712761Sandreas.sandberg@arm.com clock-output-names = "oscclk7"; 16812761Sandreas.sandberg@arm.com }; 16912761Sandreas.sandberg@arm.com }; 17012761Sandreas.sandberg@arm.com 17112761Sandreas.sandberg@arm.com 17212761Sandreas.sandberg@arm.com mcc { 17312761Sandreas.sandberg@arm.com compatible = "arm,vexpress,config-bus"; 17412761Sandreas.sandberg@arm.com arm,vexpress,config-bridge = <&v2m_sysreg>; 17512761Sandreas.sandberg@arm.com arm,vexpress,site = <0>; 17612761Sandreas.sandberg@arm.com 17712761Sandreas.sandberg@arm.com osc_peripheral: osc@2 { 17812761Sandreas.sandberg@arm.com compatible = "arm,vexpress-osc"; 17912761Sandreas.sandberg@arm.com arm,vexpress-sysreg,func = <1 2>; 18012761Sandreas.sandberg@arm.com freq-range = <24000000 24000000>; 18112761Sandreas.sandberg@arm.com #clock-cells = <0>; 18212761Sandreas.sandberg@arm.com clock-output-names = "v2m:oscclk2"; 18312761Sandreas.sandberg@arm.com }; 18412761Sandreas.sandberg@arm.com }; 18512761Sandreas.sandberg@arm.com}; 186