1/* 2 * Copyright (c) 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Giacomo Travaglini 38 */ 39 40#include "tarmac_tracer.hh" 41 42#include <string> 43 44#include "arch/arm/system.hh" 45#include "cpu/base.hh" 46 47namespace Trace { 48 49std::string 50TarmacContext::tarmacCpuName() const 51{ 52 auto id = thread->getCpuPtr()->cpuId(); 53 return "cpu" + std::to_string(id); 54} 55 56TarmacTracer::TarmacTracer(const Params *p) 57 : InstTracer(p), 58 startTick(p->start_tick), 59 endTick(p->end_tick) 60{ 61 // Wrong parameter setting: The trace end happens before the 62 // trace start. 63 panic_if(startTick > endTick, 64 "Tarmac start point: %lu is bigger than " 65 "Tarmac end point: %lu\n", startTick, endTick); 66 67 // By default cpu tracers in gem5 are not tracing faults 68 // (exceptions). 69 // This is not in compliance with the Tarmac specification: 70 // instructions like SVC, SMC, HVC have to be traced. 71 // Tarmac Tracer is then automatically enabling this behaviour. 72 setDebugFlag("ExecFaulting"); 73} 74 75InstRecord * 76TarmacTracer::getInstRecord(Tick when, ThreadContext *tc, 77 const StaticInstPtr staticInst, 78 ArmISA::PCState pc, 79 const StaticInstPtr macroStaticInst) 80{ 81 // Check if we need to start tracing since we have passed the 82 // tick start point. 83 if (when < startTick || when > endTick) 84 return nullptr; 85 86 if (ArmSystem::highestELIs64(tc)) { 87 // TarmacTracerV8 88 return new TarmacTracerRecordV8(when, tc, staticInst, pc, *this, 89 macroStaticInst); 90 } else { 91 // TarmacTracer 92 return new TarmacTracerRecord(when, tc, staticInst, pc, *this, 93 macroStaticInst); 94 } 95} 96 97} // namespace Trace 98 99Trace::TarmacTracer * 100TarmacTracerParams::create() 101{ 102 return new Trace::TarmacTracer(this); 103} 104