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/gem5/src/base/
H A Dstr.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
H A Dcp_annotate.cc8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/cpu/
H A DCheckerCPU.py5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc13557:fc33e6048b25 Sat Oct 13 03:54:00 EDT 2018 Gabe Black <gabeblack@google.com> cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
12392:e0dbdf30a2a5 Wed Dec 13 13:19:00 EST 2017 Jason Lowe-Power <jason@lowepower.com> misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
12392:e0dbdf30a2a5 Wed Dec 13 13:19:00 EST 2017 Jason Lowe-Power <jason@lowepower.com> misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
11629:22f08c96bf7f Tue Sep 13 23:20:00 EDT 2016 Michael LeBeane <michael.lebeane@amd.com> kvm: Support timing accesses for KVM cpu
This patch enables timing accesses for KVM cpu. A new state,
RunningMMIOPending, is added to indicate that there are outstanding timing
requests generated by KVM in the system. KVM's tick() is disabled and the
simulation does not enter into KVM until all outstanding timing requests have
completed. The main motivation for this is to allow KVM CPU to perform MMIO
in Ruby, since Ruby does not support atomic accesses.
/gem5/src/cpu/o3/
H A DO3Checker.py5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
/gem5/src/cpu/simple/
H A DBaseSimpleCPU.py10785:f56c10663a01 Mon Apr 13 18:33:00 EDT 2015 Dibakar Gope <gope@wisc.edu> cpu: re-organizes the branch predictor structure.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
/gem5/src/cpu/testers/traffic_gen/
H A DTrafficGen.py12810:485ca1c27812 Thu Apr 26 13:16:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Split the traffic generator into two classes

The traffic generator currently assumes that it is always driven from
a configuration file. Split it into a base class (BaseTrafficGen) that
handles basic packet generation and a derived class that implements
the config handling (TrafficGen).

Change-Id: I9407f04c40ad7e40a263c8d1ef29d37ff8e6f1b4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11515
H A DBaseTrafficGen.py12810:485ca1c27812 Thu Apr 26 13:16:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Split the traffic generator into two classes

The traffic generator currently assumes that it is always driven from
a configuration file. Split it into a base class (BaseTrafficGen) that
handles basic packet generation and a derived class that implements
the config handling (TrafficGen).

Change-Id: I9407f04c40ad7e40a263c8d1ef29d37ff8e6f1b4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11515
/gem5/src/dev/net/
H A Detherswitch.cc11317:766c3eb44fd8 Sat Feb 06 13:33:00 EST 2016 Mohammad Alian <m.alian1369@gmail.com> dist, dev: add an ethernet switch model
H A Dsinic.cc11719:e832056deaed Tue Nov 29 13:04:00 EST 2016 Michael LeBeane <michael.lebeane@amd.com> dev: Fix buffer length when unserializing an eth pkt

Changeset 11701 only serialized the useful portion of of an ethernet packets'
payload. However, the device models expect each ethernet packet to contain
a 16KB buffer, even if there is no data in it. This patch adds a 'bufLength'
field to EthPacketData so the original size of the packet buffer can always
be unserialized.

Reported-by: Gabor Dozsa <Gabor.Dozsa@arm.com>
/gem5/src/mem/slicc/ast/
H A DPeekStatementAST.py8641:4d3ecac1abec Tue Dec 13 14:49:00 EST 2011 Nathan Binkert <nate@binkert.org> gcc: fix unused variable warnings from GCC 4.6.1
/gem5/src/python/m5/
H A Ddebug.py8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
/gem5/src/python/m5/util/
H A Djobfile.py5618:1abb23c038d5 Fri Oct 10 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> jobfile: Add support for dictionaries as jobfile options.
If the same dictionary option is seen in several options, those
dictionaries are composed. If you define the same dictionary key in
multiple options, the system flags an error.
Also, clean up the jobfile code so that it is more debuggable.
/gem5/src/sim/
H A Dinit.cc13620:e0d9b09788f6 Fri Jan 25 06:13:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> sim: Prepare C++ side for Python 3

Python 3 uses wide strings instead of ordinary strings for many
APIs. Add the necessary conversions to comply with the new API.

Change-Id: I6f45c9c532537d50d54b542f34eb8fd8cb375874
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15977
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
9397:6e6b8d8ab258 Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> base: Add wrapped protobuf output streams

This patch adds support for outputting protobuf messages through a
ProtoOutputStream which hides the internal streams used by the
library. The stream is created based on the name of an output file and
optionally includes compression using gzip.

The output stream will start by putting a magic number in the file,
and then for every message that is serialized prepend the size such
that the stream can be written and read incrementally. At this point
this merely serves as a proof of concept.
8234:a08c5fb4cd89 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> python: cleanup python code so stuff doesn't automatically happen at startup
this allows things to be overridden at startup (e.g. for tests)
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/systemc/ext/channel/
H A Dsc_in.hh13054:bce8a8124325 Mon Aug 13 21:20:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement the sc_in class.

Change-Id: I08174462cb650c7918a4e8f5284d4ee814cf595d
Reviewed-on: https://gem5-review.googlesource.com/12085
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/configs/common/
H A DCacheConfig.py9036:6385cf85bf12 Thu May 31 13:30:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Bus: Split the bus into a non-coherent and coherent bus

This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.
8839:eeb293859255 Mon Feb 13 06:43:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
6981:aba5f7216636 Thu Feb 25 13:13:00 EST 2010 Lisa Hsu <Lisa.Hsu@amd.com> configs: pull out cache configuration code from se.py and fs.py.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
6981:aba5f7216636 Thu Feb 25 13:13:00 EST 2010 Lisa Hsu <Lisa.Hsu@amd.com> configs: pull out cache configuration code from se.py and fs.py.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
/gem5/src/arch/arm/insts/
H A Dvfp.cc11671:520509f3e66c Thu Oct 13 14:22:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> isa,arm: Add missing AArch32 FP instructions

This commit adds missing non-predicated, scalar floating point
instructions. Specifically VRINT* floating point integer rounding
instructions and VSEL* floating point conditional selects.

Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
/gem5/src/arch/arm/freebsd/
H A Dprocess.cc13995:5d459168a680 Tue Aug 28 10:13:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> sim-se: change syscall function signature

The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.

With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.

This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.

Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc12641:4c67bbebe381 Wed Mar 14 13:25:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace-based simulation

A new InstTracer (TarmacParser) has been implemented. This tracer is
parsing a pre-existing Tarmac trace file [1] while gem5 is running; it
is comparing execution data together with trace data and it is dumping
differences.
This allows to use Tarmac format as a glue between heterogeneous
simuators speaking the same Tarmac language.

Kudos to Giacomo Gabrielli for writing the original tracer.

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/testers/memtest/
H A Dmemtest.hh13799:15badf7874ee Tue Mar 19 13:12:00 EDT 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> misc: missing override specifier

Missing specifier of overridden virtual function
declared in sim_object.hh

Removed redundant "virtual" keyword

Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
12085:de78ea63e0ca Wed Jun 07 01:13:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper

Change-Id: Idd5992463bcf9154f823b82461070d1f1842cea3
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3746
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
8975:7f36d4436074 Tue May 01 13:40:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Separate requests and responses for timing accesses

This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.

For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).

The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.

With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.py8839:eeb293859255 Mon Feb 13 06:43:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
/gem5/src/gpu-compute/
H A Dcl_driver.cc13995:5d459168a680 Tue Aug 28 10:13:00 EDT 2018 Brandon Potter <brandon.potter@amd.com> sim-se: change syscall function signature

The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.

With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.

This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.

Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/mem/
H A DDRAMCtrl.py11679:4aa51b4a2f24 Thu Oct 13 14:22:00 EDT 2016 Omar Naji <Omar.Naji@arm.com> mem: add DRAM powerdown current

Change-Id: I763cffe0c69f5ebbbf6a6eb12bec5c13d5d0161d
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
11674:b4015b449dd3 Thu Oct 13 14:22:00 EDT 2016 Omar Naji <Omar.Naji@arm.com> mem: update DDR3 die revision

Change-Id: I8992ddc1664c3ed4b2d36d8a34e4ce8be113b9de
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
11673:9f3ccf96bb5a Thu Oct 13 14:22:00 EDT 2016 Omar Naji <Omar.Naji@arm.com> mem: add DRAM powerdown timing
11672:55276af429ed Thu Oct 13 14:22:00 EDT 2016 Omar Naji <Omar.Naji@arm.com> mem: make DDR4 x16
H A Daddr_mapper.hh13799:15badf7874ee Tue Mar 19 13:12:00 EDT 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> misc: missing override specifier

Missing specifier of overridden virtual function
declared in sim_object.hh

Removed redundant "virtual" keyword

Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dmem_delay.hh12823:ba630bc7a36d Thu Jul 19 13:56:00 EDT 2018 Robert Kovacsics <rmk35@cl.cam.ac.uk> mem: Rename Packet::checkFunctional to trySatisfyFunctional

Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

Completed in 112 milliseconds

<<51525354555657585960>>