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13675:afeab32b3655 |
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24-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Replace dict.has_key with 'key in dict'
Python 3 has removed dict.has_key in favour of 'key in dict'.
Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15987 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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11111:6da33e720481 |
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16-Sep-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: message buffer, timer table: significant changes
This patch changes MessageBuffer and TimerTable, two structures used for buffering messages by components in ruby. These structures would no longer maintain pointers to clock objects. Functions in these structures have been changed to take as input current time in Tick. Similarly, these structures will not operate on Cycle valued latencies for different operations. The corresponding functions would need to be provided with these latencies by components invoking the relevant functions. These latencies should also be in Ticks.
I felt the need for these changes while trying to speed up ruby. The ultimate aim is to eliminate Consumer class and replace it with an EventManager object in the MessageBuffer and TimerTable classes. This object would be used for scheduling events. The event itself would contain information on the object and function to be invoked.
In hindsight, it seems I should have done this while I was moving away from use of a single global clock in the memory system. That change led to introduction of clock objects that replaced the global clock object. It never crossed my mind that having clock object pointers is not a good design. And now I really don't like the fact that we have separate consumer, receiver and sender pointers in message buffers.
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10967:b36204de88c0 |
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20-Jul-2015 |
David Hashe <david.hashe@amd.com> |
slicc: Fix bug in enqueue and peek statements.
These were not generating the correct c names for types declared within a machine scope.
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10963:51f40b101a56 |
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20-Jul-2015 |
David Hashe <david.hashe@amd.com> |
slicc: support for multiple message types on the same buffer
This patch allows SLICC protocols to use more than one message type with a message buffer. For example, you can declare two in ports as such:
in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... } in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }
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10231:cb2e6950956d |
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31-May-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: eliminate equality tests with true and false
Using '== true' in a boolean expression is totally redundant, and using '== false' is pretty verbose (and arguably less readable in most cases) compared to '!'.
It's somewhat of a pet peeve, perhaps, but I had some time waiting for some tests to run and decided to clean these up.
Unfortunately, SLICC appears not to have the '!' operator, so I had to leave the '== false' tests in the SLICC code.
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8641:4d3ecac1abec |
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13-Dec-2011 |
Nathan Binkert <nate@binkert.org> |
gcc: fix unused variable warnings from GCC 4.6.1
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7567:238f99c9f441 |
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20-Aug-2010 |
Brad Beckmann <Brad.Beckmann@amd.com> |
ruby: Stall and wait input messages instead of recycling
This patch allows messages to be stalled in their input buffers and wait until a corresponding address changes state. In order to make this work, all in_ports must be ranked in order of dependence and those in_ports that may unblock an address, must wake up the stalled messages. Alot of this complexity is handled in slicc and the specification files simply annotate the in_ports.
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7007:79413d1ec307 |
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12-Mar-2010 |
Nathan Binkert <nate@binkert.org> |
slicc: Change the code generation so that the generated code is easier to read
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6863:21fbf0412e0d |
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19-Jan-2010 |
Derek Hower <drh5@cs.wisc.edu> |
ruby: new atomics implementation
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
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6657:ef5fae93a3b2 |
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22-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur".
Slicc can easily be run manually by using util/slicc
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