Searched hist:13 (Results 1026 - 1050 of 1864) sorted by relevance
/gem5/src/arch/alpha/ | ||
H A D | remote_gdb.hh | 8931:7a1dfb191e3f Fri Apr 06 13:46:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Enable multiple distributed generalized memories This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/arch/mips/ | ||
H A D | remote_gdb.hh | 8931:7a1dfb191e3f Fri Apr 06 13:46:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Enable multiple distributed generalized memories This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
H A D | MipsSystem.py | 10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5 Adds DVFS capabilities to gem5, by allowing users to specify lists for frequencies and voltages in SrcClockDomains and VoltageDomains respectively. A separate component, DVFSHandler, provides a small interface to change operating points of the associated domains. Clock domains will be linked to voltage domains and thus allow separate clock, but shared voltage lines. Currently all the valid performance-level updates are performed with a fixed transition latency as specified for the domain. Config file example: ... vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V']) tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] tsys.cluster1.clk_domain.domain_id = 0 tsys.cluster2.clk_domain.domain_id = 1 tsys.cluster1.clk_domain.voltage_domain = vd tsys.cluster2.clk_domain.voltage_domain = vd tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain, tsys.cluster2.clk_domain] tsys.dvfs_handler.enable = True 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
/gem5/src/systemc/ext/core/ | ||
H A D | sc_process_handle.hh | 12994:afce27405f70 Sat Jul 21 01:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Fix a "problem" with kill/reset exceptions. Despite what it says in the spec, the proc_ctrl compliance test throws a copy of the reset exception it catches, not the original. Because of that, the code in the kernel which catches the exception gets the base class, not the derived class with overridden virtual methods, etc. This happens to work for the Accellera implementation because they manipulate members of the base class itself which are preserved despite this bug. To make the test work, we imitate their implementation, even though it exposes more implementation details through the header files. Change-Id: I7ed9818c0552869ec790cb7f7bfbe365ade5e49c Reviewed-on: https://gem5-review.googlesource.com/12045 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> 12898:9c24286c7ddb Wed Jun 13 23:09:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add some "implementation defined" stuff to sc_attr_cltn. These "impelementation defined" methods are tested by the regression tests, so we need to have them. We might as well have the same general interface as the Accellera implementation since nothing there seems overly specialized for that environment. Change-Id: Ief6567fcd9d99d3a0f526cfa3b65043b2c828efa Reviewed-on: https://gem5-review.googlesource.com/11185 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/systemc/ext/utils/ | ||
H A D | sc_report_handler.hh | 12875:13f9e1b80121 Wed Jun 13 21:25:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Turn some macros into enums to fix regression test building. The spec defines these constants to be macros, but the regression test refers to them using the sc_core namespace. That breaks things because the macros don't expand to an identifier, they expand to an expression. This change converts the macros into enums like in the Accellera implementation to get the regression tests to build. Change-Id: I3db7dc87a7a597907df658624a7343bc6ca1734e Reviewed-on: https://gem5-review.googlesource.com/11180 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> 12875:13f9e1b80121 Wed Jun 13 21:25:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Turn some macros into enums to fix regression test building. The spec defines these constants to be macros, but the regression test refers to them using the sc_core namespace. That breaks things because the macros don't expand to an identifier, they expand to an expression. This change converts the macros into enums like in the Accellera implementation to get the regression tests to build. Change-Id: I3db7dc87a7a597907df658624a7343bc6ca1734e Reviewed-on: https://gem5-review.googlesource.com/11180 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | vfp.isa | 11671:520509f3e66c Thu Oct 13 14:22:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> isa,arm: Add missing AArch32 FP instructions This commit adds missing non-predicated, scalar floating point instructions. Specifically VRINT* floating point integer rounding instructions and VSEL* floating point conditional selects. Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com> 8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. |
/gem5/src/arch/riscv/ | ||
H A D | utility.hh | 12808:f275fd1244ce Tue Mar 13 09:29:00 EDT 2018 Robert <robert.scheffel1@tu-dresden.de> arch-riscv: enable rudimentary fs simulation These changes enable a simple binary to be simulated in full system mode. Additionally, a new fault was implemented. It is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to a reset vector. Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88 Reviewed-on: https://gem5-review.googlesource.com/9061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 12136:1070125670e2 Thu Jul 13 14:24:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
H A D | interrupts.hh | 13548:b76f99d052bb Fri Jul 13 10:48:00 EDT 2018 Alec Roelke <alec.roelke@gmail.com> arch-riscv: Add interrupt handling Implement the Interrupts SimObject for RISC-V. This basically just handles setting and getting the values of the interrupt-pending and interrupt-enable CSRs according to the privileged ISA reference chapter 3.1.14. Note that it does NOT implement the PLIC as defined in chapter 7, as that is used for handling external interrupts which are defined based on peripherals that are available. Change-Id: Ia1321430f870ff5a3950217266fde0511332485b Reviewed-on: https://gem5-review.googlesource.com/c/14377 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 12808:f275fd1244ce Tue Mar 13 09:29:00 EDT 2018 Robert <robert.scheffel1@tu-dresden.de> arch-riscv: enable rudimentary fs simulation These changes enable a simple binary to be simulated in full system mode. Additionally, a new fault was implemented. It is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to a reset vector. Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88 Reviewed-on: https://gem5-review.googlesource.com/9061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
H A D | isa.cc | 13935:02b924bd5ee9 Sun Mar 03 15:13:00 EST 2019 Alec Roelke <alec.roelke@gmail.com> arch-riscv: Implement MHARTID CSR This patch implements the MHARTID CSR by intercepting attempts to access it, similar to the way accesses to the performance counters are intercepted, to return the thread's context ID. Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> 13548:b76f99d052bb Fri Jul 13 10:48:00 EDT 2018 Alec Roelke <alec.roelke@gmail.com> arch-riscv: Add interrupt handling Implement the Interrupts SimObject for RISC-V. This basically just handles setting and getting the values of the interrupt-pending and interrupt-enable CSRs according to the privileged ISA reference chapter 3.1.14. Note that it does NOT implement the PLIC as defined in chapter 7, as that is used for handling external interrupts which are defined based on peripherals that are available. Change-Id: Ia1321430f870ff5a3950217266fde0511332485b Reviewed-on: https://gem5-review.googlesource.com/c/14377 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/x86/isa/microops/ | ||
H A D | ldstop.isa | 12682:dfc3bb0db088 Fri Apr 13 19:48:00 EDT 2018 Gabe Black <gabeblack@google.com> x86: Add a ld/st microop flag for marking an access uncacheable. This percolates down to the memory request object which will have its "UNCACHEABLE" flag set. Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce Reviewed-on: https://gem5-review.googlesource.com/9881 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> 7967:b243dc8cec8b Sun Feb 13 20:44:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Don't read in dest regs if all bits are replaced. In x86, 32 and 64 bit writes to registers in which registers appear to be 32 or 64 bits wide overwrite all bits of the destination register. This change removes false dependencies in these cases where the previous value of a register doesn't need to be read to write a new value. New versions of most microops are created that have a "Big" suffix which simply overwrite their destination, and the right version to use is selected during microop allocation based on the selected data size. This does not change the performance of the O3 CPU model significantly, I assume because there are other false dependencies from the condition code bits in the flags register. 5920:5a9c976270d6 Wed Feb 25 13:19:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a basic prefetch instruction. 5919:08f836f37f61 Wed Feb 25 13:19:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Use the right portion of a register for stores. 5912:d113f6def227 Wed Feb 25 13:18:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a flag to force memory accesses to happen at CPL 0. 5892:a0ef4a6349dc Wed Feb 25 13:15:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the stupd microop not update registers in initiateAcc. 5890:bdef71accd68 Wed Feb 25 13:15:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Get rid of translate... functions from various interface classes. 4561:ade4960f0832 Wed Jun 13 14:05:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move load/store microops into their own file. They still don't do anything, though. |
/gem5/src/cpu/testers/traffic_gen/ | ||
H A D | traffic_gen.cc | 12810:485ca1c27812 Thu Apr 26 13:16:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Split the traffic generator into two classes The traffic generator currently assumes that it is always driven from a configuration file. Split it into a base class (BaseTrafficGen) that handles basic packet generation and a derived class that implements the config handling (TrafficGen). Change-Id: I9407f04c40ad7e40a263c8d1ef29d37ff8e6f1b4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11515 12085:de78ea63e0ca Wed Jun 07 01:13:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper Change-Id: Idd5992463bcf9154f823b82461070d1f1842cea3 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3746 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 9666:74aca4cb081e Mon Apr 22 13:20:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Make the generators usable outside the TrafficGen module This patch enables the use of the generator behaviours outside the TrafficGen module. This is useful e.g. to allow packet replay modes for other devices in the system without having to replace them with a TrafficGen in the configuration files. This change also enables more specific behaviours to be composed as specific modules, e.g. BaseBandModem can use a number of generators and have application-specific parameters based around a specific set of generators. 9584:1a21964b7227 Tue Mar 12 13:41:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> cpu: Fix state transition bug in the traffic generator The traffic generator used to incorrectly determine the next state in when state 0 had a non-zero probability. Due to the way the next transition was determined, state 0 could never be entered other than as an initial state. This changeset updates the transitition() method to correctly handle such cases and cases where the transition matrix is a 1x1 matrix. 9403:af9066bc088c Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Share the send functionality between traffic generators This patch moves the packet creating and sending to a member function in the shared base class to avoid code duplication. 9402:f6e3c60f04e5 Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Add support for protobuf input for the trace generator This patch adds support for reading input traces encoded using protobuf according to what is done in the CommMonitor. A follow-up patch adds a Python script that can be used to convert the previously used ASCII traces to protobuf equivalents. The appropriate regression input is updated as part of this patch. 9400:b4a3d0953757 Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Encapsulate traffic generator input in a stream This patch encapsulates the traffic generator input in a stream class such that the parsing is not visible to the trace generator. The change takes us one step closer to using protobuf-based input traces for the trace replay. The functionality of the current input stream is identical to what it was, and the ASCII format remains the same for now. 9391:8f24dcb13b85 Mon Jan 07 13:05:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> cpu: Fix the traffic gen read percentage This patch fixes the computation that determines whether to perform a read or a write such that the two corner cases (0 and 100) are both more efficient and handled correctly. |
/gem5/src/dev/arm/ | ||
H A D | kmi.hh | 12659:3b44e9f66aac Mon Apr 09 13:42:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> dev, arm: Use the PS/2 framework in the Pl050 model The Pl050 KMI model currently has its own keyboard and mouse models. Use the generic PS/2 interface instead. Change-Id: I6523d26f8e38bcc8ba399d4d1a131723645d36c7 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9767 Reviewed-by: Gabe Black <gabeblack@google.com> 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/dev/mips/ | ||
H A D | malta_cchip.cc | 9808:13ffc0066b76 Thu Jul 11 22:57:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev: make BasicPioDevice take size in constructor Instead of relying on derived classes explicitly assigning to the BasicPioDevice pioSize field, require them to pass a size value in to the constructor. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
H A D | malta.cc | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode |
/gem5/src/gpu-compute/ | ||
H A D | wavefront.cc | 11883:3bfed693ff22 Mon Feb 27 13:18:00 EST 2017 Tony Gutierrez <anthony.gutierrez@amd.com> gpu-compute: remove unnecessary member from class The clang compiler complains that the wavefront member in the GpuISA class is unused. This changeset removes the member, because it does not appear serve a purpose. 11657:5fad5a37d6fc Tue Oct 04 13:03:00 EDT 2016 Alexandru Dutu <alexandru.dutu@amd.com> gpu-compute: Added method to compute the actual workgroup size This patch adds a method to the Wavefront class to compute the actual workgroup size. This can be different from the maximum workgroup size specified when launching the kernel through the NDRange object. Current solution is still not optimal, as we are computing these for each wavefront and the dispatcher also needs to have this information and can't actually call Wavefront::computeActuallWgSz before the wavefronts are being created. A long term solution would be to have a Workgroup class that deals with all these details. |
/gem5/src/mem/ | ||
H A D | packet_access.hh | 12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> 4040:eb894f3fc168 Mon Feb 12 13:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> rename store conditional stuff as extra data so it can be used for conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | neon64.isa | 13544:0b4e5446167c Sat Oct 13 02:32:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Stop using the FloatReg and FloatRegBits types. This will let us make those types 64 bits to be in line with the other architectures. Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021 Reviewed-on: https://gem5-review.googlesource.com/c/13621 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> 12038:619bc4100aa8 Tue Apr 25 13:35:00 EDT 2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> arch-arm: Fix some poorly done type max and min in NEON The ISA code for ARM calculates min and max elements for types using bit manipulation. That triggers some warnings, treated as errors, as the compiler can tell that there is an overflow and the sign flips. Fixed using standard lib definitions instead. Change-Id: Ie2331b410c7f76d4bd87da5afe9edf20c8ac91b3 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3481 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/arch/arm/ | ||
H A D | pmu.hh | 13581:b6dcd0183747 Sat Oct 13 04:25:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435 Reviewed-on: https://gem5-review.googlesource.com/c/13625 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> 12117:f50d7e4998e9 Tue Jun 13 19:29:00 EDT 2017 Jose Marinho <jose.marinho@arm.com> arch-arm: Support PMU evens in the 0x4000-0x4040 range ARMv8.1 added a second architected event range, 0x4000-0x4040. Events in this range are discovered using the high word of PMCEID{0,1}_EL0 Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3960 |
/gem5/src/arch/null/ | ||
H A D | registers.hh | 13556:9f57bb56153a Sat Oct 13 02:39:00 EDT 2018 Gabe Black <gabeblack@google.com> arch: Make the ISA register types aliases for the global types. The ISA specific types can thus be phased out. Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60 Reviewed-on: https://gem5-review.googlesource.com/c/13623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 9850:87d6b41749e9 Wed Sep 04 13:22:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> arch: Resurrect the NOISA build target and rename it NULL This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. |
/gem5/src/arch/x86/ | ||
H A D | tlb.hh | 12140:fab402159cdf Tue Jun 13 10:46:00 EDT 2017 Swapnil Haria <swapnilster@gmail.com> x86: Add stats to X86 TLB Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3980 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> 9423:43caa4ca5979 Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Add support for invalidating TLBs when draining This patch adds support for the memInvalidate() drain method. TLB flushing is requested by calling the virtual flushAll() method on the TLB. Note: This patch renames invalidateAll() to flushAll() on x86 and SPARC to make the interface consistent across all supported architectures. 8752:28e899b7dee3 Thu Oct 13 05:22:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Turn on the page table walker in SE mode. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense. 5895:569e3b31a868 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults. 5894:8091ac99341a Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it. 5891:73084c6bb183 Wed Feb 25 13:15:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Replace the translate functions in the TLBs with translateAtomic. |
H A D | X86TLB.py | 8839:eeb293859255 Mon Feb 13 06:43:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> MEM: Introduce the master/slave port roles in the Python classes This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves. 8752:28e899b7dee3 Thu Oct 13 05:22:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Turn on the page table walker in SE mode. |
H A D | pseudo_inst.cc | 11877:5ea85692a53e Mon Jul 20 10:15:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> syscall_emul: [patch 13/22] add system call retry capability This changeset adds functionality that allows system calls to retry without affecting thread context state such as the program counter or register values for the associated thread context (when system calls return with a retry fault). This functionality is needed to solve problems with blocking system calls in multi-process or multi-threaded simulations where information is passed between processes/threads. Blocking system calls can cause deadlock because the simulator itself is single threaded. There is only a single thread servicing the event queue which can cause deadlock if the thread hits a blocking system call instruction. To illustrate the problem, consider two processes using the producer/consumer sharing model. The processes can use file descriptors and the read and write calls to pass information to one another. If the consumer calls the blocking read system call before the producer has produced anything, the call will block the event queue (while executing the system call instruction) and deadlock the simulation. The solution implemented in this changeset is to recognize that the system calls will block and then generate a special retry fault. The fault will be sent back up through the function call chain until it is exposed to the cpu model's pipeline where the fault becomes visible. The fault will trigger the cpu model to replay the instruction at a future tick where the call has a chance to succeed without actually going into a blocking state. In subsequent patches, we recognize that a syscall will block by calling a non-blocking poll (from inside the system call implementation) and checking for events. When events show up during the poll, it signifies that the call would not have blocked and the syscall is allowed to proceed (calling an underlying host system call if necessary). If no events are returned from the poll, we generate the fault and try the instruction for the thread context at a distant tick. Note that retrying every tick is not efficient. As an aside, the simulator has some multi-threading support for the event queue, but it is not used by default and needs work. Even if the event queue was completely multi-threaded, meaning that there is a hardware thread on the host servicing a single simulator thread contexts with a 1:1 mapping between them, it's still possible to run into deadlock due to the event queue barriers on quantum boundaries. The solution of replaying at a later tick is the simplest solution and solves the problem generally. 11659:b29aca3fcb75 Tue Oct 04 13:06:00 EDT 2016 Alexandru Dutu <alexandru.dutu@amd.com> kvm: Adding details to kvm page fault in x86 Adding details, e.g. rip, rsp etc. to the kvm pagefault exit when in SE mode. |
/gem5/src/cpu/trace/ | ||
H A D | TraceCPU.py | 11633:40c951e58c2b Thu Sep 15 13:01:00 EDT 2016 Radhika Jagtap <radhika.jagtap@arm.com> cpu: Support exit when any one Trace CPU completes replay This change adds a Trace CPU param to exit simulation early, i.e. when the first (any one) trace execution is complete. With this change the user gets a choice to configure exit as either when the last CPU finishes (default) or first CPU finishes replay. Configuring an early exit enables simulating and measuring stats strictly when memory-system resources are being stressed by all Trace CPUs. Change-Id: I3998045fdcc5cd343e1ca92d18dd7f7ecdba8f1d Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> 11631:6d147afa8fc6 Thu Sep 15 13:01:00 EDT 2016 Radhika Jagtap <radhika.jagtap@arm.com> cpu: Add frequency scaling to the Trace CPU This change adds a simple feature to scale the frequency of the Trace CPU. The compute delays in the input traces provide timing. This change adds a freqency multiplier parameter to the Trace CPU set to 1.0 by default. The compute delay is manipulated to effectively achieve the frequency at which the nodes become ready and thus scale the frequency of the Trace CPU. Change-Id: Iaabbd57806941ad56094fcddbeb38fcee1172431 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/python/m5/ | ||
H A D | ticks.py | 13719:74853963ddcf Fri Jan 25 13:38:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> python: Add Python 3 workarounds for long Python 3 doesn't have a separate long type. Make long an alias for int where needed to maintain compatibility. Change-Id: I4c0861302bc3a2fa5226b3041803ef975d29b2fd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15988 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> 4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. |
/gem5/util/pbs/ | ||
H A D | send.py | 1908:73342b7d6f83 Wed Oct 12 13:01:00 EDT 2005 Nathan Binkert <binkertn@umich.edu> don't write the pbs jobid here, do it in send.py so we know what it is sooner Don't handle sigstop since you're not allowed to. util/pbs/send.py: write the pbs jobid here in send.py so we know what it is sooner 1376:190de61fed5a Sat Feb 05 13:49:00 EST 2005 Nathan Binkert <binkertn@umich.edu> Make pbs submission scripts available to all. Fix up configuration scrupts to have better support for running on the simulation pool. |
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