| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | AbstractController.cc | 206 AbstractController::blockOnQueue(Addr addr, MessageBuffer* port) argument
|
| /gem5/src/mem/ruby/system/ |
| H A D | RubyPort.cc | 176 MemSlavePort *port = senderState->port; local
430 MemSlavePort *port = senderState->port; local
[all...] |
| H A D | RubyPort.hh | 140 MemSlavePort *port; member in struct:RubyPort::SenderState
195 bool onRetryList(MemSlavePort * port) argument
200 void addToRetryList(MemSlavePort * port) argument
[all...] |
| H A D | GPUCoalescer.cc | 1158 MemSlavePort *port = ss->port; local
|
| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | base.hh | 164 TrafficGenPort port; member in class:BaseTrafficGen
|
| /gem5/src/learning_gem5/part2/ |
| H A D | simple_cache.cc | 252 int port = waitingPortId; local
[all...] |
| /gem5/src/sim/ |
| H A D | cxx_manager.cc | 346 const CxxConfigDirectoryEntry::PortDesc *port = (*i).second; local
485 bindMasterPort(SimObject *object, const CxxConfigDirectoryEntry::PortDesc &port, const std::vector<std::string> &peers) argument
535 const CxxConfigDirectoryEntry::PortDesc *port = (*i).second; local
558 parsePort(const std::string &inp, std::string &path, std::string &port, unsigned int &index) argument
[all...] |
| /gem5/ext/systemc/src/sysc/kernel/ |
| H A D | sc_module.cpp | 289 sc_module::async_reset_signal_is( const sc_in<bool>& port, bool level ) argument
295 sc_module::async_reset_signal_is( const sc_inout<bool>& port, bool level ) argument
301 sc_module::async_reset_signal_is( const sc_out<bool>& port, bool level ) argument
341 reset_signal_is( const sc_in<bool>& port, bool level ) argument
347 reset_signal_is( const sc_inout<bool>& port, bool level ) argument
353 reset_signal_is( const sc_out<bool>& port, bool level ) argument
[all...] |
| /gem5/src/dev/net/ |
| H A D | Ethernet.py | 124 port = Param.UInt16(3500, "Port helper should send packets to") variable in class:EtherTapStub
|
| /gem5/src/mem/ |
| H A D | DRAMCtrl.py | 79 port = SlavePort("Slave port") variable in class:DRAMCtrl
|
| H A D | dram_ctrl.hh | 131 MemoryPort port; member in class:DRAMCtrl
|
| /gem5/src/cpu/ |
| H A D | base.hh | 169 auto port = dynamic_cast<MasterPort *>(&getDataPort()); local
[all...] |
| /gem5/src/cpu/minor/ |
| H A D | lsq.hh | 126 LSQ &port; member in class:Minor::LSQ::LSQRequest
|
| /gem5/src/base/ |
| H A D | inet.hh | 244 uint8_t port() const { return _port; } function in struct:Net::IpWithPort
|
| H A D | remote_gdb.cc | 385 BaseRemoteGDB::port() const function in class:BaseRemoteGDB
|
| /gem5/src/systemc/core/ |
| H A D | sc_module.cc | 288 sc_module::reset_signal_is(const sc_in<bool> &port, bool val) argument
294 sc_module::reset_signal_is(const sc_inout<bool> &port, bool val) argument
300 sc_module::reset_signal_is(const sc_out<bool> &port, bool val) argument
313 sc_module::async_reset_signal_is(const sc_in<bool> &port, boo argument
319 async_reset_signal_is(const sc_inout<bool> &port, bool val) argument
325 async_reset_signal_is(const sc_out<bool> &port, bool val) argument
[all...] |
| /gem5/src/arch/arm/ |
| H A D | table_walker.hh | 830 DmaPort* port; member in class:ArmISA::TableWalker::LongDescriptor
|
| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.hh | 508 MasterPort& port; member in class:TraceCPU::FixedRetryGen
994 MasterPort& port; member in class:TraceCPU::ElasticDataGen
[all...] |
| /gem5/src/mem/cache/ |
| H A D | base.hh | 173 CacheReqPacketQueue(BaseCache &cache, MasterPort &port, argument
[all...] |
| /gem5/src/cpu/o3/ |
| H A D | lsq.hh | 305 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) : argument
317 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, argument
720 SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, argument
779 SplitDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad, argument
[all...] |
| /gem5/ext/googletest/googletest/src/ |
| H A D | gtest-internal-inl.h | 1057 SocketWriter(const string& host, const string& port) argument
1103 StreamingListener(const string& host, const string& port) argument
|