/gem5/src/arch/sparc/ |
H A D | interrupts.hh | 63 uint64_t interrupts[NumInterruptTypes]; member in class:SparcISA::Interrupts 108 interrupts[int_num] |= ULL(1) << index; 119 interrupts[int_num] &= ~(ULL(1) << index); 120 if (!interrupts[int_num]) 128 interrupts[i] = 0; 144 // priority interrupts should get serviced, 145 // it is v. important that new interrupts are inserted 149 if (interrupts[IT_HINTP]) { 153 if (interrupts[IT_INT_VEC]) { 159 if (interrupts[IT_TRAP_LEVEL_ZER [all...] |
/gem5/src/arch/arm/ |
H A D | interrupts.hh | 64 bool interrupts[NumInterruptTypes]; member in class:ArmISA::Interrupts 100 interrupts[int_num] = true; 115 interrupts[int_num] = false; 124 memset(interrupts, 0, sizeof(interrupts)); 159 return ((interrupts[INT_IRQ] && take_irq) || 160 (interrupts[INT_FIQ] && take_fiq) || 161 (interrupts[INT_ABT] && take_ea) || 162 ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq) || 163 ((interrupts[INT_VIRT_FI [all...] |
/gem5/util/cpt_upgraders/ |
H A D | smt-interrupts.py | 2 # SMT adds per-thread interrupts. Thus we must move the interrupt status 10 interrupts = cpt.get(sec, 'interrupts') 15 cpt.set(cpu_name + ".xc.0", 'interrupts', interrupts) 18 cpt.remove_option(sec, 'interrupts')
|
/gem5/src/arch/alpha/ |
H A D | interrupts.hh | 58 uint64_t interrupts[NumInterruptLevels]; member in class:AlphaISA::Interrupts 72 memset(interrupts, 0, sizeof(interrupts)); 94 interrupts[int_num] |= 1 << index; 109 interrupts[int_num] &= ~(1 << index); 110 if (interrupts[int_num] == 0) 119 memset(interrupts, 0, sizeof(interrupts)); 126 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 133 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevel [all...] |
/gem5/src/dev/ |
H A D | Device.py | 56 size, interrupts = None): 62 if interrupts: 63 if any([i < 32 for i in interrupts]): 69 node.append(FdtPropertyWords("interrupts", sum( 70 [[0, i - 32, 4] for i in interrupts], []) ))
|
/gem5/configs/learning_gem5/part1/ |
H A D | simple.py | 74 # For x86 only, make sure the interrupts are connected to the memory 77 system.cpu.interrupts[0].pio = system.membus.master 78 system.cpu.interrupts[0].int_master = system.membus.slave 79 system.cpu.interrupts[0].int_slave = system.membus.master
|
H A D | two_level.py | 126 # For x86 only, make sure the interrupts are connected to the memory 129 system.cpu.interrupts[0].pio = system.membus.master 130 system.cpu.interrupts[0].int_master = system.membus.slave 131 system.cpu.interrupts[0].int_slave = system.membus.master
|
/gem5/configs/learning_gem5/part2/ |
H A D | simple_cache.py | 76 system.cpu.interrupts[0].pio = system.membus.master 77 system.cpu.interrupts[0].int_master = system.membus.slave 78 system.cpu.interrupts[0].int_slave = system.membus.master
|
H A D | simple_memobj.py | 74 system.cpu.interrupts[0].pio = system.membus.master 75 system.cpu.interrupts[0].int_master = system.membus.slave 76 system.cpu.interrupts[0].int_slave = system.membus.master
|
/gem5/src/cpu/ |
H A D | base.hh | 57 #include "arch/interrupts.hh" 222 std::vector<TheISA::Interrupts*> interrupts; variable 228 if (interrupts.empty()) 231 assert(interrupts.size() > tid); 232 return interrupts[tid]; 240 interrupts[tid]->post(int_num, index); 248 interrupts[tid]->clear(int_num, index); 254 interrupts[tid]->clearAll(); 260 return FullSystem && interrupts[tc->threadId()]->checkInterrupts(tc);
|
H A D | base.cc | 134 interrupts(p->interrupts), profileEvent(NULL), 242 // The interrupts should always be present unless this CPU is 245 fatal_if(interrupts.size() != numThreads, 248 name(), interrupts.size(), numThreads); 250 interrupts[tid]->setCPU(this); 663 interrupts = oldCPU->interrupts; 665 interrupts[tid]->setCPU(this); 667 oldCPU->interrupts [all...] |
/gem5/tests/configs/ |
H A D | pc-simple-timing-ruby.py | 88 cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master 89 cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave 90 cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
|
/gem5/src/arch/arm/kvm/ |
H A D | base_cpu.cc | 91 const bool simFIQ(interrupts[0]->checkRaw(INT_FIQ)); 92 const bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
|
/gem5/tests/gem5/cpu_tests/ |
H A D | run.py | 154 system.cpu.interrupts[0].pio = system.membus.master 155 system.cpu.interrupts[0].int_master = system.membus.slave 156 system.cpu.interrupts[0].int_slave = system.membus.master
|
/gem5/src/dev/net/ |
H A D | sinic.cc | 433 Device::devIntrPost(uint32_t interrupts) argument 435 if ((interrupts & Regs::Intr_Res)) 438 regs.IntrStatus |= interrupts; 442 interrupts, regs.IntrStatus, regs.IntrMask); 444 interrupts = regs.IntrStatus & regs.IntrMask; 451 interrupts &= ~Regs::Intr_RxHigh; 458 interrupts &= ~Regs::Intr_TxLow; 460 if (interrupts) { 462 if ((interrupts & Regs::Intr_NoDelay) == 0) 469 Device::devIntrClear(uint32_t interrupts) argument 996 uint32_t interrupts; local [all...] |
H A D | ns_gige.cc | 735 NSGigE::devIntrPost(uint32_t interrupts) argument 737 if (interrupts & ISR_RESERVE) 740 if (interrupts & ISR_NOIMPL) 741 warn("interrupt not implemented %#x\n", interrupts); 743 interrupts &= ISR_IMPL; 744 regs.isr |= interrupts; 746 if (interrupts & regs.imr) { 747 if (interrupts & ISR_SWI) { 750 if (interrupts & ISR_RXIDLE) { 753 if (interrupts 792 devIntrClear(uint32_t interrupts) argument [all...] |
H A D | sinic.hh | 255 void devIntrPost(uint32_t interrupts); 256 void devIntrClear(uint32_t interrupts = Regs::Intr_All);
|
H A D | ns_gige.hh | 317 void devIntrPost(uint32_t interrupts); 318 void devIntrClear(uint32_t interrupts);
|
/gem5/src/arch/x86/ |
H A D | utility.cc | 43 #include "arch/x86/interrupts.hh" 185 Interrupts * interrupts = dynamic_cast<Interrupts *>( local 187 assert(interrupts); 189 interrupts->setRegNoEffect(APIC_ID, cpuId << 24); 191 interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
|
/gem5/configs/learning_gem5/part3/ |
H A D | msi_caches.py | 114 cpu.interrupts[0].pio = self.sequencers[i].master 115 cpu.interrupts[0].int_master = self.sequencers[i].slave 116 cpu.interrupts[0].int_slave = self.sequencers[i].master
|
H A D | ruby_caches_MI_example.py | 112 cpu.interrupts[0].pio = self.sequencers[i].master 113 cpu.interrupts[0].int_master = self.sequencers[i].slave 114 cpu.interrupts[0].int_slave = self.sequencers[i].master
|
/gem5/configs/example/ |
H A D | se.py | 267 system.cpu[i].interrupts[0].pio = ruby_port.master 268 system.cpu[i].interrupts[0].int_master = ruby_port.slave 269 system.cpu[i].interrupts[0].int_slave = ruby_port.master
|
H A D | apu_se.py | 464 system.cpu[i].interrupts[0].pio = system.piobus.master 465 system.cpu[i].interrupts[0].int_master = system.piobus.slave 466 system.cpu[i].interrupts[0].int_slave = system.piobus.master 506 system.cpu[cp_idx].interrupts[0].pio = system.piobus.master 507 system.cpu[cp_idx].interrupts[0].int_master = system.piobus.slave 508 system.cpu[cp_idx].interrupts[0].int_slave = system.piobus.master
|
H A D | fs.py | 179 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 181 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
|
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | illegal.S | 33 # Test vectored interrupts if they are supported. 48 # Delegate supervisor software interrupts so WFI won't stall.
|