Searched refs:Bridge (Results 1 - 9 of 9) sorted by relevance
/gem5/src/mem/ |
H A D | bridge.cc | 54 #include "debug/Bridge.hh" 55 #include "params/Bridge.hh" 57 Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name, 58 Bridge& _bridge, 69 Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name, 70 Bridge& _bridge, 79 Bridge::Bridge(Params *p) function in class:Bridge 89 Bridge::getPort(const std::string &if_name, PortID idx) 101 Bridge [all...] |
H A D | bridge.hh | 58 #include "params/Bridge.hh" 74 class Bridge : public ClockedObject class in inherits:ClockedObject 109 Bridge& bridge; 174 BridgeSlavePort(const std::string& _name, Bridge& _bridge, 229 Bridge& bridge; 271 BridgeMasterPort(const std::string& _name, Bridge& _bridge, 327 Bridge(Params *p);
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H A D | Bridge.py | 45 class Bridge(ClockedObject): class in inherits:ClockedObject 46 type = 'Bridge'
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/gem5/src/gpu-compute/ |
H A D | GPU.py | 44 from m5.objects.Bridge import Bridge 132 ldsBus = Bridge() # the bridge between the CU and its LDS
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/gem5/tests/configs/ |
H A D | twosys-tsunami-simple-atomic.py | 64 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 96 drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
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/gem5/configs/common/ |
H A D | HMC.py | 69 # SerialLink is a simple variation of the Bridge class, with the ability to 428 # then it will be forward to correct xbar. Bridge is used to connect xbars 433 system.hmc_dev.buffers = [Bridge(req_size=opt.xbar_buffer_size_req, 468 system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4]) 472 system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8]) 476 system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12]) 480 system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4]) 484 system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8]) 488 system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16])
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H A D | FSConfig.py | 114 self.bridge = Bridge(delay='50ns', 161 self.bridge = Bridge(delay='50ns') 226 self.bridge = Bridge(delay='50ns') 412 self.bridge = Bridge(delay='50ns') 453 # North Bridge 455 x86_sys.bridge = Bridge(delay='50ns') 475 x86_sys.apicbridge = Bridge(delay='50ns') 489 # North Bridge
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/gem5/configs/example/arm/ |
H A D | devices.py | 214 self.iobridge = Bridge(delay='50ns') 223 self.dmabridge = Bridge(delay='50ns',
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/gem5/configs/example/ |
H A D | fs.py | 190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 284 drive_sys.iobridge = Bridge(delay='50ns',
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