111308Santhony.gutierrez@amd.com# 211308Santhony.gutierrez@amd.com# Copyright (c) 2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com# All rights reserved. 411308Santhony.gutierrez@amd.com# 511308Santhony.gutierrez@amd.com# For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com# 711308Santhony.gutierrez@amd.com# Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com# modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com# 1011308Santhony.gutierrez@amd.com# 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com# this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com# 1311308Santhony.gutierrez@amd.com# 2. Redistributions in binary form must reproduce the above copyright notice, 1411308Santhony.gutierrez@amd.com# this list of conditions and the following disclaimer in the documentation 1511308Santhony.gutierrez@amd.com# and/or other materials provided with the distribution. 1611308Santhony.gutierrez@amd.com# 1711308Santhony.gutierrez@amd.com# 3. Neither the name of the copyright holder nor the names of its contributors 1811308Santhony.gutierrez@amd.com# may be used to endorse or promote products derived from this software 1911308Santhony.gutierrez@amd.com# without specific prior written permission. 2011308Santhony.gutierrez@amd.com# 2111308Santhony.gutierrez@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2211308Santhony.gutierrez@amd.com# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2311308Santhony.gutierrez@amd.com# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2411308Santhony.gutierrez@amd.com# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com# POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com# 3311308Santhony.gutierrez@amd.com# Author: Steve Reinhardt 3411308Santhony.gutierrez@amd.com# 3511308Santhony.gutierrez@amd.com 3611308Santhony.gutierrez@amd.comfrom m5.defines import buildEnv 3711308Santhony.gutierrez@amd.comfrom m5.params import * 3811308Santhony.gutierrez@amd.comfrom m5.proxy import * 3911308Santhony.gutierrez@amd.comfrom m5.SimObject import SimObject 4013665Sandreas.sandberg@arm.com 4113665Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject 4213665Sandreas.sandberg@arm.comfrom m5.objects.Device import DmaDevice 4313665Sandreas.sandberg@arm.comfrom m5.objects.Process import EmulatedDriver 4413665Sandreas.sandberg@arm.comfrom m5.objects.Bridge import Bridge 4513665Sandreas.sandberg@arm.comfrom m5.objects.LdsState import LdsState 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.comclass PrefetchType(Enum): vals = [ 4811308Santhony.gutierrez@amd.com 'PF_CU', 4911308Santhony.gutierrez@amd.com 'PF_PHASE', 5011308Santhony.gutierrez@amd.com 'PF_WF', 5111308Santhony.gutierrez@amd.com 'PF_STRIDE', 5211308Santhony.gutierrez@amd.com 'PF_END', 5311308Santhony.gutierrez@amd.com ] 5411308Santhony.gutierrez@amd.com 5511308Santhony.gutierrez@amd.comclass VectorRegisterFile(SimObject): 5611308Santhony.gutierrez@amd.com type = 'VectorRegisterFile' 5711308Santhony.gutierrez@amd.com cxx_class = 'VectorRegisterFile' 5811308Santhony.gutierrez@amd.com cxx_header = 'gpu-compute/vector_register_file.hh' 5911308Santhony.gutierrez@amd.com 6011308Santhony.gutierrez@amd.com simd_id = Param.Int(0, 'SIMD ID associated with this VRF') 6111308Santhony.gutierrez@amd.com num_regs_per_simd = Param.Int(2048, 'number of vector registers per SIMD') 6211534Sjohn.kalamatianos@amd.com wfSize = Param.Int(64, 'Wavefront size (in work items)') 6311308Santhony.gutierrez@amd.com min_alloc = Param.Int(4, 'min number of VGPRs allocated per WF') 6411308Santhony.gutierrez@amd.com 6511308Santhony.gutierrez@amd.comclass Wavefront(SimObject): 6611308Santhony.gutierrez@amd.com type = 'Wavefront' 6711308Santhony.gutierrez@amd.com cxx_class = 'Wavefront' 6811308Santhony.gutierrez@amd.com cxx_header = 'gpu-compute/wavefront.hh' 6911308Santhony.gutierrez@amd.com 7011308Santhony.gutierrez@amd.com simdId = Param.Int('SIMD id (0-ComputeUnit.num_SIMDs)') 7111308Santhony.gutierrez@amd.com wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)') 7211534Sjohn.kalamatianos@amd.com wfSize = Param.Int(64, 'Wavefront size (in work items)') 7311308Santhony.gutierrez@amd.com 7413892Sgabeblack@google.comclass ComputeUnit(ClockedObject): 7511308Santhony.gutierrez@amd.com type = 'ComputeUnit' 7611308Santhony.gutierrez@amd.com cxx_class = 'ComputeUnit' 7711308Santhony.gutierrez@amd.com cxx_header = 'gpu-compute/compute_unit.hh' 7811308Santhony.gutierrez@amd.com 7911308Santhony.gutierrez@amd.com wavefronts = VectorParam.Wavefront('Number of wavefronts') 8011308Santhony.gutierrez@amd.com wfSize = Param.Int(64, 'Wavefront size (in work items)') 8111308Santhony.gutierrez@amd.com num_SIMDs = Param.Int(4, 'number of SIMD units per CU') 8211308Santhony.gutierrez@amd.com 8311308Santhony.gutierrez@amd.com spbypass_pipe_length = Param.Int(4, 'vector ALU Single Precision bypass '\ 8411308Santhony.gutierrez@amd.com 'latency') 8511308Santhony.gutierrez@amd.com 8611308Santhony.gutierrez@amd.com dpbypass_pipe_length = Param.Int(8, 'vector ALU Double Precision bypass '\ 8711308Santhony.gutierrez@amd.com 'latency') 8811308Santhony.gutierrez@amd.com 8911308Santhony.gutierrez@amd.com issue_period = Param.Int(4, 'number of cycles per issue period') 9011308Santhony.gutierrez@amd.com num_global_mem_pipes = Param.Int(1,'number of global memory pipes per CU') 9111308Santhony.gutierrez@amd.com num_shared_mem_pipes = Param.Int(1,'number of shared memory pipes per CU') 9211308Santhony.gutierrez@amd.com n_wf = Param.Int(1, 'Number of wavefront slots per SIMD') 9311308Santhony.gutierrez@amd.com mem_req_latency = Param.Int(9, "Latency for request from the cu to ruby. "\ 9411308Santhony.gutierrez@amd.com "Represents the pipeline to reach the TCP and "\ 9511308Santhony.gutierrez@amd.com "specified in GPU clock cycles") 9611308Santhony.gutierrez@amd.com mem_resp_latency = Param.Int(9, "Latency for responses from ruby to the "\ 9711308Santhony.gutierrez@amd.com "cu. Represents the pipeline between the TCP "\ 9811308Santhony.gutierrez@amd.com "and cu as well as TCP data array access. "\ 9911308Santhony.gutierrez@amd.com "Specified in GPU clock cycles") 10011308Santhony.gutierrez@amd.com system = Param.System(Parent.any, "system object") 10111308Santhony.gutierrez@amd.com cu_id = Param.Int('CU id') 10211308Santhony.gutierrez@amd.com vrf_to_coalescer_bus_width = Param.Int(32, "VRF->Coalescer data bus width "\ 10311308Santhony.gutierrez@amd.com "in bytes") 10411308Santhony.gutierrez@amd.com coalescer_to_vrf_bus_width = Param.Int(32, "Coalescer->VRF data bus width "\ 10511308Santhony.gutierrez@amd.com "in bytes") 10611308Santhony.gutierrez@amd.com 10711308Santhony.gutierrez@amd.com memory_port = VectorMasterPort("Port to the memory system") 10811308Santhony.gutierrez@amd.com translation_port = VectorMasterPort('Port to the TLB hierarchy') 10911308Santhony.gutierrez@amd.com sqc_port = MasterPort("Port to the SQC (I-cache") 11011308Santhony.gutierrez@amd.com sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)") 11111308Santhony.gutierrez@amd.com perLaneTLB = Param.Bool(False, "enable per-lane TLB") 11211308Santhony.gutierrez@amd.com prefetch_depth = Param.Int(0, "Number of prefetches triggered at a time"\ 11311308Santhony.gutierrez@amd.com "(0 turns off prefetching)") 11411308Santhony.gutierrez@amd.com prefetch_stride = Param.Int(1, "Fixed Prefetch Stride (1 means next-page)") 11511308Santhony.gutierrez@amd.com prefetch_prev_type = Param.PrefetchType('PF_PHASE', "Prefetch the stride "\ 11611308Santhony.gutierrez@amd.com "from last mem req in lane of "\ 11711308Santhony.gutierrez@amd.com "CU|Phase|Wavefront") 11811308Santhony.gutierrez@amd.com execPolicy = Param.String("OLDEST-FIRST", "WF execution selection policy"); 11911308Santhony.gutierrez@amd.com xactCasMode = Param.Bool(False, "Behavior of xact_cas_load magic instr."); 12011308Santhony.gutierrez@amd.com debugSegFault = Param.Bool(False, "enable debugging GPU seg faults") 12111308Santhony.gutierrez@amd.com functionalTLB = Param.Bool(False, "Assume TLB causes no delay") 12211308Santhony.gutierrez@amd.com 12311308Santhony.gutierrez@amd.com localMemBarrier = Param.Bool(False, "Assume Barriers do not wait on "\ 12411308Santhony.gutierrez@amd.com "kernel end") 12511308Santhony.gutierrez@amd.com 12611308Santhony.gutierrez@amd.com countPages = Param.Bool(False, "Generate per-CU file of all pages touched "\ 12711308Santhony.gutierrez@amd.com "and how many times") 12811308Santhony.gutierrez@amd.com global_mem_queue_size = Param.Int(256, "Number of entries in the global " 12911308Santhony.gutierrez@amd.com "memory pipeline's queues") 13011308Santhony.gutierrez@amd.com local_mem_queue_size = Param.Int(256, "Number of entries in the local " 13111308Santhony.gutierrez@amd.com "memory pipeline's queues") 13211308Santhony.gutierrez@amd.com ldsBus = Bridge() # the bridge between the CU and its LDS 13311308Santhony.gutierrez@amd.com ldsPort = MasterPort("The port that goes to the LDS") 13411308Santhony.gutierrez@amd.com localDataStore = Param.LdsState("the LDS for this CU") 13511308Santhony.gutierrez@amd.com 13611308Santhony.gutierrez@amd.com vector_register_file = VectorParam.VectorRegisterFile("Vector register "\ 13711308Santhony.gutierrez@amd.com "file") 13811700Santhony.gutierrez@amd.com out_of_order_data_delivery = Param.Bool(False, "enable OoO data delivery" 13911700Santhony.gutierrez@amd.com " in the GM pipeline") 14011308Santhony.gutierrez@amd.com 14111308Santhony.gutierrez@amd.comclass Shader(ClockedObject): 14211308Santhony.gutierrez@amd.com type = 'Shader' 14311308Santhony.gutierrez@amd.com cxx_class = 'Shader' 14411308Santhony.gutierrez@amd.com cxx_header = 'gpu-compute/shader.hh' 14511308Santhony.gutierrez@amd.com 14611308Santhony.gutierrez@amd.com CUs = VectorParam.ComputeUnit('Number of compute units') 14711308Santhony.gutierrez@amd.com n_wf = Param.Int(1, 'Number of wavefront slots per SIMD') 14811308Santhony.gutierrez@amd.com impl_kern_boundary_sync = Param.Bool(True, """Insert acq/rel packets into 14911308Santhony.gutierrez@amd.com ruby at kernel boundaries""") 15011308Santhony.gutierrez@amd.com separate_acquire_release = Param.Bool(False, 15111308Santhony.gutierrez@amd.com """Do ld_acquire/st_release generate separate requests for the 15211308Santhony.gutierrez@amd.com acquire and release?""") 15311308Santhony.gutierrez@amd.com globalmem = Param.MemorySize('64kB', 'Memory size') 15411308Santhony.gutierrez@amd.com timing = Param.Bool(False, 'timing memory accesses') 15511308Santhony.gutierrez@amd.com 15611308Santhony.gutierrez@amd.com cpu_pointer = Param.BaseCPU(NULL, "pointer to base CPU") 15711308Santhony.gutierrez@amd.com translation = Param.Bool(False, "address translation"); 15811308Santhony.gutierrez@amd.com 15911308Santhony.gutierrez@amd.comclass ClDriver(EmulatedDriver): 16011308Santhony.gutierrez@amd.com type = 'ClDriver' 16111308Santhony.gutierrez@amd.com cxx_header = 'gpu-compute/cl_driver.hh' 16211308Santhony.gutierrez@amd.com codefile = VectorParam.String('code file name(s)') 16311308Santhony.gutierrez@amd.com 16411308Santhony.gutierrez@amd.comclass GpuDispatcher(DmaDevice): 16511308Santhony.gutierrez@amd.com type = 'GpuDispatcher' 16611308Santhony.gutierrez@amd.com cxx_header = 'gpu-compute/dispatcher.hh' 16711308Santhony.gutierrez@amd.com # put at 8GB line for now 16811308Santhony.gutierrez@amd.com pio_addr = Param.Addr(0x200000000, "Device Address") 16911308Santhony.gutierrez@amd.com pio_latency = Param.Latency('1ns', "Programmed IO latency") 17011308Santhony.gutierrez@amd.com shader_pointer = Param.Shader('pointer to shader') 17111308Santhony.gutierrez@amd.com translation_port = MasterPort('Port to the dispatcher TLB') 17211308Santhony.gutierrez@amd.com cpu = Param.BaseCPU("CPU to wake up on kernel completion") 17311308Santhony.gutierrez@amd.com 17411308Santhony.gutierrez@amd.com cl_driver = Param.ClDriver('pointer to driver') 17511308Santhony.gutierrez@amd.com 17611308Santhony.gutierrez@amd.comclass MemType(Enum): vals = [ 17711308Santhony.gutierrez@amd.com 'M_U8', 17811308Santhony.gutierrez@amd.com 'M_U16', 17911308Santhony.gutierrez@amd.com 'M_U32', 18011308Santhony.gutierrez@amd.com 'M_U64', 18111308Santhony.gutierrez@amd.com 'M_S8', 18211308Santhony.gutierrez@amd.com 'M_S16', 18311308Santhony.gutierrez@amd.com 'M_S32', 18411308Santhony.gutierrez@amd.com 'M_S64', 18511308Santhony.gutierrez@amd.com 'M_F16', 18611308Santhony.gutierrez@amd.com 'M_F32', 18711308Santhony.gutierrez@amd.com 'M_F64', 18811308Santhony.gutierrez@amd.com ] 18911308Santhony.gutierrez@amd.com 19011308Santhony.gutierrez@amd.comclass StorageClassType(Enum): vals = [ 19111308Santhony.gutierrez@amd.com 'SC_SPILL', 19211308Santhony.gutierrez@amd.com 'SC_GLOBAL', 19311308Santhony.gutierrez@amd.com 'SC_SHARED', 19411308Santhony.gutierrez@amd.com 'SC_PRIVATE', 19511308Santhony.gutierrez@amd.com 'SC_READONLY', 19611308Santhony.gutierrez@amd.com 'SC_KERNARG', 19711308Santhony.gutierrez@amd.com 'SC_NONE', 19811308Santhony.gutierrez@amd.com ] 19911308Santhony.gutierrez@amd.com 20011308Santhony.gutierrez@amd.comclass RegisterType(Enum): vals = [ 20111308Santhony.gutierrez@amd.com 'RT_VECTOR', 20211308Santhony.gutierrez@amd.com 'RT_SCALAR', 20311308Santhony.gutierrez@amd.com 'RT_CONDITION', 20411308Santhony.gutierrez@amd.com 'RT_HARDWARE', 20511308Santhony.gutierrez@amd.com 'RT_NONE', 20611308Santhony.gutierrez@amd.com ] 207