Searched hist:5422 (Results 1 - 9 of 9) sorted by relevance
/gem5/src/arch/sparc/insts/ | ||
H A D | priv.cc | 12287:4163eeb6210c Sun Nov 05 20:58:00 EST 2017 Gabe Black <gabeblack@google.com> sparc: Pull flat static instruction classes out of the ISA. These classes are just used as base classes for other instructions and don't need to be part of the ISA definition. Pull them into standard C++ files. Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554 Reviewed-on: https://gem5-review.googlesource.com/5422 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
H A D | priv.hh | 12287:4163eeb6210c Sun Nov 05 20:58:00 EST 2017 Gabe Black <gabeblack@google.com> sparc: Pull flat static instruction classes out of the ISA. These classes are just used as base classes for other instructions and don't need to be part of the ISA definition. Pull them into standard C++ files. Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554 Reviewed-on: https://gem5-review.googlesource.com/5422 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
H A D | SConscript | diff 12287:4163eeb6210c Sun Nov 05 20:58:00 EST 2017 Gabe Black <gabeblack@google.com> sparc: Pull flat static instruction classes out of the ISA. These classes are just used as base classes for other instructions and don't need to be part of the ISA definition. Pull them into standard C++ files. Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554 Reviewed-on: https://gem5-review.googlesource.com/5422 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/configs/example/arm/ | ||
H A D | fs_bigLITTLE.py | diff 12028:29ea3c7bc92f Wed Mar 22 13:36:00 EDT 2017 Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> arm, config: added support for ex5 model of big.LITTLE This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abutko@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/sparc/isa/formats/ | ||
H A D | priv.isa | diff 12287:4163eeb6210c Sun Nov 05 20:58:00 EST 2017 Gabe Black <gabeblack@google.com> sparc: Pull flat static instruction classes out of the ISA. These classes are just used as base classes for other instructions and don't need to be part of the ISA definition. Pull them into standard C++ files. Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554 Reviewed-on: https://gem5-review.googlesource.com/5422 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/configs/common/ | ||
H A D | CpuConfig.py | diff 12028:29ea3c7bc92f Wed Mar 22 13:36:00 EDT 2017 Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> arm, config: added support for ex5 model of big.LITTLE This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abutko@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/sparc/isa/ | ||
H A D | includes.isa | diff 12287:4163eeb6210c Sun Nov 05 20:58:00 EST 2017 Gabe Black <gabeblack@google.com> sparc: Pull flat static instruction classes out of the ISA. These classes are just used as base classes for other instructions and don't need to be part of the ISA definition. Pull them into standard C++ files. Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554 Reviewed-on: https://gem5-review.googlesource.com/5422 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
H A D | decoder.isa | diff 12287:4163eeb6210c Sun Nov 05 20:58:00 EST 2017 Gabe Black <gabeblack@google.com> sparc: Pull flat static instruction classes out of the ISA. These classes are just used as base classes for other instructions and don't need to be part of the ISA definition. Pull them into standard C++ files. Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554 Reviewed-on: https://gem5-review.googlesource.com/5422 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/x86/isa/decoder/ | ||
H A D | two_byte_opcodes.isa | diff 5422:f1f490fe77b0 Thu Jun 12 00:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate. |
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