1# Copyright (c) 2012, 2017-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38from __future__ import print_function 39from __future__ import absolute_import 40 41from m5 import fatal 42import m5.objects 43import inspect 44import sys 45from textwrap import TextWrapper 46 47# Dictionary of mapping names of real CPU models to classes. 48_cpu_classes = {} 49 50 51def is_cpu_class(cls): 52 """Determine if a class is a CPU that can be instantiated""" 53 54 # We can't use the normal inspect.isclass because the ParamFactory 55 # and ProxyFactory classes have a tendency to confuse it. 56 try: 57 return issubclass(cls, m5.objects.BaseCPU) and \ 58 not cls.abstract and \ 59 not issubclass(cls, m5.objects.CheckerCPU) 60 except (TypeError, AttributeError): 61 return False 62 63def _cpu_subclass_tester(name): 64 cpu_class = getattr(m5.objects, name, None) 65 66 def tester(cls): 67 return cpu_class is not None and cls is not None and \ 68 issubclass(cls, cpu_class) 69 70 return tester 71 72is_kvm_cpu = _cpu_subclass_tester("BaseKvmCPU") 73is_atomic_cpu = _cpu_subclass_tester("AtomicSimpleCPU") 74is_noncaching_cpu = _cpu_subclass_tester("NonCachingSimpleCPU") 75 76def get(name): 77 """Get a CPU class from a user provided class name or alias.""" 78 79 try: 80 cpu_class = _cpu_classes[name] 81 return cpu_class 82 except KeyError: 83 print("%s is not a valid CPU model." % (name,)) 84 sys.exit(1) 85 86def print_cpu_list(): 87 """Print a list of available CPU classes including their aliases.""" 88 89 print("Available CPU classes:") 90 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t") 91 for name, cls in _cpu_classes.items(): 92 print("\t%s" % name) 93 94 # Try to extract the class documentation from the class help 95 # string. 96 doc = inspect.getdoc(cls) 97 if doc: 98 for line in doc_wrapper.wrap(doc): 99 print(line) 100 101def cpu_names(): 102 """Return a list of valid CPU names.""" 103 return list(_cpu_classes.keys()) 104 105def config_etrace(cpu_cls, cpu_list, options): 106 if issubclass(cpu_cls, m5.objects.DerivO3CPU): 107 # Assign the same file name to all cpus for now. This must be 108 # revisited when creating elastic traces for multi processor systems. 109 for cpu in cpu_list: 110 # Attach the elastic trace probe listener. Set the protobuf trace 111 # file names. Set the dependency window size equal to the cpu it 112 # is attached to. 113 cpu.traceListener = m5.objects.ElasticTrace( 114 instFetchTraceFile = options.inst_trace_file, 115 dataDepTraceFile = options.data_trace_file, 116 depWindowSize = 3 * cpu.numROBEntries) 117 # Make the number of entries in the ROB, LQ and SQ very 118 # large so that there are no stalls due to resource 119 # limitation as such stalls will get captured in the trace 120 # as compute delay. For replay, ROB, LQ and SQ sizes are 121 # modelled in the Trace CPU. 122 cpu.numROBEntries = 512; 123 cpu.LQEntries = 128; 124 cpu.SQEntries = 128; 125 else: 126 fatal("%s does not support data dependency tracing. Use a CPU model of" 127 " type or inherited from DerivO3CPU.", cpu_cls) 128 129# Add all CPUs in the object hierarchy. 130for name, cls in inspect.getmembers(m5.objects, is_cpu_class): 131 _cpu_classes[name] = cls 132 133 134from m5.defines import buildEnv 135from importlib import import_module 136for package in [ "generic", buildEnv['TARGET_ISA']]: 137 try: 138 package = import_module(".cores." + package, 139 package=__name__.rpartition('.')[0]) 140 except ImportError: 141 # No timing models for this ISA 142 continue 143 144 for mod_name, module in inspect.getmembers(package, inspect.ismodule): 145 for name, cls in inspect.getmembers(module, is_cpu_class): 146 _cpu_classes[name] = cls 147