configs: Use absolute import paths

Use absoluate import paths to be Python 3 compatible. This also
imports absolute_import from __future__ to ensure that Python 2.7
behaves the same way as Python 3.

Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

configs: Fix Python 3 iterator and exec compatibility issues

Python 2.7 used to return lists for operations such as map and range,
this has changed in Python 3. To make the configs Python 3 compliant,
add explicit conversions from iterators to lists where needed, replace
xrange with range, and fix changes to exec syntax.

This change doesn't fix import paths since that might require us to
restructure the configs slightly.

Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16002
Reviewed-by: Gabe Black <gabeblack@google.com>

configs: simpoint-profile usable with NonCachingCPUs only

NonCachingCPU is replacing the Atomic+fastmem option.

Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15935
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Replace the fastmem with a new CPU model

The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.

The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.

This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.

Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Move KVM CPU checking to CpuConfig helper module

Both se.py and fs.py need to check if a CPU is a KVM CPU. This is
somewhat involved since CPUs can be disabled at compile time. Enable
better code reuse by moving it to the CpuConfig module.

Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12418
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Switch from the print statement to the print function.

Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0
Reviewed-on: https://gem5-review.googlesource.com/8762
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

config: Discover CPU timing models based on target ISA

The CpuConfig helper currently assumes that all timing models live in
the cores.arm package. This ignores the potential mismatch between the
target ISA and the ISA assumptions made by the timing models.

Instead of unconditionally listing all CPU models in cores.arm, list
timing models from cores.generic and cores.${TARGET_ISA}. This ensures
that the listed timing models support the ISA that gem5 is targeting.

Change-Id: If6235af2118889638f56ac4151003f38edfe9485
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3947
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Clean up core timing model discovery

Instead of hard-coding timing models in CpuConfig.py, use
introspection to find them in the cores.arm model package.

Change-Id: I6642dc9cbc3f5beeeec748e716c9426c233d51ea
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3944
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Move core timing models to config/common/cores

Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Add missing import of 'fatal' in CpuConfig

Change-Id: I7762d344cb964c3e010135ff928c6ea12538912c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3941
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm, config: added support for ex5 model of big.LITTLE

This patch enables using calibrated big and LITTLE cores, ex5_big and
ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5
model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory
hierarchy latencies have been calibrated using the lmbench micro-benchmark
suite. The preliminary validation results have been published as: 'Full-System
Simulation of big.LITTLE Multicore Architecture for Performance and Energy
Exploration', in International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016).

From http://reviews.gem5.org/r/3666

Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7
Signed-off-by: Anastasiia Butko <abutko@lbl.gov>
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/2464
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Remove support for CPU aliases.

This was added for backwards compatability, but it adds a decent amount
of complexity.

The table below shows what CPU class name to use in place of a given
alias.

+==========+========================================================+
| Alias | CPU class |
+==========+========================================================+
| timing | TimingSimpleCPU |
| atomic | AtomicSimpleCPU |
| minor | MinorCPU |
| detailed | DrivO3CPU |
| kvm | ArmKvmCPU, ArmV8KvmCPU or X86KvmCPU, depending on arch |
| trace | TraceCPU |
+==========+========================================================+

Change-Id: I251c4f64b7869c6b64dd25b36967ae240f01ef08
Reviewed-on: https://gem5-review.googlesource.com/2940
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

config: Break out base options for usage with NULL ISA

This patch breaks out the most basic configuration options into a set
of base options, to allow them to be used also by scripts that do not
involve any ISA, and thus no actual CPUs or devices.

The patch also fixes a few modules so that they can be imported in a
NULL build, and avoid dragging in FSConfig every time Options is
imported.

config: Enable elastic trace capture and replay in se/fs

This patch adds changes to the configuration scripts to support elastic
tracing and replay.

The patch adds a command line option to enable elastic tracing in SE mode
and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU
and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out
both instruction fetch and data dependency traces. The patch also enables
configuring the TraceCPU to replay traces using the SE and FS script.

The replay run is designed to resume from checkpoint using atomic cpu to
restore state keeping it consistent with FS run flow. It then switches to
TraceCPU to replay the input traces.

kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.

scons: Do not build the InOrderCPU

One step closer to shifting focus to the MinorCPU.

cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036

config: Add a 'kvm' CPU alias

Add a CPU alias, 'kvm', for the first available KVM-accelerated CPU
model.

config: Cleanup CPU configuration

The CPUs supported by the configuration scripts used to be
hard-coded. This was not ideal for several reasons. For example, the
configuration scripts depend on all CPU models even though only a
subset might have been compiled.

This changeset adds a new module to the configuration scripts that
automatically discovers the available CPU models from the compiled
SimObjects. As a nice bonus, the use of introspection allows us to
automatically generate a list of available CPU models suitable for
printing. This list is augmented with the Python doc string from the
underlying class if available.