/gem5/src/arch/alpha/ |
H A D | vtophys.cc | 58 Addr level2_pte = level1.paddr() + vaddr.level2(); 65 Addr level3_pte = level2.paddr() + vaddr.level3(); 77 Addr paddr = 0; local 81 paddr = K0Seg2Phys(vaddr); 85 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 87 return paddr; 95 Addr paddr = 0; local 99 paddr = vaddr & ~ULL(1); 102 paddr = K0Seg2Phys(vaddr); 104 paddr [all...] |
H A D | pagetable.hh | 89 Addr paddr() const { return _pfn() << PageShift; } function in struct:AlphaISA::PageTableEntry 111 VAddr paddr(_paddr); 113 ppn = paddr.vpn();
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/gem5/src/mem/ |
H A D | fs_translating_port_proxy.cc | 78 Addr paddr; local 83 paddr = TheISA::vtophys(_tc,gen.addr()); 85 paddr = TheISA::vtophys(gen.addr()); 87 PortProxy::readBlobPhys(paddr, 0, p, gen.size()); 97 Addr paddr; local 102 paddr = TheISA::vtophys(_tc,gen.addr()); 104 paddr = TheISA::vtophys(gen.addr()); 106 PortProxy::writeBlobPhys(paddr, 0, p, gen.size()); 115 Addr paddr; local 120 paddr [all...] |
H A D | page_table.cc | 49 EmulationPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags) argument 64 it->second = Entry(paddr, flags); 66 pTable.emplace(vaddr, Entry(paddr, flags)); 71 paddr += pageSize; 101 addr_maps->push_back(std::make_pair(iter.first, iter.second.paddr)); 144 EmulationPageTable::translate(Addr vaddr, Addr &paddr) argument 151 paddr = pageOffset(vaddr) + entry->paddr; 152 DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr); 159 Addr paddr; local 199 Addr paddr; local [all...] |
H A D | se_translating_port_proxy.cc | 76 Addr paddr; local 78 if (!pTable->translate(gen.addr(),paddr)) 81 PortProxy::readBlobPhys(paddr, 0, bytes + prevSize, gen.size()); 96 Addr paddr; local 98 if (!pTable->translate(gen.addr(), paddr)) { 110 pTable->translate(gen.addr(), paddr); 113 PortProxy::writeBlobPhys(paddr, 0, bytes + prevSize, gen.size()); 125 Addr paddr; local 127 if (!pTable->translate(gen.addr(), paddr)) { 131 pTable->translate(gen.addr(), paddr); [all...] |
H A D | page_table.hh | 55 Addr paddr; member in struct:EmulationPageTable::Entry 58 Entry(Addr paddr, uint64_t flags) : paddr(paddr), flags(flags) {} argument 113 * @param paddr The starting physical address where the region is mapped. 118 virtual void map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags = 0); 140 * @param paddr Physical address from translation. 143 bool translate(Addr vaddr, Addr &paddr); 153 * Perform a translation on the memory request, fills in paddr
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H A D | multi_level_page_table.hh | 162 next = first.paddr(); 216 map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags = 0) override 218 EmulationPageTable::map(vaddr, paddr, size, flags); 226 entry.reset(paddr + offset, true, flags & Uncacheable, 231 vaddr + offset, paddr + offset); 252 new_entry.reset(old_entry.paddr(), true, old_entry.uncacheable(),
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H A D | abstract_mem.cc | 213 Addr paddr = LockedAddr::mask(req->getPaddr()); local 223 req->contextId(), paddr); 224 i->addr = paddr; 231 req->contextId(), paddr); 244 Addr paddr = LockedAddr::mask(req->getPaddr()); local 261 if (i->addr == paddr && i->matchesContext(req)) { 265 req->contextId(), paddr); 278 // We write address paddr. However, there may be several entries with a 283 if (i->addr == paddr) { 285 i->contextId, paddr); [all...] |
H A D | request.hh | 266 /** Whether or not paddr is valid (has been written yet). */ 295 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) argument 297 _paddr = paddr; 318 * paddr is written via setVirt() or setPhys(), so it is always 342 * latencies. This field is set to curTick() any time paddr or vaddr 409 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, argument 417 setPhys(paddr, size, flags, mid, curTick()); 427 Request(Addr paddr, unsigned size, Flags flags, MasterID mid) argument 434 setPhys(paddr, size, flags, mid, curTick()); 437 Request(Addr paddr, unsigne argument 447 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time, Addr pc) argument 557 setPaddr(Addr paddr) argument [all...] |
H A D | abstract_mem.hh | 81 static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } argument
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/gem5/src/arch/x86/ |
H A D | vtophys.cc | 71 Addr paddr = addr | masked_addr; local 72 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 73 return paddr;
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H A D | pagetable.cc | 51 : paddr(0), vaddr(0), logBytes(0), writable(0), 59 paddr(_paddr), vaddr(_vaddr), logBytes(PageShift), writable(!read_only), 67 SERIALIZE_SCALAR(paddr); 82 UNSERIALIZE_SCALAR(paddr);
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H A D | pagetable.hh | 69 Addr paddr; member in struct:X86ISA::TlbEntry 109 return paddr; 159 Addr paddr() { return pte.base << PageShift; } function in class:X86ISA::LongModePTE 160 void paddr(Addr addr) { pte.base = addr >> PageShift; } function in class:X86ISA::LongModePTE 185 paddr(_paddr);
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H A D | tlb.cc | 230 Addr paddr = req->getPaddr(); local 234 if (m5opRange.contains(paddr)) { 237 req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF, 238 paddr & 0xFF)); 246 if (apicRange.contains(paddr)) { 252 if (paddr & ((32/8) - 1)) 261 paddr - apicRange.start())); 377 pte->paddr); 379 p->pTable->pid(), alignedVaddr, pte->paddr, 387 DPRINTF(TLB, "Entry found with paddr 408 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); local [all...] |
/gem5/src/arch/mips/ |
H A D | pagetable.hh | 86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, argument 88 : _pageStart(paddr)
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/gem5/src/arch/riscv/ |
H A D | pagetable.hh | 86 TlbEntry(Addr asn, Addr vaddr, Addr paddr, argument 88 : _pageStart(paddr)
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/gem5/src/arch/arm/tracers/ |
H A D | tarmac_record_v8.cc | 53 paddr(0), 60 paddrValid = dtb->translateFunctional(thread, addr, paddr); 68 paddr(_addr) 74 dtb->translateFunctional(thread, addr, paddr); 187 // If there is a valid vaddr->paddr translation, print the 189 std::string paddr_str = paddrValid? csprintf(":%012x",paddr) : 225 paddr, /* Phys Memory address */
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H A D | tarmac_record_v8.hh | 88 Addr paddr; member in struct:Trace::TarmacTracerRecordV8::TraceInstEntryV8 128 Addr paddr; member in struct:Trace::TarmacTracerRecordV8::TraceMemEntryV8
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/gem5/src/mem/cache/prefetch/ |
H A D | irregular_stream_buffer.hh | 119 * @param paddr physical address 123 AddressMapping& getPSMapping(Addr paddr, bool is_secure);
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/gem5/src/arch/sparc/ |
H A D | pagetable.hh | 114 entry4u |= mbits(entry,39,13); // paddr 164 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);} function in class:SparcISA::PageTableEntry 172 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); } 179 return (paddr() & ~mask) | (vaddr & mask); 233 TlbEntry(Addr asn, Addr vaddr, Addr paddr, argument 246 entry |= mbits(paddr, 39, 13); // Physical address 271 return pte.paddr();
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/gem5/src/cpu/testers/memtest/ |
H A D | memtest.cc | 229 Addr paddr; 241 paddr = uncacheAddr + offset; 243 paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 245 } while (outstandingAddrs.find(paddr) != outstandingAddrs.end()); 249 RequestPtr req = std::make_shared<Request>(paddr, 1, flags, masterId); 252 outstandingAddrs.insert(paddr);
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/gem5/src/gpu-compute/ |
H A D | gpu_tlb.cc | 819 alignedVaddr, pte->paddr); 822 pte->paddr, false, false); 861 DPRINTF(GPUTLB, "Entry found with paddr %#x, doing protection " 862 "checks.\n", entry->paddr); 865 Addr paddr = entry->paddr | (vaddr & (page_size - 1)); local 866 DPRINTF(GPUTLB, "Translated %#x -> %#x.\n", vaddr, paddr); 867 req->setPaddr(paddr); 890 Addr paddr = req->getPaddr(); local 892 if (baseAddr <= paddr 1209 Addr paddr = local_entry->paddr | (vaddr & (page_size - 1)); local 1468 Addr paddr = local_entry->paddr | (vaddr & (page_size - 1)); local [all...] |
/gem5/src/cpu/testers/garnet_synthetic_traffic/ |
H A D | GarnetSyntheticTraffic.cc | 248 Addr paddr = destination; local 249 paddr <<= blockSizeBits; 295 req = std::make_shared<Request>(paddr, access_size, flags, masterId); 302 req->setPaddr(paddr); 306 req = std::make_shared<Request>(paddr, access_size, flags, masterId);
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/gem5/src/mem/ruby/system/ |
H A D | DMASequencer.cc | 71 Addr paddr = pkt->getAddr(); local 77 Addr line_addr = makeLineAddress(paddr); 81 std::forward_as_tuple(paddr, len, write, 0, 97 msg->getPhysicalAddress() = paddr; 100 int offset = paddr & m_data_block_mask;
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/gem5/src/arch/power/ |
H A D | tlb.hh | 65 TlbEntry(Addr asn, Addr vaddr, Addr paddr, argument 67 : _pageStart(paddr)
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