112642Sgiacomo.travaglini@arm.com/* 212642Sgiacomo.travaglini@arm.com * Copyright (c) 2017-2018 ARM Limited 312642Sgiacomo.travaglini@arm.com * All rights reserved 412642Sgiacomo.travaglini@arm.com * 512642Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612642Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712642Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812642Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912642Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012642Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112642Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212642Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312642Sgiacomo.travaglini@arm.com * 1412642Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512642Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612642Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712642Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812642Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912642Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012642Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112642Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212642Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312642Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412642Sgiacomo.travaglini@arm.com * 2512642Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612642Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712642Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812642Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912642Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012642Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112642Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212642Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312642Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412642Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512642Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612642Sgiacomo.travaglini@arm.com * 3712642Sgiacomo.travaglini@arm.com * Authors: Giacomo Travaglini 3812642Sgiacomo.travaglini@arm.com */ 3912642Sgiacomo.travaglini@arm.com 4012642Sgiacomo.travaglini@arm.com/** 4112642Sgiacomo.travaglini@arm.com * @file: The file contains the informations used to generate records 4212642Sgiacomo.travaglini@arm.com * for ARMv8 cores. 4312642Sgiacomo.travaglini@arm.com */ 4412642Sgiacomo.travaglini@arm.com 4512642Sgiacomo.travaglini@arm.com#ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__ 4612642Sgiacomo.travaglini@arm.com#define __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__ 4712642Sgiacomo.travaglini@arm.com 4812642Sgiacomo.travaglini@arm.com#include "tarmac_record.hh" 4912642Sgiacomo.travaglini@arm.com 5012642Sgiacomo.travaglini@arm.comnamespace Trace { 5112642Sgiacomo.travaglini@arm.com 5212642Sgiacomo.travaglini@arm.com/** 5312642Sgiacomo.travaglini@arm.com * TarmacTracer record for ARMv8 CPUs: 5412642Sgiacomo.travaglini@arm.com * The record is adding some data to the base TarmacTracer 5512642Sgiacomo.travaglini@arm.com * record. 5612642Sgiacomo.travaglini@arm.com */ 5712642Sgiacomo.travaglini@arm.comclass TarmacTracerRecordV8 : public TarmacTracerRecord 5812642Sgiacomo.travaglini@arm.com{ 5912642Sgiacomo.travaglini@arm.com public: 6012642Sgiacomo.travaglini@arm.com 6112642Sgiacomo.travaglini@arm.com /** 6212642Sgiacomo.travaglini@arm.com * General data shared by all v8 entries 6312642Sgiacomo.travaglini@arm.com */ 6412642Sgiacomo.travaglini@arm.com struct TraceEntryV8 6512642Sgiacomo.travaglini@arm.com { 6612642Sgiacomo.travaglini@arm.com public: 6712642Sgiacomo.travaglini@arm.com TraceEntryV8(std::string _cpuName) 6812642Sgiacomo.travaglini@arm.com : cpuName(_cpuName) 6912642Sgiacomo.travaglini@arm.com {} 7012642Sgiacomo.travaglini@arm.com 7112642Sgiacomo.travaglini@arm.com protected: 7212642Sgiacomo.travaglini@arm.com std::string cpuName; 7312642Sgiacomo.travaglini@arm.com }; 7412642Sgiacomo.travaglini@arm.com 7512642Sgiacomo.travaglini@arm.com /** 7612642Sgiacomo.travaglini@arm.com * Instruction entry for v8 records 7712642Sgiacomo.travaglini@arm.com */ 7812642Sgiacomo.travaglini@arm.com struct TraceInstEntryV8: public TraceInstEntry, TraceEntryV8 7912642Sgiacomo.travaglini@arm.com { 8012642Sgiacomo.travaglini@arm.com public: 8112642Sgiacomo.travaglini@arm.com TraceInstEntryV8(const TarmacContext& tarmCtx, bool predicate); 8212642Sgiacomo.travaglini@arm.com 8312642Sgiacomo.travaglini@arm.com virtual void print(std::ostream& outs, 8412642Sgiacomo.travaglini@arm.com int verbosity = 0, 8512642Sgiacomo.travaglini@arm.com const std::string &prefix = "") const override; 8612642Sgiacomo.travaglini@arm.com 8712642Sgiacomo.travaglini@arm.com protected: 8812642Sgiacomo.travaglini@arm.com Addr paddr; 8912642Sgiacomo.travaglini@arm.com bool paddrValid; 9012642Sgiacomo.travaglini@arm.com }; 9112642Sgiacomo.travaglini@arm.com 9212642Sgiacomo.travaglini@arm.com /** 9312642Sgiacomo.travaglini@arm.com * Register entry for v8 records 9412642Sgiacomo.travaglini@arm.com */ 9512642Sgiacomo.travaglini@arm.com struct TraceRegEntryV8: public TraceRegEntry, TraceEntryV8 9612642Sgiacomo.travaglini@arm.com { 9712642Sgiacomo.travaglini@arm.com public: 9812642Sgiacomo.travaglini@arm.com TraceRegEntryV8(const TarmacContext& tarmCtx, const RegId& reg); 9912642Sgiacomo.travaglini@arm.com 10012642Sgiacomo.travaglini@arm.com virtual void print(std::ostream& outs, 10112642Sgiacomo.travaglini@arm.com int verbosity = 0, 10212642Sgiacomo.travaglini@arm.com const std::string &prefix = "") const override; 10312642Sgiacomo.travaglini@arm.com 10412642Sgiacomo.travaglini@arm.com protected: 10512642Sgiacomo.travaglini@arm.com void updateInt(const TarmacContext& tarmCtx, 10612642Sgiacomo.travaglini@arm.com RegIndex regRelIdx) override; 10712642Sgiacomo.travaglini@arm.com 10812642Sgiacomo.travaglini@arm.com void updateMisc(const TarmacContext& tarmCtx, 10912642Sgiacomo.travaglini@arm.com RegIndex regRelIdx) override; 11012642Sgiacomo.travaglini@arm.com 11112642Sgiacomo.travaglini@arm.com uint8_t regWidth; 11212642Sgiacomo.travaglini@arm.com }; 11312642Sgiacomo.travaglini@arm.com 11412642Sgiacomo.travaglini@arm.com /** 11512642Sgiacomo.travaglini@arm.com * Memory Entry for V8 11612642Sgiacomo.travaglini@arm.com */ 11712642Sgiacomo.travaglini@arm.com struct TraceMemEntryV8: public TraceMemEntry, TraceEntryV8 11812642Sgiacomo.travaglini@arm.com { 11912642Sgiacomo.travaglini@arm.com public: 12012642Sgiacomo.travaglini@arm.com TraceMemEntryV8(const TarmacContext& tarmCtx, 12112642Sgiacomo.travaglini@arm.com uint8_t _size, Addr _addr, uint64_t _data); 12212642Sgiacomo.travaglini@arm.com 12312642Sgiacomo.travaglini@arm.com virtual void print(std::ostream& outs, 12412642Sgiacomo.travaglini@arm.com int verbosity = 0, 12512642Sgiacomo.travaglini@arm.com const std::string &prefix = "") const override; 12612642Sgiacomo.travaglini@arm.com 12712642Sgiacomo.travaglini@arm.com protected: 12812642Sgiacomo.travaglini@arm.com Addr paddr; 12912642Sgiacomo.travaglini@arm.com }; 13012642Sgiacomo.travaglini@arm.com 13112642Sgiacomo.travaglini@arm.com public: 13212642Sgiacomo.travaglini@arm.com TarmacTracerRecordV8(Tick _when, ThreadContext *_thread, 13313915Sgabeblack@google.com const StaticInstPtr _staticInst, ArmISA::PCState _pc, 13412642Sgiacomo.travaglini@arm.com TarmacTracer& _parent, 13512642Sgiacomo.travaglini@arm.com const StaticInstPtr _macroStaticInst = NULL) 13612642Sgiacomo.travaglini@arm.com : TarmacTracerRecord(_when, _thread, _staticInst, _pc, 13712642Sgiacomo.travaglini@arm.com _parent, _macroStaticInst) 13812642Sgiacomo.travaglini@arm.com {} 13912642Sgiacomo.travaglini@arm.com 14012642Sgiacomo.travaglini@arm.com protected: 14112642Sgiacomo.travaglini@arm.com /** Generates an Entry for the executed instruction. */ 14212642Sgiacomo.travaglini@arm.com void addInstEntry(std::vector<InstPtr>& queue, const TarmacContext& ptr); 14312642Sgiacomo.travaglini@arm.com 14412642Sgiacomo.travaglini@arm.com /** Generates an Entry for every memory access triggered */ 14512642Sgiacomo.travaglini@arm.com void addMemEntry(std::vector<MemPtr>& queue, const TarmacContext& ptr); 14612642Sgiacomo.travaglini@arm.com 14712642Sgiacomo.travaglini@arm.com /** Generate a Record for every register being written */ 14812642Sgiacomo.travaglini@arm.com void addRegEntry(std::vector<RegPtr>& queue, const TarmacContext& ptr); 14912642Sgiacomo.travaglini@arm.com}; 15012642Sgiacomo.travaglini@arm.com 15112642Sgiacomo.travaglini@arm.com} // namespace Trace 15212642Sgiacomo.travaglini@arm.com 15312642Sgiacomo.travaglini@arm.com#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__ 154