| /gem5/src/arch/generic/ |
| H A D | tlb.hh | 78 virtual void finish(const Fault &fault, const RequestPtr &req,
93 const RequestPtr &req, ThreadContext *tc, Mode mode) = 0;
95 const RequestPtr &req, ThreadContext *tc,
98 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
118 const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0;
155 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
157 const RequestPtr &req, ThreadContext *tc,
161 const RequestPtr &req, ThreadContext *tc, Mode mode) const override;
|
| H A D | locked_mem.hh | 66 handleLockedRead(XC *xc, const RequestPtr &req)
79 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
|
| H A D | tlb.cc | 40 GenericTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode)
55 GenericTLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
63 GenericTLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc,
|
| /gem5/src/arch/arm/ |
| H A D | stage2_lookup.hh | 64 RequestPtr s1Req;
71 RequestPtr req;
77 Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, const RequestPtr &_req,
92 void mergeTe(const RequestPtr &req, BaseTLB::Mode mode);
100 void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
|
| H A D | tlb.hh | 80 virtual Fault translationCheck(const RequestPtr &req, bool is_priv,
234 Fault getTE(TlbEntry **te, const RequestPtr &req,
239 Fault getResultTe(TlbEntry **te, const RequestPtr &req,
244 Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
245 Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
247 bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
301 Fault trickBoxCheck(const RequestPtr &req, Mode mode,
331 Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
334 translateFunctional(const RequestPtr &req,
354 Fault translateFs(const RequestPtr
[all...] |
| H A D | stage2_mmu.hh | 75 RequestPtr req;
90 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
|
| /gem5/src/arch/mips/ |
| H A D | tlb.hh | 107 static Fault checkCacheability(const RequestPtr &req);
116 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
118 const RequestPtr &req, ThreadContext *tc,
121 const RequestPtr &req,
125 Fault translateInst(const RequestPtr &req, ThreadContext *tc);
126 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
|
| H A D | locked_mem.hh | 78 handleLockedRead(XC *xc, const RequestPtr &req)
95 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
|
| H A D | tlb.cc | 145 TLB::checkCacheability(const RequestPtr &req)
285 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
300 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
315 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
324 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
332 TLB::finalizePhysical(const RequestPtr &req,
|
| /gem5/src/arch/riscv/ |
| H A D | tlb.hh | 106 static Fault checkCacheability(const RequestPtr &req);
115 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
117 const RequestPtr &req, ThreadContext *tc,
120 const RequestPtr &req,
124 Fault translateInst(const RequestPtr &req, ThreadContext *tc);
125 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
|
| H A D | locked_mem.hh | 88 handleLockedRead(XC *xc, const RequestPtr &req)
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
|
| /gem5/src/cpu/ |
| H A D | translation.hh | 70 RequestPtr mainReq;
71 RequestPtr sreqLow;
72 RequestPtr sreqHigh;
81 WholeTranslationState(const RequestPtr &_req, uint8_t *_data,
95 WholeTranslationState(const RequestPtr &_req, const RequestPtr &_sreqLow,
96 const RequestPtr &_sreqHigh, uint8_t *_data,
252 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
|
| /gem5/src/arch/x86/ |
| H A D | tlb.hh | 109 Fault translateInt(const RequestPtr &req, ThreadContext *tc);
111 Fault translate(const RequestPtr &req, ThreadContext *tc,
126 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
128 const RequestPtr &req, ThreadContext *tc,
144 Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc,
|
| /gem5/src/arch/alpha/ |
| H A D | tlb.hh | 117 static Fault checkCacheability(const RequestPtr &req, bool itb = false);
140 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
141 Fault translateInst(const RequestPtr &req, ThreadContext *tc);
145 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
147 const RequestPtr &req, ThreadContext *tc,
150 const RequestPtr &req, ThreadContext *tc,
|
| H A D | locked_mem.hh | 88 handleLockedRead(XC *xc, const RequestPtr &req)
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
|
| /gem5/src/arch/power/ |
| H A D | tlb.hh | 162 static Fault checkCacheability(const RequestPtr &req);
163 Fault translateInst(const RequestPtr &req, ThreadContext *tc);
164 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
166 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
168 const RequestPtr &req, ThreadContext *tc,
171 const RequestPtr &req,
|
| H A D | tlb.cc | 148 TLB::checkCacheability(const RequestPtr &req)
282 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
301 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
313 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
325 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
333 TLB::finalizePhysical(const RequestPtr &req,
|
| /gem5/src/cpu/simple/ |
| H A D | atomic.hh | 163 RequestPtr ifetch_req;
164 RequestPtr data_read_req;
165 RequestPtr data_write_req;
166 RequestPtr data_amo_req;
214 bool genMemFragmentRequest(const RequestPtr& req, Addr frag_addr,
|
| H A D | timing.hh | 127 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
136 void sendData(const RequestPtr &req,
138 void sendSplitData(const RequestPtr &req1, const RequestPtr &req2,
139 const RequestPtr &req,
144 PacketPtr buildPacket(const RequestPtr &req, bool read);
146 const RequestPtr &req1, const RequestPtr &req2,
147 const RequestPtr &req,
300 const RequestPtr
[all...] |
| /gem5/src/mem/cache/prefetch/ |
| H A D | queued.hh | 69 RequestPtr translationRequest;
116 void setTranslationRequest(const RequestPtr &req)
124 void finish(const Fault &fault, const RequestPtr &req,
245 RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi,
|
| /gem5/src/arch/sparc/ |
| H A D | tlb.hh | 154 Fault translateInst(const RequestPtr &req, ThreadContext *tc);
155 Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
172 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
174 const RequestPtr &req, ThreadContext *tc,
177 const RequestPtr &req,
|
| /gem5/src/mem/ |
| H A D | abstract_mem.hh | 84 bool matchesContext(const RequestPtr &req) const
91 LockedAddr(const RequestPtr &req) : addr(mask(req->getPaddr())),
150 const RequestPtr &req = pkt->req;
|
| /gem5/src/cpu/o3/ |
| H A D | fetch.hh | 130 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
148 RequestPtr req;
160 void setReq(const RequestPtr &_req)
219 ProbePointArg<RequestPtr> *ppFetchRequestSent;
320 void finishTranslation(const Fault &fault, const RequestPtr &mem_req);
448 RequestPtr memReq[Impl::MaxThreads];
|
| /gem5/src/gpu-compute/ |
| H A D | gpu_tlb.hh | 116 virtual void finish(Fault fault, const RequestPtr &req,
180 Fault translateInt(const RequestPtr &req, ThreadContext *tc);
182 Fault translate(const RequestPtr &req, ThreadContext *tc,
225 Fault translateAtomic(const RequestPtr &req, ThreadContext *tc,
228 void translateTiming(const RequestPtr &req, ThreadContext *tc,
242 bool tlbLookup(const RequestPtr &req,
|
| /gem5/src/cpu/checker/ |
| H A D | cpu.cc | 143 RequestPtr
154 RequestPtr mem_req;
193 RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
278 RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
370 CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
|