Searched refs:r8 (Results 1 - 19 of 19) sorted by relevance

/gem5/system/arm/simple_bootloader/
H A Dsimple.S70 mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register
71 bics r8, r8, #0xff000000 // isolate the lower 24 bits (affinity levels)
73 mov r8, #1
74 str r8, [r4, #0] // Enable CPU interface on GIC
77 ldr r8, [r5] // load the value
78 movs r8, r8 // set the flags on this value
80 bx r8 // Jump to where we've been told
/gem5/ext/systemc/src/sysc/qt/md/
H A Dvax.s57 movl (sp)+,r8 /* Get `vuserf'. */
63 calls (sp)+,(r8) /* Call user's function. */
H A Dm88k_b.s64 add r8, r9,r0
69 add r8, r9,r0
75 add r8, r9,r0
80 add r8, r9,r0
H A Dm88k.s124 addu r8, r25,0 /* Set arg6. */
H A Dhppa.s55 stw %r8,-108(%sp)
86 ldw -108(%sp),%r8
H A Dpowerpc_mach.s611 lwz r8,PAR_9(r1)
H A Dpowerpc_sys5.s609 lwz %r8,PAR_9(%r1)
/gem5/system/alpha/palcode/
H A Dosfpal.S107 // r8 ITBmiss/DTBmiss scratch
268 cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl
269 bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl
294 srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7.
297 cmovge r9, r8, r12 // if .ge. 1d, then take shifted value
323 // This routine can use the PALshadow registers r8, r9, and r10
331 mfpr r8, ev5__ifault_va_form // Get virtual address of PTE.
337 ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss
343 and r8, osfpte_m_fo
[all...]
H A Dplatform.S239 OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
261 OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
263 OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg)
265 OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg)
850 lda r8, 0(r31) // passive release
856 lda r8, 0x680(r31) // UART0 RX vector
867 lda r8, 0x6c0(r31) // UART0 TX vector
873 lda r8, 0x690(r31) // UART1 RX vector
882 lda r8, 0x6d0(r31) // UART1 TX vector
891 beq r8,
[all...]
/gem5/src/arch/x86/
H A Dnativetrace.cc55 r8 = X86ISA::gtoh(r8);
82 r8 = tc->readIntReg(X86ISA::INTREG_R8);
164 checkReg("r8", mState.r8, nState.r8);
H A Dnativetrace.hh58 uint64_t r8; member in struct:Trace::X86NativeTrace::ThreadState
H A Dremote_gdb.hh108 uint64_t r8; member in struct:X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
H A Dremote_gdb.cc119 r.r8 = context->readIntReg(INTREG_R8);
171 context->setIntReg(INTREG_R8, r.r8);
/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/int_datatype/
H A Dint_datatype.cpp74 unsigned int r1, r2, r3, r4, r5, r6, r7, r8, r9; local
93 r8 = op1 || op2; // Logical OR
173 << "\n" << op1 << "\t || \t\t " << op2 << "\t = " << r8
/gem5/system/alpha/h/
H A Ddc21164FromGasSources.h697 #define r8 $8 macro
797 ** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and
801 #define p0 r8 /* ITB/DTB Miss Scratch */
/gem5/util/statetrace/arch/amd64/
H A Dtracechild.cc99 case R8: return myregs.r8;
/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_datatype/
H A Dstd_ulogic_datatype.cpp198 std_ulogic r1, r2, r3, r4, r5, r6, r7, r8, r9; local
217 // r8 = op1 || op2; // Logical OR
297 // << "\n" << op1 << "\t || \t\t " << op2 << "\t = " << r8
/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_vector_datatype/
H A Dstd_ulogic_vector_datatype.cpp494 std_ulogic_vector<4> r1, r2, r3, r4, r5, r6, r7, r8; local
517 // r8 = op1 || op2; // Logical OR
612 // << "\n" << op1 << "\t || \t\t " << op2 << "\t = " << r8
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc114 APPLY_IREG(r8, INTREG_R8); \

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