18012Ssaidi@eecs.umich.edu/* 28029Snate@binkert.org * Copyright (c) 2003-2006 The Regents of The University of Michigan 38029Snate@binkert.org * Copyright (c) 1992-1995 Hewlett-Packard Development Company 48029Snate@binkert.org * All rights reserved. 58012Ssaidi@eecs.umich.edu * 68029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 78029Snate@binkert.org * modification, are permitted provided that the following conditions are 88029Snate@binkert.org * met: redistributions of source code must retain the above copyright 98029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 108029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 118029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 128029Snate@binkert.org * documentation and/or other materials provided with the distribution; 138029Snate@binkert.org * neither the name of the copyright holders nor the names of its 148029Snate@binkert.org * contributors may be used to endorse or promote products derived from 158029Snate@binkert.org * this software without specific prior written permission. 168012Ssaidi@eecs.umich.edu * 178029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 188029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 198029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 208029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 218029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 228029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 238029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 248029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 258029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 268029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 278029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 288012Ssaidi@eecs.umich.edu * 298029Snate@binkert.org * Authors: Ali G. Saidi 308029Snate@binkert.org * Nathan L. Binkert 318013Sbinkertn@umich.edu */ 328012Ssaidi@eecs.umich.edu 338007Ssaidi@eecs.umich.edu// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl 348007Ssaidi@eecs.umich.edu// since we don't have a mechanism to expand the data structures.... pb Nov/95 358007Ssaidi@eecs.umich.edu#include "ev5_defs.h" 368007Ssaidi@eecs.umich.edu#include "ev5_impure.h" 378007Ssaidi@eecs.umich.edu#include "ev5_alpha_defs.h" 388007Ssaidi@eecs.umich.edu#include "ev5_paldef.h" 398007Ssaidi@eecs.umich.edu#include "ev5_osfalpha_defs.h" 408007Ssaidi@eecs.umich.edu#include "fromHudsonMacros.h" 418007Ssaidi@eecs.umich.edu#include "fromHudsonOsf.h" 428007Ssaidi@eecs.umich.edu#include "dc21164FromGasSources.h" 438007Ssaidi@eecs.umich.edu 448007Ssaidi@eecs.umich.edu#define DEBUGSTORE(c) nop 458007Ssaidi@eecs.umich.edu 468007Ssaidi@eecs.umich.edu#define DEBUG_EXC_ADDR()\ 478007Ssaidi@eecs.umich.edu bsr r25, put_exc_addr; \ 488007Ssaidi@eecs.umich.edu DEBUGSTORE(13) ; \ 498007Ssaidi@eecs.umich.edu DEBUGSTORE(10) 508007Ssaidi@eecs.umich.edu 518013Sbinkertn@umich.edu// This is the fix for the user-mode super page references causing the 528013Sbinkertn@umich.edu// machine to crash. 538007Ssaidi@eecs.umich.edu#define hw_rei_spe hw_rei 548013Sbinkertn@umich.edu 558007Ssaidi@eecs.umich.edu#define vmaj 1 568007Ssaidi@eecs.umich.edu#define vmin 18 578007Ssaidi@eecs.umich.edu#define vms_pal 1 588007Ssaidi@eecs.umich.edu#define osf_pal 2 598007Ssaidi@eecs.umich.edu#define pal_type osf_pal 608007Ssaidi@eecs.umich.edu#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0)) 618013Sbinkertn@umich.edu 628013Sbinkertn@umich.edu 638013Sbinkertn@umich.edu/////////////////////////// 648013Sbinkertn@umich.edu// PALtemp register usage 658013Sbinkertn@umich.edu/////////////////////////// 668013Sbinkertn@umich.edu 678007Ssaidi@eecs.umich.edu// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage 688007Ssaidi@eecs.umich.edu// for these PALtemps: 698007Ssaidi@eecs.umich.edu// 708007Ssaidi@eecs.umich.edu// pt0 local scratch 718007Ssaidi@eecs.umich.edu// pt1 local scratch 728007Ssaidi@eecs.umich.edu// pt2 entUna pt_entUna 738007Ssaidi@eecs.umich.edu// pt3 CPU specific impure area pointer pt_impure 748007Ssaidi@eecs.umich.edu// pt4 memory management temp 758007Ssaidi@eecs.umich.edu// pt5 memory management temp 768007Ssaidi@eecs.umich.edu// pt6 memory management temp 778007Ssaidi@eecs.umich.edu// pt7 entIF pt_entIF 788007Ssaidi@eecs.umich.edu// pt8 intmask pt_intmask 798007Ssaidi@eecs.umich.edu// pt9 entSys pt_entSys 808007Ssaidi@eecs.umich.edu// pt10 818007Ssaidi@eecs.umich.edu// pt11 entInt pt_entInt 828007Ssaidi@eecs.umich.edu// pt12 entArith pt_entArith 838007Ssaidi@eecs.umich.edu// pt13 reserved for system specific PAL 848007Ssaidi@eecs.umich.edu// pt14 reserved for system specific PAL 858007Ssaidi@eecs.umich.edu// pt15 reserved for system specific PAL 868013Sbinkertn@umich.edu// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, 878013Sbinkertn@umich.edu// pt_mces 888007Ssaidi@eecs.umich.edu// pt17 sysval pt_sysval 898007Ssaidi@eecs.umich.edu// pt18 usp pt_usp 908007Ssaidi@eecs.umich.edu// pt19 ksp pt_ksp 918007Ssaidi@eecs.umich.edu// pt20 PTBR pt_ptbr 928007Ssaidi@eecs.umich.edu// pt21 entMM pt_entMM 938007Ssaidi@eecs.umich.edu// pt22 kgp pt_kgp 948007Ssaidi@eecs.umich.edu// pt23 PCBB pt_pcbb 958007Ssaidi@eecs.umich.edu// 968013Sbinkertn@umich.edu// 978013Sbinkertn@umich.edu 988013Sbinkertn@umich.edu 998013Sbinkertn@umich.edu///////////////////////////// 1008013Sbinkertn@umich.edu// PALshadow register usage 1018013Sbinkertn@umich.edu///////////////////////////// 1028013Sbinkertn@umich.edu 1038007Ssaidi@eecs.umich.edu// 1048007Ssaidi@eecs.umich.edu// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1. 1058007Ssaidi@eecs.umich.edu// This maps the OSF PAL usage of R8 - R14 and R25: 1068007Ssaidi@eecs.umich.edu// 1078007Ssaidi@eecs.umich.edu// r8 ITBmiss/DTBmiss scratch 1088007Ssaidi@eecs.umich.edu// r9 ITBmiss/DTBmiss scratch 1098007Ssaidi@eecs.umich.edu// r10 ITBmiss/DTBmiss scratch 1108007Ssaidi@eecs.umich.edu// r11 PS 1118007Ssaidi@eecs.umich.edu// r12 local scratch 1128007Ssaidi@eecs.umich.edu// r13 local scratch 1138007Ssaidi@eecs.umich.edu// r14 local scratch 1148007Ssaidi@eecs.umich.edu// r25 local scratch 1158007Ssaidi@eecs.umich.edu// 1168007Ssaidi@eecs.umich.edu 1178007Ssaidi@eecs.umich.edu 1188007Ssaidi@eecs.umich.edu 1198007Ssaidi@eecs.umich.edu// .sbttl "PALcode configuration options" 1208007Ssaidi@eecs.umich.edu 1218007Ssaidi@eecs.umich.edu// There are a number of options that may be assembled into this version of 1228007Ssaidi@eecs.umich.edu// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit 1238007Ssaidi@eecs.umich.edu// the following). The options that can be adjusted cause the resultant PALcode 1248007Ssaidi@eecs.umich.edu// to reflect the desired target system. 1258007Ssaidi@eecs.umich.edu 1268007Ssaidi@eecs.umich.edu// multiprocessor support can be enabled for a max of n processors by 1278007Ssaidi@eecs.umich.edu// setting the following to the number of processors on the system. 1288007Ssaidi@eecs.umich.edu// Note that this is really the max cpuid. 1298007Ssaidi@eecs.umich.edu 1308013Sbinkertn@umich.edu#define max_cpuid 1 1318007Ssaidi@eecs.umich.edu#ifndef max_cpuid 1328007Ssaidi@eecs.umich.edu#define max_cpuid 8 1338007Ssaidi@eecs.umich.edu#endif 1348007Ssaidi@eecs.umich.edu 1358013Sbinkertn@umich.edu#define osf_svmin 1 1368007Ssaidi@eecs.umich.edu#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0)) 1378007Ssaidi@eecs.umich.edu 1388013Sbinkertn@umich.edu// 1398013Sbinkertn@umich.edu// RESET - Reset Trap Entry Point 1408013Sbinkertn@umich.edu// 1418007Ssaidi@eecs.umich.edu// RESET - offset 0000 1428007Ssaidi@eecs.umich.edu// Entry: 1438007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on reset, or branched to 1448007Ssaidi@eecs.umich.edu// on swppal. 1458007Ssaidi@eecs.umich.edu// 1468007Ssaidi@eecs.umich.edu// r0 = whami 1478007Ssaidi@eecs.umich.edu// r1 = pal_base 1488007Ssaidi@eecs.umich.edu// r2 = base of scratch area 1498007Ssaidi@eecs.umich.edu// r3 = halt code 1508007Ssaidi@eecs.umich.edu// 1518007Ssaidi@eecs.umich.edu// 1528007Ssaidi@eecs.umich.edu// Function: 1538007Ssaidi@eecs.umich.edu// 1548013Sbinkertn@umich.edu// 1558007Ssaidi@eecs.umich.edu 1568007Ssaidi@eecs.umich.edu .text 0 1578007Ssaidi@eecs.umich.edu . = 0x0000 1588013Sbinkertn@umich.edu .globl _start 1598007Ssaidi@eecs.umich.edu .globl Pal_Base 1608013Sbinkertn@umich.edu_start: 1618007Ssaidi@eecs.umich.eduPal_Base: 1628007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_RESET_ENTRY) 1638007Ssaidi@eecs.umich.eduTrap_Reset: 1648007Ssaidi@eecs.umich.edu nop 1658007Ssaidi@eecs.umich.edu /* 1668007Ssaidi@eecs.umich.edu * store into r1 1678007Ssaidi@eecs.umich.edu */ 1688007Ssaidi@eecs.umich.edu br r1,sys_reset 1698007Ssaidi@eecs.umich.edu 1708007Ssaidi@eecs.umich.edu // Specify PAL version info as a constant 1718007Ssaidi@eecs.umich.edu // at a known location (reset + 8). 1728007Ssaidi@eecs.umich.edu 1738007Ssaidi@eecs.umich.edu .long osfpal_version_l // <pal_type@16> ! <vmaj@8> ! <vmin@0> 1748007Ssaidi@eecs.umich.edu .long osfpal_version_h // <max_cpuid@16> ! <osf_svmin@0> 1758007Ssaidi@eecs.umich.edu .long 0 1768007Ssaidi@eecs.umich.edu .long 0 1778007Ssaidi@eecs.umich.edupal_impure_start: 1788007Ssaidi@eecs.umich.edu .quad 0 1798007Ssaidi@eecs.umich.edupal_debug_ptr: 1808007Ssaidi@eecs.umich.edu .quad 0 // reserved for debug pointer ; 20 1818013Sbinkertn@umich.edu 1828013Sbinkertn@umich.edu 1838013Sbinkertn@umich.edu// 1848013Sbinkertn@umich.edu// IACCVIO - Istream Access Violation Trap Entry Point 1858013Sbinkertn@umich.edu// 1868007Ssaidi@eecs.umich.edu// IACCVIO - offset 0080 1878007Ssaidi@eecs.umich.edu// Entry: 1888007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on Istream access violation or sign check error on PC. 1898007Ssaidi@eecs.umich.edu// 1908007Ssaidi@eecs.umich.edu// Function: 1918007Ssaidi@eecs.umich.edu// Build stack frame 1928007Ssaidi@eecs.umich.edu// a0 <- Faulting VA 1938007Ssaidi@eecs.umich.edu// a1 <- MMCSR (1 for ACV) 1948007Ssaidi@eecs.umich.edu// a2 <- -1 (for ifetch fault) 1958007Ssaidi@eecs.umich.edu// vector via entMM 1968013Sbinkertn@umich.edu// 1978007Ssaidi@eecs.umich.edu 1988007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_IACCVIO_ENTRY) 1998007Ssaidi@eecs.umich.eduTrap_Iaccvio: 2008007Ssaidi@eecs.umich.edu DEBUGSTORE(0x42) 2018007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 2028007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 2038007Ssaidi@eecs.umich.edu 2048007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 2058007Ssaidi@eecs.umich.edu bge r25, TRAP_IACCVIO_10_ // no stack swap needed if cm=kern 2068007Ssaidi@eecs.umich.edu 2078007Ssaidi@eecs.umich.edu 2088007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 2098007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 2108007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 2118007Ssaidi@eecs.umich.edu 2128007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 2138007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 2148007Ssaidi@eecs.umich.edu 2158007Ssaidi@eecs.umich.eduTRAP_IACCVIO_10_: 2168007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 2178007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 2188007Ssaidi@eecs.umich.edu 2198007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 2208007Ssaidi@eecs.umich.edu bic r14, 3, r16 // pass pc/va as a0 2218007Ssaidi@eecs.umich.edu 2228007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 2238007Ssaidi@eecs.umich.edu or r31, mmcsr_c_acv, r17 // pass mm_csr as a1 2248007Ssaidi@eecs.umich.edu 2258007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 2268007Ssaidi@eecs.umich.edu mfpr r13, pt_entmm // get entry point 2278007Ssaidi@eecs.umich.edu 2288007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 2298007Ssaidi@eecs.umich.edu bis r12, r31, r11 // update ps 2308007Ssaidi@eecs.umich.edu 2318007Ssaidi@eecs.umich.edu stq r16, osfsf_pc(sp) // save pc 2328007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 2338007Ssaidi@eecs.umich.edu 2348007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entMM 2358007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 2368007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 2378007Ssaidi@eecs.umich.edu 2388007Ssaidi@eecs.umich.edu subq r31, 1, r18 // pass flag of istream, as a2 2398007Ssaidi@eecs.umich.edu hw_rei_spe 2408007Ssaidi@eecs.umich.edu 2418007Ssaidi@eecs.umich.edu 2428013Sbinkertn@umich.edu// 2438013Sbinkertn@umich.edu// INTERRUPT - Interrupt Trap Entry Point 2448013Sbinkertn@umich.edu// 2458007Ssaidi@eecs.umich.edu// INTERRUPT - offset 0100 2468007Ssaidi@eecs.umich.edu// Entry: 2478007Ssaidi@eecs.umich.edu// Vectored into via trap on hardware interrupt 2488007Ssaidi@eecs.umich.edu// 2498007Ssaidi@eecs.umich.edu// Function: 2508007Ssaidi@eecs.umich.edu// check for halt interrupt 2518007Ssaidi@eecs.umich.edu// check for passive release (current ipl geq requestor) 2528013Sbinkertn@umich.edu// if necessary, switch to kernel mode push stack frame, 2538013Sbinkertn@umich.edu// update ps (including current mode and ipl copies), sp, and gp 2548007Ssaidi@eecs.umich.edu// pass the interrupt info to the system module 2558007Ssaidi@eecs.umich.edu// 2568013Sbinkertn@umich.edu// 2578007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_INTERRUPT_ENTRY) 2588007Ssaidi@eecs.umich.eduTrap_Interrupt: 2598007Ssaidi@eecs.umich.edu mfpr r13, ev5__intid // Fetch level of interruptor 2608007Ssaidi@eecs.umich.edu mfpr r25, ev5__isr // Fetch interrupt summary register 2618007Ssaidi@eecs.umich.edu 2628007Ssaidi@eecs.umich.edu srl r25, isr_v_hlt, r9 // Get HLT bit 2638007Ssaidi@eecs.umich.edu mfpr r14, ev5__ipl 2648007Ssaidi@eecs.umich.edu 2658007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern 2668007Ssaidi@eecs.umich.edu blbs r9, sys_halt_interrupt // halt_interrupt if HLT bit set 2678007Ssaidi@eecs.umich.edu 2688007Ssaidi@eecs.umich.edu cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl 2698007Ssaidi@eecs.umich.edu bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl 2708007Ssaidi@eecs.umich.edu 2718007Ssaidi@eecs.umich.edu and r11, osfps_m_mode, r10 // get mode bit 2728007Ssaidi@eecs.umich.edu beq r10, TRAP_INTERRUPT_10_ // Skip stack swap in kernel 2738007Ssaidi@eecs.umich.edu 2748007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 2758007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp // get kern stack 2768007Ssaidi@eecs.umich.edu 2778007Ssaidi@eecs.umich.eduTRAP_INTERRUPT_10_: 2788007Ssaidi@eecs.umich.edu lda sp, (0-osfsf_c_size)(sp)// allocate stack space 2798007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 2808007Ssaidi@eecs.umich.edu 2818007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save ps 2828007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 2838007Ssaidi@eecs.umich.edu 2848007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // push gp 2858007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // a0 2868007Ssaidi@eecs.umich.edu 2878007Ssaidi@eecs.umich.edu// pvc_violate 354 // ps is cleared anyway, if store to stack faults. 2888007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 2898007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 2908007Ssaidi@eecs.umich.edu 2918007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 2928007Ssaidi@eecs.umich.edu subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL 2938007Ssaidi@eecs.umich.edu 2948007Ssaidi@eecs.umich.edu srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7. 2958007Ssaidi@eecs.umich.edu subq r13, 0x1d, r9 // Check for 1d, 1e, 1f 2968007Ssaidi@eecs.umich.edu 2978007Ssaidi@eecs.umich.edu cmovge r9, r8, r12 // if .ge. 1d, then take shifted value 2988007Ssaidi@eecs.umich.edu bis r12, r31, r11 // set new ps 2998007Ssaidi@eecs.umich.edu 3008007Ssaidi@eecs.umich.edu mfpr r12, pt_intmask 3018007Ssaidi@eecs.umich.edu and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already) 3028007Ssaidi@eecs.umich.edu 3038007Ssaidi@eecs.umich.edu /* 3048007Ssaidi@eecs.umich.edu * Lance had space problems. We don't. 3058007Ssaidi@eecs.umich.edu */ 3068007Ssaidi@eecs.umich.edu extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL 3078007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // update gp 3088007Ssaidi@eecs.umich.edu mtpr r14, ev5__ipl // load the new IPL into Ibox 3098007Ssaidi@eecs.umich.edu br r31, sys_interrupt // Go handle interrupt 3108007Ssaidi@eecs.umich.edu 3118007Ssaidi@eecs.umich.edu 3128007Ssaidi@eecs.umich.edu 3138013Sbinkertn@umich.edu// 3148013Sbinkertn@umich.edu// ITBMISS - Istream TBmiss Trap Entry Point 3158013Sbinkertn@umich.edu// 3168007Ssaidi@eecs.umich.edu// ITBMISS - offset 0180 3178007Ssaidi@eecs.umich.edu// Entry: 3188007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on Istream translation buffer miss. 3198007Ssaidi@eecs.umich.edu// 3208007Ssaidi@eecs.umich.edu// Function: 3218007Ssaidi@eecs.umich.edu// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid. 3228007Ssaidi@eecs.umich.edu// Can trap into DTBMISS_DOUBLE. 3238007Ssaidi@eecs.umich.edu// This routine can use the PALshadow registers r8, r9, and r10 3248007Ssaidi@eecs.umich.edu// 3258013Sbinkertn@umich.edu// 3268007Ssaidi@eecs.umich.edu 3278007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_ITB_MISS_ENTRY) 3288007Ssaidi@eecs.umich.eduTrap_Itbmiss: 3298013Sbinkertn@umich.edu // Real MM mapping 3308007Ssaidi@eecs.umich.edu nop 3318007Ssaidi@eecs.umich.edu mfpr r8, ev5__ifault_va_form // Get virtual address of PTE. 3328007Ssaidi@eecs.umich.edu 3338007Ssaidi@eecs.umich.edu nop 3348007Ssaidi@eecs.umich.edu mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss. 3358007Ssaidi@eecs.umich.edu 3368007Ssaidi@eecs.umich.edupal_itb_ldq: 3378007Ssaidi@eecs.umich.edu ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss 3388007Ssaidi@eecs.umich.edu mtpr r10, exc_addr // Restore exc_address if there was a trap. 3398007Ssaidi@eecs.umich.edu 3408007Ssaidi@eecs.umich.edu mfpr r31, ev5__va // Unlock VA in case there was a double miss 3418007Ssaidi@eecs.umich.edu nop 3428007Ssaidi@eecs.umich.edu 3438007Ssaidi@eecs.umich.edu and r8, osfpte_m_foe, r25 // Look for FOE set. 3448007Ssaidi@eecs.umich.edu blbc r8, invalid_ipte_handler // PTE not valid. 3458007Ssaidi@eecs.umich.edu 3468007Ssaidi@eecs.umich.edu nop 3478007Ssaidi@eecs.umich.edu bne r25, foe_ipte_handler // FOE is set 3488007Ssaidi@eecs.umich.edu 3498007Ssaidi@eecs.umich.edu nop 3508007Ssaidi@eecs.umich.edu mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB. 3518007Ssaidi@eecs.umich.edu 3528007Ssaidi@eecs.umich.edu hw_rei_stall // 3538007Ssaidi@eecs.umich.edu 3548013Sbinkertn@umich.edu 3558013Sbinkertn@umich.edu// 3568013Sbinkertn@umich.edu// DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point 3578013Sbinkertn@umich.edu// 3588007Ssaidi@eecs.umich.edu// DTBMISS_SINGLE - offset 0200 3598007Ssaidi@eecs.umich.edu// Entry: 3608013Sbinkertn@umich.edu// Vectored into via hardware trap on Dstream single translation 3618013Sbinkertn@umich.edu// buffer miss. 3628007Ssaidi@eecs.umich.edu// 3638007Ssaidi@eecs.umich.edu// Function: 3648007Ssaidi@eecs.umich.edu// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid. 3658007Ssaidi@eecs.umich.edu// Can trap into DTBMISS_DOUBLE. 3668007Ssaidi@eecs.umich.edu// This routine can use the PALshadow registers r8, r9, and r10 3678013Sbinkertn@umich.edu// 3688007Ssaidi@eecs.umich.edu 3698007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_DTB_MISS_ENTRY) 3708007Ssaidi@eecs.umich.eduTrap_Dtbmiss_Single: 3718007Ssaidi@eecs.umich.edu mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0. 3728007Ssaidi@eecs.umich.edu mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1. 3738007Ssaidi@eecs.umich.edu 3748007Ssaidi@eecs.umich.edu// DEBUGSTORE(0x45) 3758007Ssaidi@eecs.umich.edu// DEBUG_EXC_ADDR() 3768007Ssaidi@eecs.umich.edu // Real MM mapping 3778007Ssaidi@eecs.umich.edu mfpr r9, ev5__mm_stat // Get read/write bit. E0. 3788007Ssaidi@eecs.umich.edu mtpr r10, pt6 // Stash exc_addr away 3798007Ssaidi@eecs.umich.edu 3808007Ssaidi@eecs.umich.edupal_dtb_ldq: 3818007Ssaidi@eecs.umich.edu ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss 3828007Ssaidi@eecs.umich.edu nop // Pad MF VA 3838007Ssaidi@eecs.umich.edu 3848007Ssaidi@eecs.umich.edu mfpr r10, ev5__va // Get original faulting VA for TB load. E0. 3858007Ssaidi@eecs.umich.edu nop 3868007Ssaidi@eecs.umich.edu 3878007Ssaidi@eecs.umich.edu mtpr r8, ev5__dtb_pte // Write DTB PTE part. E0. 3888007Ssaidi@eecs.umich.edu blbc r8, invalid_dpte_handler // Handle invalid PTE 3898007Ssaidi@eecs.umich.edu 3908007Ssaidi@eecs.umich.edu mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles. 3918007Ssaidi@eecs.umich.edu mfpr r10, pt6 3928007Ssaidi@eecs.umich.edu 3938007Ssaidi@eecs.umich.edu // Following 2 instructions take 2 cycles 3948007Ssaidi@eecs.umich.edu mtpr r10, exc_addr // Return linkage in case we trapped. E1. 3958007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad the write to dtb_tag 3968007Ssaidi@eecs.umich.edu 3978007Ssaidi@eecs.umich.edu hw_rei // Done, return 3988013Sbinkertn@umich.edu 3998013Sbinkertn@umich.edu 4008013Sbinkertn@umich.edu// 4018013Sbinkertn@umich.edu// DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point 4028013Sbinkertn@umich.edu// 4038013Sbinkertn@umich.edu// 4048007Ssaidi@eecs.umich.edu// DTBMISS_DOUBLE - offset 0280 4058007Ssaidi@eecs.umich.edu// Entry: 4068013Sbinkertn@umich.edu// Vectored into via hardware trap on Double TBmiss from single 4078013Sbinkertn@umich.edu// miss flows. 4088007Ssaidi@eecs.umich.edu// 4098007Ssaidi@eecs.umich.edu// r8 - faulting VA 4108007Ssaidi@eecs.umich.edu// r9 - original MMstat 4118007Ssaidi@eecs.umich.edu// r10 - original exc_addr (both itb,dtb miss) 4128007Ssaidi@eecs.umich.edu// pt6 - original exc_addr (dtb miss flow only) 4138007Ssaidi@eecs.umich.edu// VA IPR - locked with original faulting VA 4148007Ssaidi@eecs.umich.edu// 4158007Ssaidi@eecs.umich.edu// Function: 4168007Ssaidi@eecs.umich.edu// Get PTE, if valid load TB and return. 4178007Ssaidi@eecs.umich.edu// If not valid then take TNV/ACV exception. 4188007Ssaidi@eecs.umich.edu// 4198007Ssaidi@eecs.umich.edu// pt4 and pt5 are reserved for this flow. 4208007Ssaidi@eecs.umich.edu// 4218007Ssaidi@eecs.umich.edu// 4228013Sbinkertn@umich.edu// 4238007Ssaidi@eecs.umich.edu 4248007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY) 4258007Ssaidi@eecs.umich.eduTrap_Dtbmiss_double: 4268007Ssaidi@eecs.umich.edu mtpr r8, pt4 // save r8 to do exc_addr check 4278007Ssaidi@eecs.umich.edu mfpr r8, exc_addr 4288007Ssaidi@eecs.umich.edu blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy! 4298007Ssaidi@eecs.umich.edu mfpr r8, pt4 // restore r8 4308007Ssaidi@eecs.umich.edu nop 4318007Ssaidi@eecs.umich.edu mtpr r22, pt5 // Get some scratch space. E1. 4328007Ssaidi@eecs.umich.edu // Due to virtual scheme, we can skip the first lookup and go 4338007Ssaidi@eecs.umich.edu // right to fetch of level 2 PTE 4348007Ssaidi@eecs.umich.edu sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA 4358007Ssaidi@eecs.umich.edu mtpr r21, pt4 // Get some scratch space. E1. 4368007Ssaidi@eecs.umich.edu 4378007Ssaidi@eecs.umich.edu srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 4388007Ssaidi@eecs.umich.edu mfpr r21, pt_ptbr // Get physical address of the page table. 4398007Ssaidi@eecs.umich.edu 4408007Ssaidi@eecs.umich.edu nop 4418007Ssaidi@eecs.umich.edu addq r21, r22, r21 // Index into page table for level 2 PTE. 4428007Ssaidi@eecs.umich.edu 4438007Ssaidi@eecs.umich.edu sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA 4448013Sbinkertn@umich.edu ldq_p r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored) 4458007Ssaidi@eecs.umich.edu 4468007Ssaidi@eecs.umich.edu srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 4478007Ssaidi@eecs.umich.edu blbc r21, double_pte_inv // Check for Invalid PTE. 4488007Ssaidi@eecs.umich.edu 4498007Ssaidi@eecs.umich.edu srl r21, 32, r21 // extract PFN from PTE 4508007Ssaidi@eecs.umich.edu sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to <seg3>*8 4518007Ssaidi@eecs.umich.edu 4528007Ssaidi@eecs.umich.edu addq r21, r22, r21 // Index into page table for level 3 PTE. 4538007Ssaidi@eecs.umich.edu nop 4548007Ssaidi@eecs.umich.edu 4558013Sbinkertn@umich.edu ldq_p r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored) 4568007Ssaidi@eecs.umich.edu blbc r21, double_pte_inv // Check for invalid PTE. 4578007Ssaidi@eecs.umich.edu 4588007Ssaidi@eecs.umich.edu mtpr r21, ev5__dtb_pte // Write the PTE. E0. 4598007Ssaidi@eecs.umich.edu mfpr r22, pt5 // Restore scratch register 4608007Ssaidi@eecs.umich.edu 4618007Ssaidi@eecs.umich.edu mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles. 4628007Ssaidi@eecs.umich.edu mfpr r21, pt4 // Restore scratch register 4638007Ssaidi@eecs.umich.edu 4648007Ssaidi@eecs.umich.edu nop // Pad write to tag. 4658007Ssaidi@eecs.umich.edu nop 4668007Ssaidi@eecs.umich.edu 4678007Ssaidi@eecs.umich.edu nop // Pad write to tag. 4688007Ssaidi@eecs.umich.edu nop 4698007Ssaidi@eecs.umich.edu 4708007Ssaidi@eecs.umich.edu hw_rei 4718007Ssaidi@eecs.umich.edu 4728007Ssaidi@eecs.umich.edu 4738007Ssaidi@eecs.umich.edu 4748013Sbinkertn@umich.edu// 4758013Sbinkertn@umich.edu// UNALIGN -- Dstream unalign trap 4768013Sbinkertn@umich.edu// 4778007Ssaidi@eecs.umich.edu// UNALIGN - offset 0300 4788007Ssaidi@eecs.umich.edu// Entry: 4798007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on unaligned Dstream reference. 4808007Ssaidi@eecs.umich.edu// 4818007Ssaidi@eecs.umich.edu// Function: 4828007Ssaidi@eecs.umich.edu// Build stack frame 4838007Ssaidi@eecs.umich.edu// a0 <- Faulting VA 4848007Ssaidi@eecs.umich.edu// a1 <- Opcode 4858007Ssaidi@eecs.umich.edu// a2 <- src/dst register number 4868007Ssaidi@eecs.umich.edu// vector via entUna 4878013Sbinkertn@umich.edu// 4888007Ssaidi@eecs.umich.edu 4898007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_UNALIGN_ENTRY) 4908007Ssaidi@eecs.umich.eduTrap_Unalign: 4918007Ssaidi@eecs.umich.edu/* DEBUGSTORE(0x47)*/ 4928007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 4938007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 4948007Ssaidi@eecs.umich.edu 4958007Ssaidi@eecs.umich.edu mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss 4968007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 4978007Ssaidi@eecs.umich.edu 4988007Ssaidi@eecs.umich.edu srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits 4998007Ssaidi@eecs.umich.edu blbs r14, pal_pal_bug_check // Bugcheck if unaligned in PAL 5008007Ssaidi@eecs.umich.edu 5018007Ssaidi@eecs.umich.edu blbs r8, UNALIGN_NO_DISMISS // lsb only set on store or fetch_m 5028007Ssaidi@eecs.umich.edu // not set, must be a load 5038007Ssaidi@eecs.umich.edu and r13, 0x1F, r8 // isolate ra 5048007Ssaidi@eecs.umich.edu 5058007Ssaidi@eecs.umich.edu cmpeq r8, 0x1F, r8 // check for r31/F31 5068007Ssaidi@eecs.umich.edu bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault 5078007Ssaidi@eecs.umich.edu 5088007Ssaidi@eecs.umich.eduUNALIGN_NO_DISMISS: 5098007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 5108007Ssaidi@eecs.umich.edu bge r25, UNALIGN_NO_DISMISS_10_ // no stack swap needed if cm=kern 5118007Ssaidi@eecs.umich.edu 5128007Ssaidi@eecs.umich.edu 5138007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 5148007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 5158007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 5168007Ssaidi@eecs.umich.edu 5178007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 5188007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 5198007Ssaidi@eecs.umich.edu 5208007Ssaidi@eecs.umich.eduUNALIGN_NO_DISMISS_10_: 5218007Ssaidi@eecs.umich.edu mfpr r25, ev5__va // Unlock VA 5228007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 5238007Ssaidi@eecs.umich.edu 5248007Ssaidi@eecs.umich.edu mtpr r25, pt0 // Stash VA 5258007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 5268007Ssaidi@eecs.umich.edu 5278007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 5288007Ssaidi@eecs.umich.edu srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode 5298007Ssaidi@eecs.umich.edu 5308007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 5318007Ssaidi@eecs.umich.edu addq r14, 4, r14 // inc PC past the ld/st 5328007Ssaidi@eecs.umich.edu 5338007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 5348007Ssaidi@eecs.umich.edu and r25, mm_stat_m_opcode, r17// Clean opocde for a1 5358007Ssaidi@eecs.umich.edu 5368007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 5378007Ssaidi@eecs.umich.edu mfpr r16, pt0 // a0 <- va/unlock 5388007Ssaidi@eecs.umich.edu 5398007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 5408007Ssaidi@eecs.umich.edu mfpr r25, pt_entuna // get entry point 5418007Ssaidi@eecs.umich.edu 5428007Ssaidi@eecs.umich.edu 5438007Ssaidi@eecs.umich.edu bis r12, r31, r11 // update ps 5448007Ssaidi@eecs.umich.edu br r31, unalign_trap_cont 5458007Ssaidi@eecs.umich.edu 5468007Ssaidi@eecs.umich.edu 5478013Sbinkertn@umich.edu// 5488013Sbinkertn@umich.edu// DFAULT - Dstream Fault Trap Entry Point 5498013Sbinkertn@umich.edu// 5508007Ssaidi@eecs.umich.edu// DFAULT - offset 0380 5518007Ssaidi@eecs.umich.edu// Entry: 5528013Sbinkertn@umich.edu// Vectored into via hardware trap on dstream fault or sign check 5538013Sbinkertn@umich.edu// error on DVA. 5548007Ssaidi@eecs.umich.edu// 5558007Ssaidi@eecs.umich.edu// Function: 5568007Ssaidi@eecs.umich.edu// Ignore faults on FETCH/FETCH_M 5578007Ssaidi@eecs.umich.edu// Check for DFAULT in PAL 5588007Ssaidi@eecs.umich.edu// Build stack frame 5598007Ssaidi@eecs.umich.edu// a0 <- Faulting VA 5608007Ssaidi@eecs.umich.edu// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW) 5618007Ssaidi@eecs.umich.edu// a2 <- R/W 5628007Ssaidi@eecs.umich.edu// vector via entMM 5638007Ssaidi@eecs.umich.edu// 5648013Sbinkertn@umich.edu// 5658007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_D_FAULT_ENTRY) 5668007Ssaidi@eecs.umich.eduTrap_Dfault: 5678007Ssaidi@eecs.umich.edu// DEBUGSTORE(0x48) 5688007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 5698007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 5708007Ssaidi@eecs.umich.edu 5718007Ssaidi@eecs.umich.edu mfpr r13, ev5__mm_stat // Get mmstat 5728007Ssaidi@eecs.umich.edu mfpr r8, exc_addr // get pc, preserve r14 5738007Ssaidi@eecs.umich.edu 5748007Ssaidi@eecs.umich.edu srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits 5758007Ssaidi@eecs.umich.edu blbs r8, dfault_in_pal 5768007Ssaidi@eecs.umich.edu 5778007Ssaidi@eecs.umich.edu bis r8, r31, r14 // move exc_addr to correct place 5788007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 5798007Ssaidi@eecs.umich.edu 5808007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 5818007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 5828007Ssaidi@eecs.umich.edu and r9, mm_stat_m_opcode, r9 // Clean all but opcode 5838007Ssaidi@eecs.umich.edu 5848007Ssaidi@eecs.umich.edu cmpeq r9, evx_opc_sync, r9 // Is the opcode fetch/fetchm? 5858007Ssaidi@eecs.umich.edu bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault 5868007Ssaidi@eecs.umich.edu 5878007Ssaidi@eecs.umich.edu //dismiss exception if load to r31/f31 5888007Ssaidi@eecs.umich.edu blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm 5898007Ssaidi@eecs.umich.edu 5908007Ssaidi@eecs.umich.edu // not a store or fetch, must be a load 5918007Ssaidi@eecs.umich.edu srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits 5928007Ssaidi@eecs.umich.edu 5938007Ssaidi@eecs.umich.edu and r9, 0x1F, r9 // isolate rnum 5948007Ssaidi@eecs.umich.edu nop 5958007Ssaidi@eecs.umich.edu 5968007Ssaidi@eecs.umich.edu cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31? 5978007Ssaidi@eecs.umich.edu bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault 5988007Ssaidi@eecs.umich.edu 5998007Ssaidi@eecs.umich.edudfault_no_dismiss: 6008007Ssaidi@eecs.umich.edu and r13, 0xf, r13 // Clean extra bits in mm_stat 6018007Ssaidi@eecs.umich.edu bge r25, dfault_trap_cont // no stack swap needed if cm=kern 6028007Ssaidi@eecs.umich.edu 6038007Ssaidi@eecs.umich.edu 6048007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 6058007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 6068007Ssaidi@eecs.umich.edu 6078007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 6088007Ssaidi@eecs.umich.edu br r31, dfault_trap_cont 6098007Ssaidi@eecs.umich.edu 6108007Ssaidi@eecs.umich.edu 6118013Sbinkertn@umich.edu// 6128013Sbinkertn@umich.edu// MCHK - Machine Check Trap Entry Point 6138013Sbinkertn@umich.edu// 6148007Ssaidi@eecs.umich.edu// MCHK - offset 0400 6158007Ssaidi@eecs.umich.edu// Entry: 6168007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on machine check. 6178007Ssaidi@eecs.umich.edu// 6188007Ssaidi@eecs.umich.edu// Function: 6198007Ssaidi@eecs.umich.edu// 6208013Sbinkertn@umich.edu// 6218007Ssaidi@eecs.umich.edu 6228007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_MCHK_ENTRY) 6238007Ssaidi@eecs.umich.eduTrap_Mchk: 6248007Ssaidi@eecs.umich.edu DEBUGSTORE(0x49) 6258007Ssaidi@eecs.umich.edu mtpr r31, ic_flush_ctl // Flush the Icache 6268007Ssaidi@eecs.umich.edu br r31, sys_machine_check 6278007Ssaidi@eecs.umich.edu 6288007Ssaidi@eecs.umich.edu 6298013Sbinkertn@umich.edu// 6308013Sbinkertn@umich.edu// OPCDEC - Illegal Opcode Trap Entry Point 6318013Sbinkertn@umich.edu// 6328007Ssaidi@eecs.umich.edu// OPCDEC - offset 0480 6338007Ssaidi@eecs.umich.edu// Entry: 6348007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on illegal opcode. 6358007Ssaidi@eecs.umich.edu// 6368007Ssaidi@eecs.umich.edu// Build stack frame 6378007Ssaidi@eecs.umich.edu// a0 <- code 6388007Ssaidi@eecs.umich.edu// a1 <- unpred 6398007Ssaidi@eecs.umich.edu// a2 <- unpred 6408007Ssaidi@eecs.umich.edu// vector via entIF 6418007Ssaidi@eecs.umich.edu// 6428013Sbinkertn@umich.edu// 6438007Ssaidi@eecs.umich.edu 6448007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_OPCDEC_ENTRY) 6458007Ssaidi@eecs.umich.eduTrap_Opcdec: 6468007Ssaidi@eecs.umich.edu DEBUGSTORE(0x4a) 6478007Ssaidi@eecs.umich.edu//simos DEBUG_EXC_ADDR() 6488007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 6498007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 6508007Ssaidi@eecs.umich.edu 6518007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 6528007Ssaidi@eecs.umich.edu blbs r14, pal_pal_bug_check // check opcdec in palmode 6538007Ssaidi@eecs.umich.edu 6548007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 6558007Ssaidi@eecs.umich.edu bge r25, TRAP_OPCDEC_10_ // no stack swap needed if cm=kern 6568007Ssaidi@eecs.umich.edu 6578007Ssaidi@eecs.umich.edu 6588007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 6598007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 6608007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 6618007Ssaidi@eecs.umich.edu 6628007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 6638007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 6648007Ssaidi@eecs.umich.edu 6658007Ssaidi@eecs.umich.eduTRAP_OPCDEC_10_: 6668007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 6678007Ssaidi@eecs.umich.edu addq r14, 4, r14 // inc pc 6688007Ssaidi@eecs.umich.edu 6698007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 6708007Ssaidi@eecs.umich.edu bis r31, osf_a0_opdec, r16 // set a0 6718007Ssaidi@eecs.umich.edu 6728007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 6738007Ssaidi@eecs.umich.edu mfpr r13, pt_entif // get entry point 6748007Ssaidi@eecs.umich.edu 6758007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 6768007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 6778007Ssaidi@eecs.umich.edu 6788007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 6798007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 6808007Ssaidi@eecs.umich.edu 6818007Ssaidi@eecs.umich.edu bis r12, r31, r11 // update ps 6828007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 6838007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei, E1 6848007Ssaidi@eecs.umich.edu 6858007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp, E1 6868007Ssaidi@eecs.umich.edu 6878007Ssaidi@eecs.umich.edu hw_rei_spe // done, E1 6888007Ssaidi@eecs.umich.edu 6898007Ssaidi@eecs.umich.edu 6908013Sbinkertn@umich.edu// 6918013Sbinkertn@umich.edu// ARITH - Arithmetic Exception Trap Entry Point 6928013Sbinkertn@umich.edu// 6938007Ssaidi@eecs.umich.edu// ARITH - offset 0500 6948007Ssaidi@eecs.umich.edu// Entry: 6958007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on arithmetic excpetion. 6968007Ssaidi@eecs.umich.edu// 6978007Ssaidi@eecs.umich.edu// Function: 6988007Ssaidi@eecs.umich.edu// Build stack frame 6998007Ssaidi@eecs.umich.edu// a0 <- exc_sum 7008007Ssaidi@eecs.umich.edu// a1 <- exc_mask 7018007Ssaidi@eecs.umich.edu// a2 <- unpred 7028007Ssaidi@eecs.umich.edu// vector via entArith 7038007Ssaidi@eecs.umich.edu// 7048013Sbinkertn@umich.edu// 7058007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_ARITH_ENTRY) 7068007Ssaidi@eecs.umich.eduTrap_Arith: 7078007Ssaidi@eecs.umich.edu DEBUGSTORE(0x4b) 7088007Ssaidi@eecs.umich.edu and r11, osfps_m_mode, r12 // get mode bit 7098007Ssaidi@eecs.umich.edu mfpr r31, ev5__va // unlock mbox 7108007Ssaidi@eecs.umich.edu 7118007Ssaidi@eecs.umich.edu bis r11, r31, r25 // save ps 7128007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 7138007Ssaidi@eecs.umich.edu 7148007Ssaidi@eecs.umich.edu nop 7158007Ssaidi@eecs.umich.edu blbs r14, pal_pal_bug_check // arith trap from PAL 7168007Ssaidi@eecs.umich.edu 7178007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 7188007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 7198007Ssaidi@eecs.umich.edu beq r12, TRAP_ARITH_10_ // if zero we are in kern now 7208007Ssaidi@eecs.umich.edu 7218007Ssaidi@eecs.umich.edu bis r31, r31, r25 // set the new ps 7228007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 7238007Ssaidi@eecs.umich.edu 7248007Ssaidi@eecs.umich.edu nop 7258007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp // get kern stack 7268007Ssaidi@eecs.umich.edu 7278007Ssaidi@eecs.umich.eduTRAP_ARITH_10_: lda sp, 0-osfsf_c_size(sp) // allocate stack space 7288007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 7298007Ssaidi@eecs.umich.edu 7308007Ssaidi@eecs.umich.edu nop // Pad current mode write and stq 7318007Ssaidi@eecs.umich.edu mfpr r13, ev5__exc_sum // get the exc_sum 7328007Ssaidi@eecs.umich.edu 7338007Ssaidi@eecs.umich.edu mfpr r12, pt_entarith 7348007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 7358007Ssaidi@eecs.umich.edu 7368007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) 7378007Ssaidi@eecs.umich.edu mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle 7388007Ssaidi@eecs.umich.edu 7398007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save ps 7408007Ssaidi@eecs.umich.edu bis r25, r31, r11 // set new ps 7418007Ssaidi@eecs.umich.edu 7428007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 7438013Sbinkertn@umich.edu srl r13, exc_sum_v_swc, r16 // shift data to correct position 7448007Ssaidi@eecs.umich.edu 7458007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) 7468007Ssaidi@eecs.umich.edu// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow 7478007Ssaidi@eecs.umich.edu mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask 7488007Ssaidi@eecs.umich.edu 7498007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) 7508007Ssaidi@eecs.umich.edu mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1 7518007Ssaidi@eecs.umich.edu 7528007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kern gp - E1 7538007Ssaidi@eecs.umich.edu hw_rei_spe // done - E1 7548007Ssaidi@eecs.umich.edu 7558007Ssaidi@eecs.umich.edu 7568013Sbinkertn@umich.edu// 7578013Sbinkertn@umich.edu// FEN - Illegal Floating Point Operation Trap Entry Point 7588013Sbinkertn@umich.edu// 7598007Ssaidi@eecs.umich.edu// FEN - offset 0580 7608007Ssaidi@eecs.umich.edu// Entry: 7618007Ssaidi@eecs.umich.edu// Vectored into via hardware trap on illegal FP op. 7628007Ssaidi@eecs.umich.edu// 7638007Ssaidi@eecs.umich.edu// Function: 7648007Ssaidi@eecs.umich.edu// Build stack frame 7658007Ssaidi@eecs.umich.edu// a0 <- code 7668007Ssaidi@eecs.umich.edu// a1 <- unpred 7678007Ssaidi@eecs.umich.edu// a2 <- unpred 7688007Ssaidi@eecs.umich.edu// vector via entIF 7698007Ssaidi@eecs.umich.edu// 7708013Sbinkertn@umich.edu// 7718007Ssaidi@eecs.umich.edu 7728007Ssaidi@eecs.umich.edu HDW_VECTOR(PAL_FEN_ENTRY) 7738007Ssaidi@eecs.umich.eduTrap_Fen: 7748007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 7758007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 7768007Ssaidi@eecs.umich.edu 7778007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 7788007Ssaidi@eecs.umich.edu blbs r14, pal_pal_bug_check // check opcdec in palmode 7798007Ssaidi@eecs.umich.edu 7808007Ssaidi@eecs.umich.edu mfpr r13, ev5__icsr 7818007Ssaidi@eecs.umich.edu nop 7828007Ssaidi@eecs.umich.edu 7838007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS 7848007Ssaidi@eecs.umich.edu bge r25, TRAP_FEN_10_ // no stack swap needed if cm=kern 7858007Ssaidi@eecs.umich.edu 7868007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 7878007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 7888007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 7898007Ssaidi@eecs.umich.edu 7908007Ssaidi@eecs.umich.edu bis r31, r31, r12 // Set new PS 7918007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 7928007Ssaidi@eecs.umich.edu 7938007Ssaidi@eecs.umich.eduTRAP_FEN_10_: 7948007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 7958007Ssaidi@eecs.umich.edu srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0 7968007Ssaidi@eecs.umich.edu 7978007Ssaidi@eecs.umich.edu 7988007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 7998007Ssaidi@eecs.umich.edu mfpr r13, pt_entif // get entry point 8008007Ssaidi@eecs.umich.edu 8018007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 8028007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 8038007Ssaidi@eecs.umich.edu 8048007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 8058007Ssaidi@eecs.umich.edu bis r12, r31, r11 // set new ps 8068007Ssaidi@eecs.umich.edu 8078007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 8088007Ssaidi@eecs.umich.edu blbs r25,fen_to_opcdec // If FP is enabled, this is really OPCDEC. 8098007Ssaidi@eecs.umich.edu 8108007Ssaidi@eecs.umich.edu bis r31, osf_a0_fen, r16 // set a0 8118007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 8128007Ssaidi@eecs.umich.edu 8138007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 8148007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei -E1 8158007Ssaidi@eecs.umich.edu 8168007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp -E1 8178007Ssaidi@eecs.umich.edu 8188007Ssaidi@eecs.umich.edu hw_rei_spe // done -E1 8198007Ssaidi@eecs.umich.edu 8208007Ssaidi@eecs.umich.edu// FEN trap was taken, but the fault is really opcdec. 8218007Ssaidi@eecs.umich.edu ALIGN_BRANCH 8228007Ssaidi@eecs.umich.edufen_to_opcdec: 8238007Ssaidi@eecs.umich.edu addq r14, 4, r14 // save PC+4 8248007Ssaidi@eecs.umich.edu bis r31, osf_a0_opdec, r16 // set a0 8258007Ssaidi@eecs.umich.edu 8268007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 8278007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 8288007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 8298007Ssaidi@eecs.umich.edu 8308007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 8318007Ssaidi@eecs.umich.edu hw_rei_spe // done 8328007Ssaidi@eecs.umich.edu 8338007Ssaidi@eecs.umich.edu 8348007Ssaidi@eecs.umich.edu 8358013Sbinkertn@umich.edu////////////////////////////////////////////////////////////////////////////// 8368013Sbinkertn@umich.edu// Misc handlers - Start area for misc code. 8378013Sbinkertn@umich.edu////////////////////////////////////////////////////////////////////////////// 8388013Sbinkertn@umich.edu 8398013Sbinkertn@umich.edu// 8408013Sbinkertn@umich.edu// dfault_trap_cont 8418007Ssaidi@eecs.umich.edu// A dfault trap has been taken. The sp has been updated if necessary. 8428007Ssaidi@eecs.umich.edu// Push a stack frame a vector via entMM. 8438007Ssaidi@eecs.umich.edu// 8448007Ssaidi@eecs.umich.edu// Current state: 8458007Ssaidi@eecs.umich.edu// r12 - new PS 8468007Ssaidi@eecs.umich.edu// r13 - MMstat 8478007Ssaidi@eecs.umich.edu// VA - locked 8488007Ssaidi@eecs.umich.edu// 8498013Sbinkertn@umich.edu// 8508007Ssaidi@eecs.umich.edu ALIGN_BLOCK 8518007Ssaidi@eecs.umich.edudfault_trap_cont: 8528007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 8538007Ssaidi@eecs.umich.edu mfpr r25, ev5__va // Fetch VA/unlock 8548007Ssaidi@eecs.umich.edu 8558007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 8568007Ssaidi@eecs.umich.edu and r13, 1, r18 // Clean r/w bit for a2 8578007Ssaidi@eecs.umich.edu 8588007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 8598007Ssaidi@eecs.umich.edu bis r25, r31, r16 // a0 <- va 8608007Ssaidi@eecs.umich.edu 8618007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 8628007Ssaidi@eecs.umich.edu srl r13, 1, r17 // shift fault bits to right position 8638007Ssaidi@eecs.umich.edu 8648007Ssaidi@eecs.umich.edu stq r11, osfsf_ps(sp) // save old ps 8658007Ssaidi@eecs.umich.edu bis r12, r31, r11 // update ps 8668007Ssaidi@eecs.umich.edu 8678007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 8688007Ssaidi@eecs.umich.edu mfpr r25, pt_entmm // get entry point 8698007Ssaidi@eecs.umich.edu 8708007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 8718007Ssaidi@eecs.umich.edu cmovlbs r17, 1, r17 // a2. acv overrides fox. 8728007Ssaidi@eecs.umich.edu 8738007Ssaidi@eecs.umich.edu mtpr r25, exc_addr // load exc_addr with entMM 8748007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 8758007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 8768007Ssaidi@eecs.umich.edu 8778007Ssaidi@eecs.umich.edu hw_rei_spe // done 8788007Ssaidi@eecs.umich.edu 8798013Sbinkertn@umich.edu// 8808007Ssaidi@eecs.umich.edu//unalign_trap_cont 8818007Ssaidi@eecs.umich.edu// An unalign trap has been taken. Just need to finish up a few things. 8828007Ssaidi@eecs.umich.edu// 8838007Ssaidi@eecs.umich.edu// Current state: 8848007Ssaidi@eecs.umich.edu// r25 - entUna 8858007Ssaidi@eecs.umich.edu// r13 - shifted MMstat 8868007Ssaidi@eecs.umich.edu// 8878013Sbinkertn@umich.edu// 8888007Ssaidi@eecs.umich.edu ALIGN_BLOCK 8898007Ssaidi@eecs.umich.eduunalign_trap_cont: 8908007Ssaidi@eecs.umich.edu mtpr r25, exc_addr // load exc_addr with entUna 8918007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 8928007Ssaidi@eecs.umich.edu 8938007Ssaidi@eecs.umich.edu 8948007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 8958007Ssaidi@eecs.umich.edu and r13, mm_stat_m_ra, r18 // Clean Ra for a2 8968007Ssaidi@eecs.umich.edu 8978007Ssaidi@eecs.umich.edu hw_rei_spe // done 8988007Ssaidi@eecs.umich.edu 8998007Ssaidi@eecs.umich.edu 9008007Ssaidi@eecs.umich.edu 9018013Sbinkertn@umich.edu// 9028007Ssaidi@eecs.umich.edu// dfault_in_pal 9038007Ssaidi@eecs.umich.edu// Dfault trap was taken, exc_addr points to a PAL PC. 9048007Ssaidi@eecs.umich.edu// r9 - mmstat<opcode> right justified 9058007Ssaidi@eecs.umich.edu// r8 - exception address 9068007Ssaidi@eecs.umich.edu// 9078007Ssaidi@eecs.umich.edu// These are the cases: 9088007Ssaidi@eecs.umich.edu// opcode was STQ -- from a stack builder, KSP not valid halt 9098007Ssaidi@eecs.umich.edu// r14 - original exc_addr 9108007Ssaidi@eecs.umich.edu// r11 - original PS 9118007Ssaidi@eecs.umich.edu// opcode was STL_C -- rti or retsys clear lock_flag by stack write, 9128007Ssaidi@eecs.umich.edu// KSP not valid halt 9138007Ssaidi@eecs.umich.edu// r11 - original PS 9148007Ssaidi@eecs.umich.edu// r14 - original exc_addr 9158007Ssaidi@eecs.umich.edu// opcode was LDQ -- retsys or rti stack read, KSP not valid halt 9168007Ssaidi@eecs.umich.edu// r11 - original PS 9178007Ssaidi@eecs.umich.edu// r14 - original exc_addr 9188007Ssaidi@eecs.umich.edu// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables 9198007Ssaidi@eecs.umich.edu// r10 - original exc_addr 9208007Ssaidi@eecs.umich.edu// r11 - original PS 9218007Ssaidi@eecs.umich.edu// 9228007Ssaidi@eecs.umich.edu// 9238013Sbinkertn@umich.edu// 9248007Ssaidi@eecs.umich.edu ALIGN_BLOCK 9258007Ssaidi@eecs.umich.edudfault_in_pal: 9268007Ssaidi@eecs.umich.edu DEBUGSTORE(0x50) 9278007Ssaidi@eecs.umich.edu bic r8, 3, r8 // Clean PC 9288007Ssaidi@eecs.umich.edu mfpr r9, pal_base 9298007Ssaidi@eecs.umich.edu 9308007Ssaidi@eecs.umich.edu mfpr r31, va // unlock VA 9318013Sbinkertn@umich.edu 9328013Sbinkertn@umich.edu // if not real_mm, should never get here from miss flows 9338007Ssaidi@eecs.umich.edu 9348007Ssaidi@eecs.umich.edu subq r9, r8, r8 // pal_base - offset 9358007Ssaidi@eecs.umich.edu 9368007Ssaidi@eecs.umich.edu lda r9, pal_itb_ldq-pal_base(r8) 9378007Ssaidi@eecs.umich.edu nop 9388007Ssaidi@eecs.umich.edu 9398007Ssaidi@eecs.umich.edu beq r9, dfault_do_bugcheck 9408007Ssaidi@eecs.umich.edu lda r9, pal_dtb_ldq-pal_base(r8) 9418007Ssaidi@eecs.umich.edu 9428007Ssaidi@eecs.umich.edu beq r9, dfault_do_bugcheck 9438007Ssaidi@eecs.umich.edu 9448007Ssaidi@eecs.umich.edu// 9458007Ssaidi@eecs.umich.edu// KSP invalid halt case -- 9468007Ssaidi@eecs.umich.eduksp_inval_halt: 9478007Ssaidi@eecs.umich.edu DEBUGSTORE(76) 9488007Ssaidi@eecs.umich.edu bic r11, osfps_m_mode, r11 // set ps to kernel mode 9498007Ssaidi@eecs.umich.edu mtpr r0, pt0 9508007Ssaidi@eecs.umich.edu 9518007Ssaidi@eecs.umich.edu mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode 9528007Ssaidi@eecs.umich.edu mtpr r31, ips 9538007Ssaidi@eecs.umich.edu 9548007Ssaidi@eecs.umich.edu mtpr r14, exc_addr // Set PC to instruction that caused trouble 9558007Ssaidi@eecs.umich.edu bsr r0, pal_update_pcb // update the pcb 9568007Ssaidi@eecs.umich.edu 9578007Ssaidi@eecs.umich.edu lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt 9588007Ssaidi@eecs.umich.edu br r31, sys_enter_console // enter the console 9598007Ssaidi@eecs.umich.edu 9608007Ssaidi@eecs.umich.edu ALIGN_BRANCH 9618007Ssaidi@eecs.umich.edudfault_do_bugcheck: 9628007Ssaidi@eecs.umich.edu bis r10, r31, r14 // bugcheck expects exc_addr in r14 9638007Ssaidi@eecs.umich.edu br r31, pal_pal_bug_check 9648007Ssaidi@eecs.umich.edu 9658007Ssaidi@eecs.umich.edu 9668013Sbinkertn@umich.edu// 9678007Ssaidi@eecs.umich.edu// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31 9688007Ssaidi@eecs.umich.edu// On entry - 9698007Ssaidi@eecs.umich.edu// r14 - exc_addr 9708007Ssaidi@eecs.umich.edu// VA is locked 9718007Ssaidi@eecs.umich.edu// 9728013Sbinkertn@umich.edu// 9738013Sbinkertn@umich.edu ALIGN_BLOCK 9748007Ssaidi@eecs.umich.edudfault_fetch_ldr31_err: 9758007Ssaidi@eecs.umich.edu mtpr r11, ev5__dtb_cm 9768007Ssaidi@eecs.umich.edu mtpr r11, ev5__ps // Make sure ps hasn't changed 9778007Ssaidi@eecs.umich.edu 9788007Ssaidi@eecs.umich.edu mfpr r31, va // unlock the mbox 9798007Ssaidi@eecs.umich.edu addq r14, 4, r14 // inc the pc to skip the fetch 9808007Ssaidi@eecs.umich.edu 9818007Ssaidi@eecs.umich.edu mtpr r14, exc_addr // give ibox new PC 9828007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad exc_addr write 9838007Ssaidi@eecs.umich.edu 9848007Ssaidi@eecs.umich.edu hw_rei 9858007Ssaidi@eecs.umich.edu 9868007Ssaidi@eecs.umich.edu 9878007Ssaidi@eecs.umich.edu 9888007Ssaidi@eecs.umich.edu ALIGN_BLOCK 9898013Sbinkertn@umich.edu// 9908007Ssaidi@eecs.umich.edu// sys_from_kern 9918007Ssaidi@eecs.umich.edu// callsys from kernel mode - OS bugcheck machine check 9928007Ssaidi@eecs.umich.edu// 9938013Sbinkertn@umich.edu// 9948007Ssaidi@eecs.umich.edusys_from_kern: 9958007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // PC points to call_pal 9968007Ssaidi@eecs.umich.edu subq r14, 4, r14 9978007Ssaidi@eecs.umich.edu 9988007Ssaidi@eecs.umich.edu lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code 9998007Ssaidi@eecs.umich.edu br r31, pal_pal_mchk 10008007Ssaidi@eecs.umich.edu 10018007Ssaidi@eecs.umich.edu 10028013Sbinkertn@umich.edu// Continuation of long call_pal flows 10038013Sbinkertn@umich.edu// 10048007Ssaidi@eecs.umich.edu// wrent_tbl 10058007Ssaidi@eecs.umich.edu// Table to write *int in paltemps. 10068007Ssaidi@eecs.umich.edu// 4 instructions/entry 10078007Ssaidi@eecs.umich.edu// r16 has new value 10088007Ssaidi@eecs.umich.edu// 10098013Sbinkertn@umich.edu// 10108013Sbinkertn@umich.edu ALIGN_BLOCK 10118007Ssaidi@eecs.umich.eduwrent_tbl: 10128007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 10138007Ssaidi@eecs.umich.edu nop 10148007Ssaidi@eecs.umich.edu mtpr r16, pt_entint 10158007Ssaidi@eecs.umich.edu 10168007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 10178007Ssaidi@eecs.umich.edu hw_rei 10188007Ssaidi@eecs.umich.edu 10198007Ssaidi@eecs.umich.edu 10208007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 10218007Ssaidi@eecs.umich.edu nop 10228007Ssaidi@eecs.umich.edu mtpr r16, pt_entarith 10238007Ssaidi@eecs.umich.edu 10248007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 10258007Ssaidi@eecs.umich.edu hw_rei 10268007Ssaidi@eecs.umich.edu 10278007Ssaidi@eecs.umich.edu 10288007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 10298007Ssaidi@eecs.umich.edu nop 10308007Ssaidi@eecs.umich.edu mtpr r16, pt_entmm 10318007Ssaidi@eecs.umich.edu 10328007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 10338007Ssaidi@eecs.umich.edu hw_rei 10348007Ssaidi@eecs.umich.edu 10358007Ssaidi@eecs.umich.edu 10368007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 10378007Ssaidi@eecs.umich.edu nop 10388007Ssaidi@eecs.umich.edu mtpr r16, pt_entif 10398007Ssaidi@eecs.umich.edu 10408007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 10418007Ssaidi@eecs.umich.edu hw_rei 10428007Ssaidi@eecs.umich.edu 10438007Ssaidi@eecs.umich.edu 10448007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 10458007Ssaidi@eecs.umich.edu nop 10468007Ssaidi@eecs.umich.edu mtpr r16, pt_entuna 10478007Ssaidi@eecs.umich.edu 10488007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 10498007Ssaidi@eecs.umich.edu hw_rei 10508007Ssaidi@eecs.umich.edu 10518007Ssaidi@eecs.umich.edu 10528007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent, dest=1 10538007Ssaidi@eecs.umich.edu nop 10548007Ssaidi@eecs.umich.edu mtpr r16, pt_entsys 10558007Ssaidi@eecs.umich.edu 10568007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad for mt->mf paltemp rule 10578007Ssaidi@eecs.umich.edu hw_rei 10588007Ssaidi@eecs.umich.edu 10598007Ssaidi@eecs.umich.edu ALIGN_BLOCK 10608013Sbinkertn@umich.edu// 10618007Ssaidi@eecs.umich.edu// tbi_tbl 10628007Ssaidi@eecs.umich.edu// Table to do tbi instructions 10638007Ssaidi@eecs.umich.edu// 4 instructions per entry 10648013Sbinkertn@umich.edu// 10658007Ssaidi@eecs.umich.edutbi_tbl: 10668007Ssaidi@eecs.umich.edu // -2 tbia 10678007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 10688007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_ia // Flush DTB 10698007Ssaidi@eecs.umich.edu mtpr r31, ev5__itb_ia // Flush ITB 10708007Ssaidi@eecs.umich.edu 10718007Ssaidi@eecs.umich.edu hw_rei_stall 10728007Ssaidi@eecs.umich.edu 10738007Ssaidi@eecs.umich.edu nop // Pad table 10748007Ssaidi@eecs.umich.edu 10758007Ssaidi@eecs.umich.edu // -1 tbiap 10768007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 10778007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_iap // Flush DTB 10788007Ssaidi@eecs.umich.edu mtpr r31, ev5__itb_iap // Flush ITB 10798007Ssaidi@eecs.umich.edu 10808007Ssaidi@eecs.umich.edu hw_rei_stall 10818007Ssaidi@eecs.umich.edu 10828007Ssaidi@eecs.umich.edu nop // Pad table 10838007Ssaidi@eecs.umich.edu 10848007Ssaidi@eecs.umich.edu 10858007Ssaidi@eecs.umich.edu // 0 unused 10868007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 10878007Ssaidi@eecs.umich.edu hw_rei // Pad table 10888007Ssaidi@eecs.umich.edu nop 10898007Ssaidi@eecs.umich.edu nop 10908007Ssaidi@eecs.umich.edu nop 10918007Ssaidi@eecs.umich.edu 10928007Ssaidi@eecs.umich.edu 10938007Ssaidi@eecs.umich.edu // 1 tbisi 10948007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 10958007Ssaidi@eecs.umich.edu 10968007Ssaidi@eecs.umich.edu nop 10978007Ssaidi@eecs.umich.edu nop 10988007Ssaidi@eecs.umich.edu mtpr r17, ev5__itb_is // Flush ITB 10998007Ssaidi@eecs.umich.edu hw_rei_stall 11008007Ssaidi@eecs.umich.edu 11018007Ssaidi@eecs.umich.edu // 2 tbisd 11028007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 11038007Ssaidi@eecs.umich.edu mtpr r17, ev5__dtb_is // Flush DTB. 11048007Ssaidi@eecs.umich.edu nop 11058007Ssaidi@eecs.umich.edu 11068007Ssaidi@eecs.umich.edu nop 11078007Ssaidi@eecs.umich.edu hw_rei_stall 11088007Ssaidi@eecs.umich.edu 11098007Ssaidi@eecs.umich.edu 11108007Ssaidi@eecs.umich.edu // 3 tbis 11118007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi, dest=1 11128007Ssaidi@eecs.umich.edu mtpr r17, ev5__dtb_is // Flush DTB 11138007Ssaidi@eecs.umich.edu br r31, tbi_finish 11148007Ssaidi@eecs.umich.edu ALIGN_BRANCH 11158007Ssaidi@eecs.umich.edutbi_finish: 11168007Ssaidi@eecs.umich.edu mtpr r17, ev5__itb_is // Flush ITB 11178007Ssaidi@eecs.umich.edu hw_rei_stall 11188007Ssaidi@eecs.umich.edu 11198007Ssaidi@eecs.umich.edu 11208007Ssaidi@eecs.umich.edu 11218007Ssaidi@eecs.umich.edu ALIGN_BLOCK 11228013Sbinkertn@umich.edu// 11238007Ssaidi@eecs.umich.edu// bpt_bchk_common: 11248007Ssaidi@eecs.umich.edu// Finish up the bpt/bchk instructions 11258013Sbinkertn@umich.edu// 11268007Ssaidi@eecs.umich.edubpt_bchk_common: 11278007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 11288007Ssaidi@eecs.umich.edu mfpr r13, pt_entif // get entry point 11298007Ssaidi@eecs.umich.edu 11308007Ssaidi@eecs.umich.edu stq r12, osfsf_ps(sp) // save old ps 11318007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 11328007Ssaidi@eecs.umich.edu 11338007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 11348007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 11358007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 11368007Ssaidi@eecs.umich.edu 11378007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 11388007Ssaidi@eecs.umich.edu 11398007Ssaidi@eecs.umich.edu 11408007Ssaidi@eecs.umich.edu hw_rei_spe // done 11418007Ssaidi@eecs.umich.edu 11428007Ssaidi@eecs.umich.edu 11438007Ssaidi@eecs.umich.edu ALIGN_BLOCK 11448013Sbinkertn@umich.edu// 11458007Ssaidi@eecs.umich.edu// rti_to_user 11468007Ssaidi@eecs.umich.edu// Finish up the rti instruction 11478013Sbinkertn@umich.edu// 11488007Ssaidi@eecs.umich.edurti_to_user: 11498007Ssaidi@eecs.umich.edu mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 11508007Ssaidi@eecs.umich.edu mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 11518007Ssaidi@eecs.umich.edu 11528007Ssaidi@eecs.umich.edu mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles 11538007Ssaidi@eecs.umich.edu mtpr r25, pt_ksp // save off incase RTI to user 11548007Ssaidi@eecs.umich.edu 11558007Ssaidi@eecs.umich.edu mfpr r30, pt_usp 11568007Ssaidi@eecs.umich.edu hw_rei_spe // and back 11578007Ssaidi@eecs.umich.edu 11588007Ssaidi@eecs.umich.edu 11598007Ssaidi@eecs.umich.edu ALIGN_BLOCK 11608013Sbinkertn@umich.edu// 11618007Ssaidi@eecs.umich.edu// rti_to_kern 11628007Ssaidi@eecs.umich.edu// Finish up the rti instruction 11638013Sbinkertn@umich.edu// 11648007Ssaidi@eecs.umich.edurti_to_kern: 11658007Ssaidi@eecs.umich.edu and r12, osfps_m_ipl, r11 // clean ps 11668007Ssaidi@eecs.umich.edu mfpr r12, pt_intmask // get int mask 11678007Ssaidi@eecs.umich.edu 11688007Ssaidi@eecs.umich.edu extbl r12, r11, r12 // get mask for this ipl 11698007Ssaidi@eecs.umich.edu mtpr r25, pt_ksp // save off incase RTI to user 11708007Ssaidi@eecs.umich.edu 11718007Ssaidi@eecs.umich.edu mtpr r12, ev5__ipl // set the new ipl. 11728007Ssaidi@eecs.umich.edu or r25, r31, sp // sp 11738007Ssaidi@eecs.umich.edu 11748007Ssaidi@eecs.umich.edu// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals 11758007Ssaidi@eecs.umich.edu hw_rei 11768007Ssaidi@eecs.umich.edu 11778007Ssaidi@eecs.umich.edu ALIGN_BLOCK 11788013Sbinkertn@umich.edu// 11798007Ssaidi@eecs.umich.edu// swpctx_cont 11808007Ssaidi@eecs.umich.edu// Finish up the swpctx instruction 11818013Sbinkertn@umich.edu// 11828007Ssaidi@eecs.umich.edu 11838007Ssaidi@eecs.umich.eduswpctx_cont: 11848007Ssaidi@eecs.umich.edu 11858007Ssaidi@eecs.umich.edu bic r25, r24, r25 // clean icsr<FPE,PMP> 11868007Ssaidi@eecs.umich.edu sll r12, icsr_v_fpe, r12 // shift new fen to pos 11878007Ssaidi@eecs.umich.edu 11888013Sbinkertn@umich.edu ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr 11898007Ssaidi@eecs.umich.edu srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 11908007Ssaidi@eecs.umich.edu 11918007Ssaidi@eecs.umich.edu or r25, r12, r25 // icsr with new fen 11928007Ssaidi@eecs.umich.edu srl r23, 32, r24 // move asn to low asn pos 11938007Ssaidi@eecs.umich.edu 11948007Ssaidi@eecs.umich.edu and r22, 1, r22 11958007Ssaidi@eecs.umich.edu sll r24, itb_asn_v_asn, r12 11968007Ssaidi@eecs.umich.edu 11978007Ssaidi@eecs.umich.edu sll r22, icsr_v_pmp, r22 11988007Ssaidi@eecs.umich.edu nop 11998007Ssaidi@eecs.umich.edu 12008007Ssaidi@eecs.umich.edu or r25, r22, r25 // icsr with new pme 12018007Ssaidi@eecs.umich.edu 12028007Ssaidi@eecs.umich.edu sll r24, dtb_asn_v_asn, r24 12038007Ssaidi@eecs.umich.edu 12048007Ssaidi@eecs.umich.edu subl r23, r13, r13 // gen new cc offset 12058007Ssaidi@eecs.umich.edu mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4 12068007Ssaidi@eecs.umich.edu 12078007Ssaidi@eecs.umich.edu mtpr r24, dtb_asn // Load up new ASN 12088007Ssaidi@eecs.umich.edu mtpr r25, icsr // write the icsr 12098007Ssaidi@eecs.umich.edu 12108007Ssaidi@eecs.umich.edu sll r14, page_offset_size_bits, r14 // Move PTBR into internal position. 12118013Sbinkertn@umich.edu ldq_p r25, osfpcb_q_usp(r16) // get new usp 12128007Ssaidi@eecs.umich.edu 12138007Ssaidi@eecs.umich.edu insll r13, 4, r13 // >> 32 12148013Sbinkertn@umich.edu// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow 12158007Ssaidi@eecs.umich.edu mtpr r14, pt_ptbr // load the new ptbr 12168007Ssaidi@eecs.umich.edu 12178007Ssaidi@eecs.umich.edu mtpr r13, cc // set new offset 12188013Sbinkertn@umich.edu ldq_p r30, osfpcb_q_ksp(r16) // get new ksp 12198013Sbinkertn@umich.edu 12208013Sbinkertn@umich.edu// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow 12218007Ssaidi@eecs.umich.edu mtpr r25, pt_usp // save usp 12228007Ssaidi@eecs.umich.edu 12238007Ssaidi@eecs.umich.eduno_pm_change_10_: hw_rei_stall // back we go 12248007Ssaidi@eecs.umich.edu 12258007Ssaidi@eecs.umich.edu ALIGN_BLOCK 12268013Sbinkertn@umich.edu// 12278007Ssaidi@eecs.umich.edu// swppal_cont - finish up the swppal call_pal 12288013Sbinkertn@umich.edu// 12298007Ssaidi@eecs.umich.edu 12308007Ssaidi@eecs.umich.eduswppal_cont: 12318007Ssaidi@eecs.umich.edu mfpr r2, pt_misc // get misc bits 12328007Ssaidi@eecs.umich.edu sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit 12338007Ssaidi@eecs.umich.edu or r2, r0, r2 // set the bit 12348007Ssaidi@eecs.umich.edu mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel) 12358007Ssaidi@eecs.umich.edu mtpr r2, pt_misc // update the chip 12368007Ssaidi@eecs.umich.edu 12378007Ssaidi@eecs.umich.edu or r3, r31, r4 12388007Ssaidi@eecs.umich.edu mfpr r3, pt_impure // pass pointer to the impure area in r3 12398007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r3 // adjust impure pointer for ipr read 12408007Ssaidi@eecs.umich.edu//orig restore_reg1 bc_ctl, r1, r3, ipr=1 // pass cns_bc_ctl in r1 12418007Ssaidi@eecs.umich.edu//orig restore_reg1 bc_config, r2, r3, ipr=1 // pass cns_bc_config in r2 12428007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r3 // restore impure pointer 12438007Ssaidi@eecs.umich.edu lda r3, CNS_Q_IPR(r3) 12448007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r1,CNS_Q_BC_CTL,r3); 12458007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r1,CNS_Q_BC_CFG,r3); 12468007Ssaidi@eecs.umich.edu lda r3, -CNS_Q_IPR(r3) 12478007Ssaidi@eecs.umich.edu 12488007Ssaidi@eecs.umich.edu or r31, r31, r0 // set status to success 12498007Ssaidi@eecs.umich.edu// pvc_violate 1007 12508007Ssaidi@eecs.umich.edu jmp r31, (r4) // and call our friend, it's her problem now 12518007Ssaidi@eecs.umich.edu 12528007Ssaidi@eecs.umich.edu 12538007Ssaidi@eecs.umich.eduswppal_fail: 12548007Ssaidi@eecs.umich.edu addq r0, 1, r0 // set unknown pal or not loaded 12558007Ssaidi@eecs.umich.edu hw_rei // and return 12568007Ssaidi@eecs.umich.edu 12578007Ssaidi@eecs.umich.edu 12588007Ssaidi@eecs.umich.edu// .sbttl "Memory management" 12598007Ssaidi@eecs.umich.edu 12608007Ssaidi@eecs.umich.edu ALIGN_BLOCK 12618013Sbinkertn@umich.edu// 12628007Ssaidi@eecs.umich.edu//foe_ipte_handler 12638007Ssaidi@eecs.umich.edu// IFOE detected on level 3 pte, sort out FOE vs ACV 12648007Ssaidi@eecs.umich.edu// 12658007Ssaidi@eecs.umich.edu// on entry: 12668007Ssaidi@eecs.umich.edu// with 12678007Ssaidi@eecs.umich.edu// R8 = pte 12688007Ssaidi@eecs.umich.edu// R10 = pc 12698007Ssaidi@eecs.umich.edu// 12708007Ssaidi@eecs.umich.edu// Function 12718007Ssaidi@eecs.umich.edu// Determine TNV vs ACV vs FOE. Build stack and dispatch 12728007Ssaidi@eecs.umich.edu// Will not be here if TNV. 12738013Sbinkertn@umich.edu// 12748007Ssaidi@eecs.umich.edu 12758007Ssaidi@eecs.umich.edufoe_ipte_handler: 12768007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 12778007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 12788007Ssaidi@eecs.umich.edu 12798007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 12808007Ssaidi@eecs.umich.edu bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern 12818007Ssaidi@eecs.umich.edu 12828007Ssaidi@eecs.umich.edu 12838007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 12848007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 12858007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 12868007Ssaidi@eecs.umich.edu 12878007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 12888007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 12898007Ssaidi@eecs.umich.edu 12908007Ssaidi@eecs.umich.edu srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern 12918007Ssaidi@eecs.umich.edu nop 12928007Ssaidi@eecs.umich.edu 12938007Ssaidi@eecs.umich.edufoe_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> 12948007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 12958007Ssaidi@eecs.umich.edu 12968007Ssaidi@eecs.umich.edu or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack 12978007Ssaidi@eecs.umich.edu mfpr r13, pt_entmm // get entry point 12988007Ssaidi@eecs.umich.edu 12998007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // a0 13008007Ssaidi@eecs.umich.edu or r14, r31, r16 // pass pc/va as a0 13018007Ssaidi@eecs.umich.edu 13028007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 13038007Ssaidi@eecs.umich.edu nop 13048007Ssaidi@eecs.umich.edu 13058007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 13068007Ssaidi@eecs.umich.edu lda r17, mmcsr_c_acv(r31) // assume ACV 13078007Ssaidi@eecs.umich.edu 13088007Ssaidi@eecs.umich.edu stq r16, osfsf_pc(sp) // save pc 13098007Ssaidi@eecs.umich.edu cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE 13108007Ssaidi@eecs.umich.edu 13118007Ssaidi@eecs.umich.edu stq r12, osfsf_ps(sp) // save ps 13128007Ssaidi@eecs.umich.edu subq r31, 1, r18 // pass flag of istream as a2 13138007Ssaidi@eecs.umich.edu 13148007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) 13158007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // set vector address 13168007Ssaidi@eecs.umich.edu 13178007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // load kgp 13188007Ssaidi@eecs.umich.edu hw_rei_spe // out to exec 13198007Ssaidi@eecs.umich.edu 13208007Ssaidi@eecs.umich.edu ALIGN_BLOCK 13218013Sbinkertn@umich.edu// 13228007Ssaidi@eecs.umich.edu//invalid_ipte_handler 13238007Ssaidi@eecs.umich.edu// TNV detected on level 3 pte, sort out TNV vs ACV 13248007Ssaidi@eecs.umich.edu// 13258007Ssaidi@eecs.umich.edu// on entry: 13268007Ssaidi@eecs.umich.edu// with 13278007Ssaidi@eecs.umich.edu// R8 = pte 13288007Ssaidi@eecs.umich.edu// R10 = pc 13298007Ssaidi@eecs.umich.edu// 13308007Ssaidi@eecs.umich.edu// Function 13318007Ssaidi@eecs.umich.edu// Determine TNV vs ACV. Build stack and dispatch. 13328013Sbinkertn@umich.edu// 13338007Ssaidi@eecs.umich.edu 13348007Ssaidi@eecs.umich.eduinvalid_ipte_handler: 13358007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 13368007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 13378007Ssaidi@eecs.umich.edu 13388007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 13398007Ssaidi@eecs.umich.edu bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern 13408007Ssaidi@eecs.umich.edu 13418007Ssaidi@eecs.umich.edu 13428007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 13438007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 13448007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 13458007Ssaidi@eecs.umich.edu 13468007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 13478007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 13488007Ssaidi@eecs.umich.edu 13498007Ssaidi@eecs.umich.edu srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern 13508007Ssaidi@eecs.umich.edu nop 13518007Ssaidi@eecs.umich.edu 13528007Ssaidi@eecs.umich.eduinvalid_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> 13538007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 13548007Ssaidi@eecs.umich.edu 13558007Ssaidi@eecs.umich.edu or r10, r31, r14 // Save pc/va in case TBmiss on stack 13568007Ssaidi@eecs.umich.edu mfpr r13, pt_entmm // get entry point 13578007Ssaidi@eecs.umich.edu 13588007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // a0 13598007Ssaidi@eecs.umich.edu or r14, r31, r16 // pass pc/va as a0 13608007Ssaidi@eecs.umich.edu 13618007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 13628007Ssaidi@eecs.umich.edu nop 13638007Ssaidi@eecs.umich.edu 13648007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 13658007Ssaidi@eecs.umich.edu and r25, 1, r17 // Isolate kre 13668007Ssaidi@eecs.umich.edu 13678007Ssaidi@eecs.umich.edu stq r16, osfsf_pc(sp) // save pc 13688007Ssaidi@eecs.umich.edu xor r17, 1, r17 // map to acv/tnv as a1 13698007Ssaidi@eecs.umich.edu 13708007Ssaidi@eecs.umich.edu stq r12, osfsf_ps(sp) // save ps 13718007Ssaidi@eecs.umich.edu subq r31, 1, r18 // pass flag of istream as a2 13728007Ssaidi@eecs.umich.edu 13738007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) 13748007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // set vector address 13758007Ssaidi@eecs.umich.edu 13768007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // load kgp 13778007Ssaidi@eecs.umich.edu hw_rei_spe // out to exec 13788007Ssaidi@eecs.umich.edu 13798007Ssaidi@eecs.umich.edu 13808007Ssaidi@eecs.umich.edu 13818007Ssaidi@eecs.umich.edu 13828007Ssaidi@eecs.umich.edu ALIGN_BLOCK 13838013Sbinkertn@umich.edu// 13848007Ssaidi@eecs.umich.edu//invalid_dpte_handler 13858007Ssaidi@eecs.umich.edu// INVALID detected on level 3 pte, sort out TNV vs ACV 13868007Ssaidi@eecs.umich.edu// 13878007Ssaidi@eecs.umich.edu// on entry: 13888007Ssaidi@eecs.umich.edu// with 13898007Ssaidi@eecs.umich.edu// R10 = va 13908007Ssaidi@eecs.umich.edu// R8 = pte 13918007Ssaidi@eecs.umich.edu// R9 = mm_stat 13928007Ssaidi@eecs.umich.edu// PT6 = pc 13938007Ssaidi@eecs.umich.edu// 13948007Ssaidi@eecs.umich.edu// Function 13958007Ssaidi@eecs.umich.edu// Determine TNV vs ACV. Build stack and dispatch 13968013Sbinkertn@umich.edu// 13978007Ssaidi@eecs.umich.edu 13988007Ssaidi@eecs.umich.edu 13998007Ssaidi@eecs.umich.eduinvalid_dpte_handler: 14008007Ssaidi@eecs.umich.edu mfpr r12, pt6 14018007Ssaidi@eecs.umich.edu blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode 14028007Ssaidi@eecs.umich.edu 14038007Ssaidi@eecs.umich.edu bis r12, r31, r14 // save PC in case of tbmiss or fault 14048007Ssaidi@eecs.umich.edu srl r9, mm_stat_v_opcode, r25 // shift opc to <0> 14058007Ssaidi@eecs.umich.edu 14068007Ssaidi@eecs.umich.edu mtpr r11, pt0 // Save PS for stack write 14078007Ssaidi@eecs.umich.edu and r25, mm_stat_m_opcode, r25 // isolate opcode 14088007Ssaidi@eecs.umich.edu 14098007Ssaidi@eecs.umich.edu cmpeq r25, evx_opc_sync, r25 // is it FETCH/FETCH_M? 14108007Ssaidi@eecs.umich.edu blbs r25, nmiss_fetch_ldr31_err // yes 14118007Ssaidi@eecs.umich.edu 14128007Ssaidi@eecs.umich.edu //dismiss exception if load to r31/f31 14138007Ssaidi@eecs.umich.edu blbs r9, invalid_dpte_no_dismiss // mm_stat<0> set on store or fetchm 14148007Ssaidi@eecs.umich.edu 14158007Ssaidi@eecs.umich.edu // not a store or fetch, must be a load 14168007Ssaidi@eecs.umich.edu srl r9, mm_stat_v_ra, r25 // Shift rnum to low bits 14178007Ssaidi@eecs.umich.edu 14188007Ssaidi@eecs.umich.edu and r25, 0x1F, r25 // isolate rnum 14198007Ssaidi@eecs.umich.edu nop 14208007Ssaidi@eecs.umich.edu 14218007Ssaidi@eecs.umich.edu cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31? 14228007Ssaidi@eecs.umich.edu bne r25, nmiss_fetch_ldr31_err // Yes, dismiss the fault 14238007Ssaidi@eecs.umich.edu 14248007Ssaidi@eecs.umich.eduinvalid_dpte_no_dismiss: 14258007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 14268007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 14278007Ssaidi@eecs.umich.edu 14288007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 14298007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 14308007Ssaidi@eecs.umich.edu bge r25, invalid_dpte_no_dismiss_10_ // no stack swap needed if cm=kern 14318007Ssaidi@eecs.umich.edu 14328007Ssaidi@eecs.umich.edu srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern 14338007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 14348007Ssaidi@eecs.umich.edu 14358007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 14368007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 14378007Ssaidi@eecs.umich.edu 14388007Ssaidi@eecs.umich.eduinvalid_dpte_no_dismiss_10_: srl r8, osfpte_v_kre, r12 // get kre to <0> 14398007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 14408007Ssaidi@eecs.umich.edu 14418007Ssaidi@eecs.umich.edu or r10, r31, r25 // Save va in case TBmiss on stack 14428007Ssaidi@eecs.umich.edu and r9, 1, r13 // save r/w flag 14438007Ssaidi@eecs.umich.edu 14448007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // a0 14458007Ssaidi@eecs.umich.edu or r25, r31, r16 // pass va as a0 14468007Ssaidi@eecs.umich.edu 14478007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 14488007Ssaidi@eecs.umich.edu or r31, mmcsr_c_acv, r17 // assume acv 14498007Ssaidi@eecs.umich.edu 14508007Ssaidi@eecs.umich.edu srl r12, osfpte_v_kwe-osfpte_v_kre, r25 // get write enable to <0> 14518007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) 14528007Ssaidi@eecs.umich.edu 14538007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 14548007Ssaidi@eecs.umich.edu cmovlbs r13, r25, r12 // if write access move acv based on write enable 14558007Ssaidi@eecs.umich.edu 14568007Ssaidi@eecs.umich.edu or r13, r31, r18 // pass flag of dstream access and read vs write 14578007Ssaidi@eecs.umich.edu mfpr r25, pt0 // get ps 14588007Ssaidi@eecs.umich.edu 14598007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 14608007Ssaidi@eecs.umich.edu mfpr r13, pt_entmm // get entry point 14618007Ssaidi@eecs.umich.edu 14628007Ssaidi@eecs.umich.edu stq r25, osfsf_ps(sp) // save ps 14638007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // set vector address 14648007Ssaidi@eecs.umich.edu 14658007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // load kgp 14668007Ssaidi@eecs.umich.edu cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv 14678007Ssaidi@eecs.umich.edu 14688007Ssaidi@eecs.umich.edu hw_rei_spe // out to exec 14698007Ssaidi@eecs.umich.edu 14708013Sbinkertn@umich.edu// 14718007Ssaidi@eecs.umich.edu// 14728007Ssaidi@eecs.umich.edu// We come here if we are erring on a dtb_miss, and the instr is a 14738007Ssaidi@eecs.umich.edu// fetch, fetch_m, of load to r31/f31. 14748007Ssaidi@eecs.umich.edu// The PC is incremented, and we return to the program. 14758007Ssaidi@eecs.umich.edu// essentially ignoring the instruction and error. 14768007Ssaidi@eecs.umich.edu// 14778013Sbinkertn@umich.edu// 14788007Ssaidi@eecs.umich.edu ALIGN_BLOCK 14798007Ssaidi@eecs.umich.edunmiss_fetch_ldr31_err: 14808007Ssaidi@eecs.umich.edu mfpr r12, pt6 14818007Ssaidi@eecs.umich.edu addq r12, 4, r12 // bump pc to pc+4 14828007Ssaidi@eecs.umich.edu 14838007Ssaidi@eecs.umich.edu mtpr r12, exc_addr // and set entry point 14848007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad exc_addr write 14858007Ssaidi@eecs.umich.edu 14868007Ssaidi@eecs.umich.edu hw_rei // 14878007Ssaidi@eecs.umich.edu 14888007Ssaidi@eecs.umich.edu ALIGN_BLOCK 14898013Sbinkertn@umich.edu// 14908007Ssaidi@eecs.umich.edu// double_pte_inv 14918007Ssaidi@eecs.umich.edu// We had a single tbmiss which turned into a double tbmiss which found 14928007Ssaidi@eecs.umich.edu// an invalid PTE. Return to single miss with a fake pte, and the invalid 14938007Ssaidi@eecs.umich.edu// single miss flow will report the error. 14948007Ssaidi@eecs.umich.edu// 14958007Ssaidi@eecs.umich.edu// on entry: 14968007Ssaidi@eecs.umich.edu// r21 PTE 14978007Ssaidi@eecs.umich.edu// r22 available 14988007Ssaidi@eecs.umich.edu// VA IPR locked with original fault VA 14998007Ssaidi@eecs.umich.edu// pt4 saved r21 15008007Ssaidi@eecs.umich.edu// pt5 saved r22 15018007Ssaidi@eecs.umich.edu// pt6 original exc_addr 15028007Ssaidi@eecs.umich.edu// 15038007Ssaidi@eecs.umich.edu// on return to tbmiss flow: 15048007Ssaidi@eecs.umich.edu// r8 fake PTE 15058007Ssaidi@eecs.umich.edu// 15068007Ssaidi@eecs.umich.edu// 15078013Sbinkertn@umich.edu// 15088007Ssaidi@eecs.umich.edudouble_pte_inv: 15098007Ssaidi@eecs.umich.edu srl r21, osfpte_v_kre, r21 // get the kre bit to <0> 15108007Ssaidi@eecs.umich.edu mfpr r22, exc_addr // get the pc 15118007Ssaidi@eecs.umich.edu 15128007Ssaidi@eecs.umich.edu lda r22, 4(r22) // inc the pc 15138007Ssaidi@eecs.umich.edu lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set 15148007Ssaidi@eecs.umich.edu 15158007Ssaidi@eecs.umich.edu cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0 15168007Ssaidi@eecs.umich.edu mtpr r22, exc_addr // set for rei 15178007Ssaidi@eecs.umich.edu 15188007Ssaidi@eecs.umich.edu mfpr r21, pt4 // restore regs 15198007Ssaidi@eecs.umich.edu mfpr r22, pt5 // restore regs 15208007Ssaidi@eecs.umich.edu 15218007Ssaidi@eecs.umich.edu hw_rei // back to tb miss 15228007Ssaidi@eecs.umich.edu 15238007Ssaidi@eecs.umich.edu ALIGN_BLOCK 15248013Sbinkertn@umich.edu// 15258007Ssaidi@eecs.umich.edu//tnv_in_pal 15268007Ssaidi@eecs.umich.edu// The only places in pal that ld or store are the 15278007Ssaidi@eecs.umich.edu// stack builders, rti or retsys. Any of these mean we 15288007Ssaidi@eecs.umich.edu// need to take a ksp not valid halt. 15298007Ssaidi@eecs.umich.edu// 15308013Sbinkertn@umich.edu// 15318007Ssaidi@eecs.umich.edutnv_in_pal: 15328007Ssaidi@eecs.umich.edu 15338007Ssaidi@eecs.umich.edu 15348007Ssaidi@eecs.umich.edu br r31, ksp_inval_halt 15358007Ssaidi@eecs.umich.edu 15368007Ssaidi@eecs.umich.edu 15378007Ssaidi@eecs.umich.edu// .sbttl "Icache flush routines" 15388007Ssaidi@eecs.umich.edu 15398007Ssaidi@eecs.umich.edu ALIGN_BLOCK 15408013Sbinkertn@umich.edu// 15418007Ssaidi@eecs.umich.edu// Common Icache flush routine. 15428007Ssaidi@eecs.umich.edu// 15438007Ssaidi@eecs.umich.edu// 15448013Sbinkertn@umich.edu// 15458007Ssaidi@eecs.umich.edupal_ic_flush: 15468007Ssaidi@eecs.umich.edu nop 15478007Ssaidi@eecs.umich.edu mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 15488007Ssaidi@eecs.umich.edu nop 15498007Ssaidi@eecs.umich.edu nop 15508007Ssaidi@eecs.umich.edu 15518007Ssaidi@eecs.umich.edu// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) 15528007Ssaidi@eecs.umich.edu nop 15538007Ssaidi@eecs.umich.edu nop 15548007Ssaidi@eecs.umich.edu nop 15558007Ssaidi@eecs.umich.edu nop 15568007Ssaidi@eecs.umich.edu 15578007Ssaidi@eecs.umich.edu nop 15588007Ssaidi@eecs.umich.edu nop 15598007Ssaidi@eecs.umich.edu nop 15608007Ssaidi@eecs.umich.edu nop 15618007Ssaidi@eecs.umich.edu 15628007Ssaidi@eecs.umich.edu nop 15638007Ssaidi@eecs.umich.edu nop // 10 15648007Ssaidi@eecs.umich.edu 15658007Ssaidi@eecs.umich.edu nop 15668007Ssaidi@eecs.umich.edu nop 15678007Ssaidi@eecs.umich.edu nop 15688007Ssaidi@eecs.umich.edu nop 15698007Ssaidi@eecs.umich.edu 15708007Ssaidi@eecs.umich.edu nop 15718007Ssaidi@eecs.umich.edu nop 15728007Ssaidi@eecs.umich.edu nop 15738007Ssaidi@eecs.umich.edu nop 15748007Ssaidi@eecs.umich.edu 15758007Ssaidi@eecs.umich.edu nop 15768007Ssaidi@eecs.umich.edu nop // 20 15778007Ssaidi@eecs.umich.edu 15788007Ssaidi@eecs.umich.edu nop 15798007Ssaidi@eecs.umich.edu nop 15808007Ssaidi@eecs.umich.edu nop 15818007Ssaidi@eecs.umich.edu nop 15828007Ssaidi@eecs.umich.edu 15838007Ssaidi@eecs.umich.edu nop 15848007Ssaidi@eecs.umich.edu nop 15858007Ssaidi@eecs.umich.edu nop 15868007Ssaidi@eecs.umich.edu nop 15878007Ssaidi@eecs.umich.edu 15888007Ssaidi@eecs.umich.edu nop 15898007Ssaidi@eecs.umich.edu nop // 30 15908007Ssaidi@eecs.umich.edu nop 15918007Ssaidi@eecs.umich.edu nop 15928007Ssaidi@eecs.umich.edu nop 15938007Ssaidi@eecs.umich.edu nop 15948007Ssaidi@eecs.umich.edu 15958007Ssaidi@eecs.umich.edu nop 15968007Ssaidi@eecs.umich.edu nop 15978007Ssaidi@eecs.umich.edu nop 15988007Ssaidi@eecs.umich.edu nop 15998007Ssaidi@eecs.umich.edu 16008007Ssaidi@eecs.umich.edu nop 16018007Ssaidi@eecs.umich.edu nop // 40 16028007Ssaidi@eecs.umich.edu 16038007Ssaidi@eecs.umich.edu nop 16048007Ssaidi@eecs.umich.edu nop 16058007Ssaidi@eecs.umich.edu 16068007Ssaidi@eecs.umich.eduone_cycle_and_hw_rei: 16078007Ssaidi@eecs.umich.edu nop 16088007Ssaidi@eecs.umich.edu nop 16098007Ssaidi@eecs.umich.edu 16108007Ssaidi@eecs.umich.edu hw_rei_stall 16118007Ssaidi@eecs.umich.edu 16128007Ssaidi@eecs.umich.edu ALIGN_BLOCK 16138013Sbinkertn@umich.edu// 16148007Ssaidi@eecs.umich.edu//osfpal_calpal_opcdec 16158007Ssaidi@eecs.umich.edu// Here for all opcdec CALL_PALs 16168007Ssaidi@eecs.umich.edu// 16178007Ssaidi@eecs.umich.edu// Build stack frame 16188007Ssaidi@eecs.umich.edu// a0 <- code 16198007Ssaidi@eecs.umich.edu// a1 <- unpred 16208007Ssaidi@eecs.umich.edu// a2 <- unpred 16218007Ssaidi@eecs.umich.edu// vector via entIF 16228007Ssaidi@eecs.umich.edu// 16238013Sbinkertn@umich.edu// 16248007Ssaidi@eecs.umich.edu 16258007Ssaidi@eecs.umich.eduosfpal_calpal_opcdec: 16268007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 16278007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 16288007Ssaidi@eecs.umich.edu 16298007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 16308007Ssaidi@eecs.umich.edu nop 16318007Ssaidi@eecs.umich.edu 16328007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 16338007Ssaidi@eecs.umich.edu bge r25, osfpal_calpal_opcdec_10_ // no stack swap needed if cm=kern 16348007Ssaidi@eecs.umich.edu 16358007Ssaidi@eecs.umich.edu 16368007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 16378007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 16388007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 16398007Ssaidi@eecs.umich.edu 16408007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 16418007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 16428007Ssaidi@eecs.umich.edu 16438007Ssaidi@eecs.umich.eduosfpal_calpal_opcdec_10_: 16448007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 16458007Ssaidi@eecs.umich.edu nop 16468007Ssaidi@eecs.umich.edu 16478007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 16488007Ssaidi@eecs.umich.edu bis r31, osf_a0_opdec, r16 // set a0 16498007Ssaidi@eecs.umich.edu 16508007Ssaidi@eecs.umich.edu stq r18, osfsf_a2(sp) // a2 16518007Ssaidi@eecs.umich.edu mfpr r13, pt_entif // get entry point 16528007Ssaidi@eecs.umich.edu 16538007Ssaidi@eecs.umich.edu stq r12, osfsf_ps(sp) // save old ps 16548007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 16558007Ssaidi@eecs.umich.edu 16568007Ssaidi@eecs.umich.edu stq r14, osfsf_pc(sp) // save pc 16578007Ssaidi@eecs.umich.edu nop 16588007Ssaidi@eecs.umich.edu 16598007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save gp 16608007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // load exc_addr with entIF 16618007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 16628007Ssaidi@eecs.umich.edu 16638007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kgp 16648007Ssaidi@eecs.umich.edu 16658007Ssaidi@eecs.umich.edu 16668007Ssaidi@eecs.umich.edu hw_rei_spe // done 16678007Ssaidi@eecs.umich.edu 16688007Ssaidi@eecs.umich.edu 16698007Ssaidi@eecs.umich.edu 16708007Ssaidi@eecs.umich.edu 16718007Ssaidi@eecs.umich.edu 16728013Sbinkertn@umich.edu// 16738007Ssaidi@eecs.umich.edu//pal_update_pcb 16748007Ssaidi@eecs.umich.edu// Update the PCB with the current SP, AST, and CC info 16758007Ssaidi@eecs.umich.edu// 16768007Ssaidi@eecs.umich.edu// r0 - return linkage 16778013Sbinkertn@umich.edu// 16788007Ssaidi@eecs.umich.edu ALIGN_BLOCK 16798007Ssaidi@eecs.umich.edu 16808007Ssaidi@eecs.umich.edupal_update_pcb: 16818007Ssaidi@eecs.umich.edu mfpr r12, pt_pcbb // get pcbb 16828007Ssaidi@eecs.umich.edu and r11, osfps_m_mode, r25 // get mode 16838007Ssaidi@eecs.umich.edu beq r25, pal_update_pcb_10_ // in kern? no need to update user sp 16848007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 16858013Sbinkertn@umich.edu stq_p r30, osfpcb_q_usp(r12) // store usp 16868007Ssaidi@eecs.umich.edu br r31, pal_update_pcb_20_ // join common 16878013Sbinkertn@umich.edupal_update_pcb_10_: stq_p r30, osfpcb_q_ksp(r12) // store ksp 16888007Ssaidi@eecs.umich.edupal_update_pcb_20_: rpcc r13 // get cyccounter 16898007Ssaidi@eecs.umich.edu srl r13, 32, r14 // move offset 16908007Ssaidi@eecs.umich.edu addl r13, r14, r14 // merge for new time 16918013Sbinkertn@umich.edu stl_p r14, osfpcb_l_cc(r12) // save time 16928007Ssaidi@eecs.umich.edu 16938007Ssaidi@eecs.umich.edu//orig pvc_jsr updpcb, bsr=1, dest=1 16948007Ssaidi@eecs.umich.edu ret r31, (r0) 16958007Ssaidi@eecs.umich.edu 16968007Ssaidi@eecs.umich.edu 16978013Sbinkertn@umich.edu// 16988013Sbinkertn@umich.edu// pal_save_state 16998007Ssaidi@eecs.umich.edu// 17008007Ssaidi@eecs.umich.edu// Function 17018007Ssaidi@eecs.umich.edu// All chip state saved, all PT's, SR's FR's, IPR's 17028007Ssaidi@eecs.umich.edu// 17038007Ssaidi@eecs.umich.edu// 17048007Ssaidi@eecs.umich.edu// Regs' on entry... 17058007Ssaidi@eecs.umich.edu// 17068007Ssaidi@eecs.umich.edu// R0 = halt code 17078007Ssaidi@eecs.umich.edu// pt0 = r0 17088007Ssaidi@eecs.umich.edu// R1 = pointer to impure 17098007Ssaidi@eecs.umich.edu// pt4 = r1 17108007Ssaidi@eecs.umich.edu// R3 = return addr 17118007Ssaidi@eecs.umich.edu// pt5 = r3 17128007Ssaidi@eecs.umich.edu// 17138007Ssaidi@eecs.umich.edu// register usage: 17148007Ssaidi@eecs.umich.edu// r0 = halt_code 17158007Ssaidi@eecs.umich.edu// r1 = addr of impure area 17168007Ssaidi@eecs.umich.edu// r3 = return_address 17178007Ssaidi@eecs.umich.edu// r4 = scratch 17188007Ssaidi@eecs.umich.edu// 17198013Sbinkertn@umich.edu// 17208007Ssaidi@eecs.umich.edu 17218007Ssaidi@eecs.umich.edu ALIGN_BLOCK 17228007Ssaidi@eecs.umich.edu .globl pal_save_state 17238007Ssaidi@eecs.umich.edupal_save_state: 17248007Ssaidi@eecs.umich.edu// 17258007Ssaidi@eecs.umich.edu// 17268007Ssaidi@eecs.umich.edu// start of implementation independent save routine 17278007Ssaidi@eecs.umich.edu// 17288007Ssaidi@eecs.umich.edu// the impure area is larger than the addressibility of hw_ld and hw_st 17298007Ssaidi@eecs.umich.edu// therefore, we need to play some games: The impure area 17308007Ssaidi@eecs.umich.edu// is informally divided into the "machine independent" part and the 17318007Ssaidi@eecs.umich.edu// "machine dependent" part. The state that will be saved in the 17328007Ssaidi@eecs.umich.edu// "machine independent" part are gpr's, fpr's, hlt, flag, mchkflag (use (un)fix_impure_gpr macros). 17338007Ssaidi@eecs.umich.edu// All others will be in the "machine dependent" part (use (un)fix_impure_ipr macros). 17348007Ssaidi@eecs.umich.edu// The impure pointer will need to be adjusted by a different offset for each. The store/restore_reg 17358007Ssaidi@eecs.umich.edu// macros will automagically adjust the offset correctly. 17368007Ssaidi@eecs.umich.edu// 17378007Ssaidi@eecs.umich.edu 17388007Ssaidi@eecs.umich.edu// The distributed code is commented out and followed by corresponding SRC code. 17398007Ssaidi@eecs.umich.edu// Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0) 17408007Ssaidi@eecs.umich.edu 17418007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 // adjust impure area pointer for stores to "gpr" part of impure area 17428007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // Point to center of CPU segment 17438007Ssaidi@eecs.umich.edu//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag 17448007Ssaidi@eecs.umich.edu SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag 17458007Ssaidi@eecs.umich.edu//orig store_reg1 hlt, r0, r1, ipr=1 17468007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code 17478007Ssaidi@eecs.umich.edu 17488007Ssaidi@eecs.umich.edu mfpr r0, pt0 // get r0 back //orig 17498007Ssaidi@eecs.umich.edu//orig store_reg1 0, r0, r1 // save r0 17508007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0 17518007Ssaidi@eecs.umich.edu 17528007Ssaidi@eecs.umich.edu mfpr r0, pt4 // get r1 back //orig 17538007Ssaidi@eecs.umich.edu//orig store_reg1 1, r0, r1 // save r1 17548007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1 17558007Ssaidi@eecs.umich.edu 17568007Ssaidi@eecs.umich.edu//orig store_reg 2 // save r2 17578007Ssaidi@eecs.umich.edu SAVE_GPR(r2,CNS_Q_GPR+0x10,r1) // Save r2 17588007Ssaidi@eecs.umich.edu 17598007Ssaidi@eecs.umich.edu mfpr r0, pt5 // get r3 back //orig 17608007Ssaidi@eecs.umich.edu//orig store_reg1 3, r0, r1 // save r3 17618007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3 17628007Ssaidi@eecs.umich.edu 17638007Ssaidi@eecs.umich.edu // reason code has been saved 17648007Ssaidi@eecs.umich.edu // r0 has been saved 17658007Ssaidi@eecs.umich.edu // r1 has been saved 17668007Ssaidi@eecs.umich.edu // r2 has been saved 17678007Ssaidi@eecs.umich.edu // r3 has been saved 17688007Ssaidi@eecs.umich.edu // pt0, pt4, pt5 have been lost 17698007Ssaidi@eecs.umich.edu 17708007Ssaidi@eecs.umich.edu // 17718007Ssaidi@eecs.umich.edu // Get out of shadow mode 17728007Ssaidi@eecs.umich.edu // 17738007Ssaidi@eecs.umich.edu 17748013Sbinkertn@umich.edu mfpr r2, icsr // Get icsr 17758007Ssaidi@eecs.umich.edu ldah r0, (1<<(icsr_v_sde-16))(r31) 17768013Sbinkertn@umich.edu bic r2, r0, r0 // ICSR with SDE clear 17778013Sbinkertn@umich.edu mtpr r0, icsr // Turn off SDE 17788013Sbinkertn@umich.edu 17798013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 1 17808013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 2 17818013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 3 17828013Sbinkertn@umich.edu nop 17838007Ssaidi@eecs.umich.edu 17848007Ssaidi@eecs.umich.edu 17858007Ssaidi@eecs.umich.edu // save integer regs R4-r31 17868007Ssaidi@eecs.umich.edu SAVE_GPR(r4,CNS_Q_GPR+0x20,r1) 17878007Ssaidi@eecs.umich.edu SAVE_GPR(r5,CNS_Q_GPR+0x28,r1) 17888007Ssaidi@eecs.umich.edu SAVE_GPR(r6,CNS_Q_GPR+0x30,r1) 17898007Ssaidi@eecs.umich.edu SAVE_GPR(r7,CNS_Q_GPR+0x38,r1) 17908007Ssaidi@eecs.umich.edu SAVE_GPR(r8,CNS_Q_GPR+0x40,r1) 17918007Ssaidi@eecs.umich.edu SAVE_GPR(r9,CNS_Q_GPR+0x48,r1) 17928007Ssaidi@eecs.umich.edu SAVE_GPR(r10,CNS_Q_GPR+0x50,r1) 17938007Ssaidi@eecs.umich.edu SAVE_GPR(r11,CNS_Q_GPR+0x58,r1) 17948007Ssaidi@eecs.umich.edu SAVE_GPR(r12,CNS_Q_GPR+0x60,r1) 17958007Ssaidi@eecs.umich.edu SAVE_GPR(r13,CNS_Q_GPR+0x68,r1) 17968007Ssaidi@eecs.umich.edu SAVE_GPR(r14,CNS_Q_GPR+0x70,r1) 17978007Ssaidi@eecs.umich.edu SAVE_GPR(r15,CNS_Q_GPR+0x78,r1) 17988007Ssaidi@eecs.umich.edu SAVE_GPR(r16,CNS_Q_GPR+0x80,r1) 17998007Ssaidi@eecs.umich.edu SAVE_GPR(r17,CNS_Q_GPR+0x88,r1) 18008007Ssaidi@eecs.umich.edu SAVE_GPR(r18,CNS_Q_GPR+0x90,r1) 18018007Ssaidi@eecs.umich.edu SAVE_GPR(r19,CNS_Q_GPR+0x98,r1) 18028007Ssaidi@eecs.umich.edu SAVE_GPR(r20,CNS_Q_GPR+0xA0,r1) 18038007Ssaidi@eecs.umich.edu SAVE_GPR(r21,CNS_Q_GPR+0xA8,r1) 18048007Ssaidi@eecs.umich.edu SAVE_GPR(r22,CNS_Q_GPR+0xB0,r1) 18058007Ssaidi@eecs.umich.edu SAVE_GPR(r23,CNS_Q_GPR+0xB8,r1) 18068007Ssaidi@eecs.umich.edu SAVE_GPR(r24,CNS_Q_GPR+0xC0,r1) 18078007Ssaidi@eecs.umich.edu SAVE_GPR(r25,CNS_Q_GPR+0xC8,r1) 18088007Ssaidi@eecs.umich.edu SAVE_GPR(r26,CNS_Q_GPR+0xD0,r1) 18098007Ssaidi@eecs.umich.edu SAVE_GPR(r27,CNS_Q_GPR+0xD8,r1) 18108007Ssaidi@eecs.umich.edu SAVE_GPR(r28,CNS_Q_GPR+0xE0,r1) 18118007Ssaidi@eecs.umich.edu SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1) 18128007Ssaidi@eecs.umich.edu SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1) 18138007Ssaidi@eecs.umich.edu SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1) 18148007Ssaidi@eecs.umich.edu 18158007Ssaidi@eecs.umich.edu // save all paltemp regs except pt0 18168007Ssaidi@eecs.umich.edu 18178007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores 18188007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores 18198007Ssaidi@eecs.umich.edu 18208007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Restore the impure base address. 18218007Ssaidi@eecs.umich.edu lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area. 18228007Ssaidi@eecs.umich.edu SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle 18238007Ssaidi@eecs.umich.edu SAVE_IPR(pt1,CNS_Q_PT+0x08,r1) 18248007Ssaidi@eecs.umich.edu SAVE_IPR(pt2,CNS_Q_PT+0x10,r1) 18258007Ssaidi@eecs.umich.edu SAVE_IPR(pt3,CNS_Q_PT+0x18,r1) 18268007Ssaidi@eecs.umich.edu SAVE_IPR(pt4,CNS_Q_PT+0x20,r1) 18278007Ssaidi@eecs.umich.edu SAVE_IPR(pt5,CNS_Q_PT+0x28,r1) 18288007Ssaidi@eecs.umich.edu SAVE_IPR(pt6,CNS_Q_PT+0x30,r1) 18298007Ssaidi@eecs.umich.edu SAVE_IPR(pt7,CNS_Q_PT+0x38,r1) 18308007Ssaidi@eecs.umich.edu SAVE_IPR(pt8,CNS_Q_PT+0x40,r1) 18318007Ssaidi@eecs.umich.edu SAVE_IPR(pt9,CNS_Q_PT+0x48,r1) 18328007Ssaidi@eecs.umich.edu SAVE_IPR(pt10,CNS_Q_PT+0x50,r1) 18338007Ssaidi@eecs.umich.edu SAVE_IPR(pt11,CNS_Q_PT+0x58,r1) 18348007Ssaidi@eecs.umich.edu SAVE_IPR(pt12,CNS_Q_PT+0x60,r1) 18358007Ssaidi@eecs.umich.edu SAVE_IPR(pt13,CNS_Q_PT+0x68,r1) 18368007Ssaidi@eecs.umich.edu SAVE_IPR(pt14,CNS_Q_PT+0x70,r1) 18378007Ssaidi@eecs.umich.edu SAVE_IPR(pt15,CNS_Q_PT+0x78,r1) 18388007Ssaidi@eecs.umich.edu SAVE_IPR(pt16,CNS_Q_PT+0x80,r1) 18398007Ssaidi@eecs.umich.edu SAVE_IPR(pt17,CNS_Q_PT+0x88,r1) 18408007Ssaidi@eecs.umich.edu SAVE_IPR(pt18,CNS_Q_PT+0x90,r1) 18418007Ssaidi@eecs.umich.edu SAVE_IPR(pt19,CNS_Q_PT+0x98,r1) 18428007Ssaidi@eecs.umich.edu SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1) 18438007Ssaidi@eecs.umich.edu SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1) 18448007Ssaidi@eecs.umich.edu SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1) 18458007Ssaidi@eecs.umich.edu SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1) 18468007Ssaidi@eecs.umich.edu 18478007Ssaidi@eecs.umich.edu // Restore shadow mode 18488013Sbinkertn@umich.edu mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) 18498013Sbinkertn@umich.edu mfpr r31, pt0 18508013Sbinkertn@umich.edu mtpr r2, icsr // Restore original ICSR 18518013Sbinkertn@umich.edu 18528013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 1 18538013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 2 18548013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 3 18558013Sbinkertn@umich.edu nop 18568007Ssaidi@eecs.umich.edu 18578007Ssaidi@eecs.umich.edu // save all integer shadow regs 18588007Ssaidi@eecs.umich.edu SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code 18598007Ssaidi@eecs.umich.edu SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) 18608007Ssaidi@eecs.umich.edu SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) 18618007Ssaidi@eecs.umich.edu SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) 18628007Ssaidi@eecs.umich.edu SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) 18638007Ssaidi@eecs.umich.edu SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) 18648007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) 18658007Ssaidi@eecs.umich.edu SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) 18668007Ssaidi@eecs.umich.edu 18678007Ssaidi@eecs.umich.edu SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) 18688007Ssaidi@eecs.umich.edu SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1) 18698007Ssaidi@eecs.umich.edu SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1) 18708007Ssaidi@eecs.umich.edu SAVE_IPR(va,CNS_Q_VA,r1) 18718007Ssaidi@eecs.umich.edu SAVE_IPR(icsr,CNS_Q_ICSR,r1) 18728007Ssaidi@eecs.umich.edu SAVE_IPR(ipl,CNS_Q_IPL,r1) 18738007Ssaidi@eecs.umich.edu SAVE_IPR(ips,CNS_Q_IPS,r1) 18748007Ssaidi@eecs.umich.edu SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) 18758007Ssaidi@eecs.umich.edu SAVE_IPR(aster,CNS_Q_ASTER,r1) 18768007Ssaidi@eecs.umich.edu SAVE_IPR(astrr,CNS_Q_ASTRR,r1) 18778007Ssaidi@eecs.umich.edu SAVE_IPR(sirr,CNS_Q_SIRR,r1) 18788007Ssaidi@eecs.umich.edu SAVE_IPR(isr,CNS_Q_ISR,r1) 18798007Ssaidi@eecs.umich.edu SAVE_IPR(iVptBr,CNS_Q_IVPTBR,r1) 18808007Ssaidi@eecs.umich.edu SAVE_IPR(mcsr,CNS_Q_MCSR,r1) 18818007Ssaidi@eecs.umich.edu SAVE_IPR(dcMode,CNS_Q_DC_MODE,r1) 18828007Ssaidi@eecs.umich.edu 18838007Ssaidi@eecs.umich.edu//orig pvc_violate 379 // mf maf_mode after a store ok (pvc doesn't distinguish ld from st) 18848007Ssaidi@eecs.umich.edu//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for 18858007Ssaidi@eecs.umich.edu//orig // PVC violation applies only to 18868007Ssaidi@eecs.umich.edupvc$osf35$379: // loads. HW_ST ok here, so ignore 18878007Ssaidi@eecs.umich.edu SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2 18888007Ssaidi@eecs.umich.edu 18898007Ssaidi@eecs.umich.edu 18908007Ssaidi@eecs.umich.edu //the following iprs are informational only -- will not be restored 18918007Ssaidi@eecs.umich.edu 18928007Ssaidi@eecs.umich.edu SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1) 18938007Ssaidi@eecs.umich.edu SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1) 18948007Ssaidi@eecs.umich.edu SAVE_IPR(intId,CNS_Q_INT_ID,r1) 18958007Ssaidi@eecs.umich.edu SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1) 18968007Ssaidi@eecs.umich.edu SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1) 18978007Ssaidi@eecs.umich.edu ldah r14, 0xFFF0(zero) 18988007Ssaidi@eecs.umich.edu zap r14, 0xE0, r14 // Get base address of CBOX IPRs 18998007Ssaidi@eecs.umich.edu NOP // Pad mfpr dcPerr out of shadow of 19008007Ssaidi@eecs.umich.edu NOP // last store 19018007Ssaidi@eecs.umich.edu NOP 19028007Ssaidi@eecs.umich.edu SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1) 19038007Ssaidi@eecs.umich.edu 19048007Ssaidi@eecs.umich.edu // read cbox ipr state 19058007Ssaidi@eecs.umich.edu 19068007Ssaidi@eecs.umich.edu mb 19078007Ssaidi@eecs.umich.edu ldq_p r2, scCtl(r14) 19088007Ssaidi@eecs.umich.edu ldq_p r13, ldLock(r14) 19098007Ssaidi@eecs.umich.edu ldq_p r4, scAddr(r14) 19108007Ssaidi@eecs.umich.edu ldq_p r5, eiAddr(r14) 19118007Ssaidi@eecs.umich.edu ldq_p r6, bcTagAddr(r14) 19128007Ssaidi@eecs.umich.edu ldq_p r7, fillSyn(r14) 19138007Ssaidi@eecs.umich.edu bis r5, r4, zero // Make sure all loads complete before 19148007Ssaidi@eecs.umich.edu bis r7, r6, zero // reading registers that unlock them. 19158007Ssaidi@eecs.umich.edu ldq_p r8, scStat(r14) // Unlocks scAddr. 19168007Ssaidi@eecs.umich.edu ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn. 19178007Ssaidi@eecs.umich.edu ldq_p zero, eiStat(r14) // Make sure it is really unlocked. 19188007Ssaidi@eecs.umich.edu mb 19198013Sbinkertn@umich.edu 19208013Sbinkertn@umich.edu // save cbox ipr state 19218007Ssaidi@eecs.umich.edu SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1); 19228007Ssaidi@eecs.umich.edu SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1); 19238007Ssaidi@eecs.umich.edu SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1); 19248007Ssaidi@eecs.umich.edu SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1); 19258007Ssaidi@eecs.umich.edu SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1); 19268007Ssaidi@eecs.umich.edu SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1); 19278007Ssaidi@eecs.umich.edu SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1); 19288007Ssaidi@eecs.umich.edu SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1); 19298013Sbinkertn@umich.edu //bc_config? sl_rcv? 19308013Sbinkertn@umich.edu 19318013Sbinkertn@umich.edu// restore impure base 19328007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 19338007Ssaidi@eecs.umich.edu lda r1, -CNS_Q_IPR(r1) 19348007Ssaidi@eecs.umich.edu 19358013Sbinkertn@umich.edu// save all floating regs 19368013Sbinkertn@umich.edu mfpr r0, icsr // get icsr 19378013Sbinkertn@umich.edu or r31, 1, r2 // get a one 19388007Ssaidi@eecs.umich.edu sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position 19398013Sbinkertn@umich.edu or r2, r0, r0 // set FEN on 19408013Sbinkertn@umich.edu mtpr r0, icsr // write to icsr, enabling FEN 19418007Ssaidi@eecs.umich.edu 19428007Ssaidi@eecs.umich.edu// map the save area virtually 19438007Ssaidi@eecs.umich.edu mtpr r31, dtbIa // Clear all DTB entries 19448007Ssaidi@eecs.umich.edu srl r1, va_s_off, r0 // Clean off byte-within-page offset 19458007Ssaidi@eecs.umich.edu sll r0, pte_v_pfn, r0 // Shift to form PFN 19468007Ssaidi@eecs.umich.edu lda r0, pte_m_prot(r0) // Set all read/write enable bits 19478007Ssaidi@eecs.umich.edu mtpr r0, dtbPte // Load the PTE and set valid 19488007Ssaidi@eecs.umich.edu mtpr r1, dtbTag // Write the PTE and tag into the DTB 19498007Ssaidi@eecs.umich.edu 19508007Ssaidi@eecs.umich.edu 19518013Sbinkertn@umich.edu// map the next page too - in case the impure area crosses a page boundary 19528007Ssaidi@eecs.umich.edu lda r4, (1<<va_s_off)(r1) // Generate address for next page 19538007Ssaidi@eecs.umich.edu srl r4, va_s_off, r0 // Clean off byte-within-page offset 19548007Ssaidi@eecs.umich.edu sll r0, pte_v_pfn, r0 // Shift to form PFN 19558007Ssaidi@eecs.umich.edu lda r0, pte_m_prot(r0) // Set all read/write enable bits 19568007Ssaidi@eecs.umich.edu mtpr r0, dtbPte // Load the PTE and set valid 19578007Ssaidi@eecs.umich.edu mtpr r4, dtbTag // Write the PTE and tag into the DTB 19588007Ssaidi@eecs.umich.edu 19598013Sbinkertn@umich.edu sll r31, 0, r31 // stall cycle 1 19608013Sbinkertn@umich.edu sll r31, 0, r31 // stall cycle 2 19618013Sbinkertn@umich.edu sll r31, 0, r31 // stall cycle 3 19628013Sbinkertn@umich.edu nop 19638013Sbinkertn@umich.edu 19648013Sbinkertn@umich.edu// add offset for saving fpr regs 19658007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 19668007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // Point to center of CPU segment 19678007Ssaidi@eecs.umich.edu 19688007Ssaidi@eecs.umich.edu// now save the regs - F0-F31 19698007Ssaidi@eecs.umich.edu mf_fpcr f0 // original 19708007Ssaidi@eecs.umich.edu 19718007Ssaidi@eecs.umich.edu SAVE_FPR(f0,CNS_Q_FPR+0x00,r1) 19728007Ssaidi@eecs.umich.edu SAVE_FPR(f1,CNS_Q_FPR+0x08,r1) 19738007Ssaidi@eecs.umich.edu SAVE_FPR(f2,CNS_Q_FPR+0x10,r1) 19748007Ssaidi@eecs.umich.edu SAVE_FPR(f3,CNS_Q_FPR+0x18,r1) 19758007Ssaidi@eecs.umich.edu SAVE_FPR(f4,CNS_Q_FPR+0x20,r1) 19768007Ssaidi@eecs.umich.edu SAVE_FPR(f5,CNS_Q_FPR+0x28,r1) 19778007Ssaidi@eecs.umich.edu SAVE_FPR(f6,CNS_Q_FPR+0x30,r1) 19788007Ssaidi@eecs.umich.edu SAVE_FPR(f7,CNS_Q_FPR+0x38,r1) 19798007Ssaidi@eecs.umich.edu SAVE_FPR(f8,CNS_Q_FPR+0x40,r1) 19808007Ssaidi@eecs.umich.edu SAVE_FPR(f9,CNS_Q_FPR+0x48,r1) 19818007Ssaidi@eecs.umich.edu SAVE_FPR(f10,CNS_Q_FPR+0x50,r1) 19828007Ssaidi@eecs.umich.edu SAVE_FPR(f11,CNS_Q_FPR+0x58,r1) 19838007Ssaidi@eecs.umich.edu SAVE_FPR(f12,CNS_Q_FPR+0x60,r1) 19848007Ssaidi@eecs.umich.edu SAVE_FPR(f13,CNS_Q_FPR+0x68,r1) 19858007Ssaidi@eecs.umich.edu SAVE_FPR(f14,CNS_Q_FPR+0x70,r1) 19868007Ssaidi@eecs.umich.edu SAVE_FPR(f15,CNS_Q_FPR+0x78,r1) 19878007Ssaidi@eecs.umich.edu SAVE_FPR(f16,CNS_Q_FPR+0x80,r1) 19888007Ssaidi@eecs.umich.edu SAVE_FPR(f17,CNS_Q_FPR+0x88,r1) 19898007Ssaidi@eecs.umich.edu SAVE_FPR(f18,CNS_Q_FPR+0x90,r1) 19908007Ssaidi@eecs.umich.edu SAVE_FPR(f19,CNS_Q_FPR+0x98,r1) 19918007Ssaidi@eecs.umich.edu SAVE_FPR(f20,CNS_Q_FPR+0xA0,r1) 19928007Ssaidi@eecs.umich.edu SAVE_FPR(f21,CNS_Q_FPR+0xA8,r1) 19938007Ssaidi@eecs.umich.edu SAVE_FPR(f22,CNS_Q_FPR+0xB0,r1) 19948007Ssaidi@eecs.umich.edu SAVE_FPR(f23,CNS_Q_FPR+0xB8,r1) 19958007Ssaidi@eecs.umich.edu SAVE_FPR(f24,CNS_Q_FPR+0xC0,r1) 19968007Ssaidi@eecs.umich.edu SAVE_FPR(f25,CNS_Q_FPR+0xC8,r1) 19978007Ssaidi@eecs.umich.edu SAVE_FPR(f26,CNS_Q_FPR+0xD0,r1) 19988007Ssaidi@eecs.umich.edu SAVE_FPR(f27,CNS_Q_FPR+0xD8,r1) 19998007Ssaidi@eecs.umich.edu SAVE_FPR(f28,CNS_Q_FPR+0xE0,r1) 20008007Ssaidi@eecs.umich.edu SAVE_FPR(f29,CNS_Q_FPR+0xE8,r1) 20018007Ssaidi@eecs.umich.edu SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1) 20028007Ssaidi@eecs.umich.edu SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1) 20038007Ssaidi@eecs.umich.edu 20048013Sbinkertn@umich.edu//switch impure offset from gpr to ipr--- 20058007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 20068007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 20078007Ssaidi@eecs.umich.edu//orig store_reg1 fpcsr, f0, r1, fpcsr=1 20088007Ssaidi@eecs.umich.edu 20098013Sbinkertn@umich.edu SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach 20108007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Restore the impure base address 20118007Ssaidi@eecs.umich.edu 20128013Sbinkertn@umich.edu// and back to gpr --- 20138007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 20148007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 20158007Ssaidi@eecs.umich.edu 20168007Ssaidi@eecs.umich.edu//orig lda r0, cns_mchksize(r31) // get size of mchk area 20178007Ssaidi@eecs.umich.edu//orig store_reg1 mchkflag, r0, r1, ipr=1 20188007Ssaidi@eecs.umich.edu//orig mb 20198007Ssaidi@eecs.umich.edu 20208007Ssaidi@eecs.umich.edu lda r1, CNS_Q_IPR(r1) // Point to base of IPR area again 20218007Ssaidi@eecs.umich.edu // save this using the IPR base (it is closer) not the GRP base as they used...pb 20228007Ssaidi@eecs.umich.edu lda r0, MACHINE_CHECK_SIZE(r31) // get size of mchk area 20238007Ssaidi@eecs.umich.edu SAVE_SHADOW(r0,CNS_Q_MCHK,r1); 20248007Ssaidi@eecs.umich.edu mb 20258007Ssaidi@eecs.umich.edu 20268007Ssaidi@eecs.umich.edu//orig or r31, 1, r0 // get a one 20278007Ssaidi@eecs.umich.edu//orig store_reg1 flag, r0, r1, ipr=1 // set dump area flag 20288007Ssaidi@eecs.umich.edu//orig mb 20298007Ssaidi@eecs.umich.edu 20308007Ssaidi@eecs.umich.edu lda r1, -CNS_Q_IPR(r1) // back to the base 20318007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // Point to center of CPU segment 20328007Ssaidi@eecs.umich.edu or r31, 1, r0 // get a one 20338007Ssaidi@eecs.umich.edu SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag 20348007Ssaidi@eecs.umich.edu mb 20358007Ssaidi@eecs.umich.edu 20368013Sbinkertn@umich.edu // restore impure area base 20378007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 20388007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Point to center of CPU segment 20398007Ssaidi@eecs.umich.edu 20408013Sbinkertn@umich.edu mtpr r31, dtb_ia // clear the dtb 20418013Sbinkertn@umich.edu mtpr r31, itb_ia // clear the itb 20428007Ssaidi@eecs.umich.edu 20438007Ssaidi@eecs.umich.edu//orig pvc_jsr savsta, bsr=1, dest=1 20448007Ssaidi@eecs.umich.edu ret r31, (r3) // and back we go 20458013Sbinkertn@umich.edu 20468007Ssaidi@eecs.umich.edu 20478007Ssaidi@eecs.umich.edu 20488007Ssaidi@eecs.umich.edu// .sbttl "PAL_RESTORE_STATE" 20498013Sbinkertn@umich.edu// 20508007Ssaidi@eecs.umich.edu// 20518007Ssaidi@eecs.umich.edu// Pal_restore_state 20528007Ssaidi@eecs.umich.edu// 20538007Ssaidi@eecs.umich.edu// 20548007Ssaidi@eecs.umich.edu// register usage: 20558007Ssaidi@eecs.umich.edu// r1 = addr of impure area 20568007Ssaidi@eecs.umich.edu// r3 = return_address 20578007Ssaidi@eecs.umich.edu// all other regs are scratchable, as they are about to 20588007Ssaidi@eecs.umich.edu// be reloaded from ram. 20598007Ssaidi@eecs.umich.edu// 20608007Ssaidi@eecs.umich.edu// Function: 20618007Ssaidi@eecs.umich.edu// All chip state restored, all SRs, FRs, PTs, IPRs 20628007Ssaidi@eecs.umich.edu// *** except R1, R3, PT0, PT4, PT5 *** 20638007Ssaidi@eecs.umich.edu// 20648013Sbinkertn@umich.edu// 20658007Ssaidi@eecs.umich.edu ALIGN_BLOCK 20668007Ssaidi@eecs.umich.edupal_restore_state: 20678007Ssaidi@eecs.umich.edu 20688007Ssaidi@eecs.umich.edu//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so. 20698007Ssaidi@eecs.umich.edu 20708013Sbinkertn@umich.edu// map the console io area virtually 20718007Ssaidi@eecs.umich.edu mtpr r31, dtbIa // Clear all DTB entries 20728007Ssaidi@eecs.umich.edu srl r1, va_s_off, r0 // Clean off byte-within-page offset 20738007Ssaidi@eecs.umich.edu sll r0, pte_v_pfn, r0 // Shift to form PFN 20748007Ssaidi@eecs.umich.edu lda r0, pte_m_prot(r0) // Set all read/write enable bits 20758007Ssaidi@eecs.umich.edu mtpr r0, dtbPte // Load the PTE and set valid 20768007Ssaidi@eecs.umich.edu mtpr r1, dtbTag // Write the PTE and tag into the DTB 20778007Ssaidi@eecs.umich.edu 20788007Ssaidi@eecs.umich.edu 20798013Sbinkertn@umich.edu// map the next page too, in case impure area crosses page boundary 20808007Ssaidi@eecs.umich.edu lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page 20818007Ssaidi@eecs.umich.edu srl r4, va_s_off, r0 // Clean off byte-within-page offset 20828007Ssaidi@eecs.umich.edu sll r0, pte_v_pfn, r0 // Shift to form PFN 20838007Ssaidi@eecs.umich.edu lda r0, pte_m_prot(r0) // Set all read/write enable bits 20848007Ssaidi@eecs.umich.edu mtpr r0, dtbPte // Load the PTE and set valid 20858007Ssaidi@eecs.umich.edu mtpr r4, dtbTag // Write the PTE and tag into the DTB 20868007Ssaidi@eecs.umich.edu 20878013Sbinkertn@umich.edu// save all floating regs 20888007Ssaidi@eecs.umich.edu mfpr r0, icsr // Get current ICSR 20898007Ssaidi@eecs.umich.edu bis zero, 1, r2 // Get a '1' 20908007Ssaidi@eecs.umich.edu or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2 20918007Ssaidi@eecs.umich.edu sll r2, icsr_v_fpe, r2 // Shift bits into position 20928007Ssaidi@eecs.umich.edu bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE> 20938007Ssaidi@eecs.umich.edu mtpr r0, icsr // Update the chip 20948007Ssaidi@eecs.umich.edu 20958007Ssaidi@eecs.umich.edu mfpr r31, pt0 // FPE bubble cycle 1 //orig 20968007Ssaidi@eecs.umich.edu mfpr r31, pt0 // FPE bubble cycle 2 //orig 20978007Ssaidi@eecs.umich.edu mfpr r31, pt0 // FPE bubble cycle 3 //orig 20988007Ssaidi@eecs.umich.edu 20998007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 21008007Ssaidi@eecs.umich.edu//orig restore_reg1 fpcsr, f0, r1, fpcsr=1 21018007Ssaidi@eecs.umich.edu//orig mt_fpcr f0 21028007Ssaidi@eecs.umich.edu//orig 21038007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 21048007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access 21058007Ssaidi@eecs.umich.edu lda r1, 200(r1) // Point to base of IPR area again 21068007Ssaidi@eecs.umich.edu RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb 21078007Ssaidi@eecs.umich.edu mt_fpcr f0 // original 21088007Ssaidi@eecs.umich.edu 21098007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // point to center of CPU segment 21108013Sbinkertn@umich.edu 21118013Sbinkertn@umich.edu// restore all floating regs 21128007Ssaidi@eecs.umich.edu RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1) 21138007Ssaidi@eecs.umich.edu RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1) 21148007Ssaidi@eecs.umich.edu RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1) 21158007Ssaidi@eecs.umich.edu RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1) 21168007Ssaidi@eecs.umich.edu RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1) 21178007Ssaidi@eecs.umich.edu RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1) 21188007Ssaidi@eecs.umich.edu RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1) 21198007Ssaidi@eecs.umich.edu RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1) 21208007Ssaidi@eecs.umich.edu RESTORE_FPR(f8,CNS_Q_FPR+0x40,r1) 21218007Ssaidi@eecs.umich.edu RESTORE_FPR(f9,CNS_Q_FPR+0x48,r1) 21228007Ssaidi@eecs.umich.edu RESTORE_FPR(f10,CNS_Q_FPR+0x50,r1) 21238007Ssaidi@eecs.umich.edu RESTORE_FPR(f11,CNS_Q_FPR+0x58,r1) 21248007Ssaidi@eecs.umich.edu RESTORE_FPR(f12,CNS_Q_FPR+0x60,r1) 21258007Ssaidi@eecs.umich.edu RESTORE_FPR(f13,CNS_Q_FPR+0x68,r1) 21268007Ssaidi@eecs.umich.edu RESTORE_FPR(f14,CNS_Q_FPR+0x70,r1) 21278007Ssaidi@eecs.umich.edu RESTORE_FPR(f15,CNS_Q_FPR+0x78,r1) 21288007Ssaidi@eecs.umich.edu RESTORE_FPR(f16,CNS_Q_FPR+0x80,r1) 21298007Ssaidi@eecs.umich.edu RESTORE_FPR(f17,CNS_Q_FPR+0x88,r1) 21308007Ssaidi@eecs.umich.edu RESTORE_FPR(f18,CNS_Q_FPR+0x90,r1) 21318007Ssaidi@eecs.umich.edu RESTORE_FPR(f19,CNS_Q_FPR+0x98,r1) 21328007Ssaidi@eecs.umich.edu RESTORE_FPR(f20,CNS_Q_FPR+0xA0,r1) 21338007Ssaidi@eecs.umich.edu RESTORE_FPR(f21,CNS_Q_FPR+0xA8,r1) 21348007Ssaidi@eecs.umich.edu RESTORE_FPR(f22,CNS_Q_FPR+0xB0,r1) 21358007Ssaidi@eecs.umich.edu RESTORE_FPR(f23,CNS_Q_FPR+0xB8,r1) 21368007Ssaidi@eecs.umich.edu RESTORE_FPR(f24,CNS_Q_FPR+0xC0,r1) 21378007Ssaidi@eecs.umich.edu RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1) 21388007Ssaidi@eecs.umich.edu RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1) 21398007Ssaidi@eecs.umich.edu RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1) 21408007Ssaidi@eecs.umich.edu RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1) 21418007Ssaidi@eecs.umich.edu RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1) 21428007Ssaidi@eecs.umich.edu RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1) 21438007Ssaidi@eecs.umich.edu RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1) 21448007Ssaidi@eecs.umich.edu 21458013Sbinkertn@umich.edu// switch impure pointer from gpr to ipr area -- 21468007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 21478007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 21488007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Restore base address of impure area. 21498007Ssaidi@eecs.umich.edu lda r1, CNS_Q_IPR(r1) // Point to base of IPR area. 21508013Sbinkertn@umich.edu 21518013Sbinkertn@umich.edu// restore all pal regs 21528007Ssaidi@eecs.umich.edu RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle 21538007Ssaidi@eecs.umich.edu RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1) 21548007Ssaidi@eecs.umich.edu RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1) 21558007Ssaidi@eecs.umich.edu RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1) 21568007Ssaidi@eecs.umich.edu RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1) 21578007Ssaidi@eecs.umich.edu RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1) 21588007Ssaidi@eecs.umich.edu RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1) 21598007Ssaidi@eecs.umich.edu RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1) 21608007Ssaidi@eecs.umich.edu RESTORE_IPR(pt8,CNS_Q_PT+0x40,r1) 21618007Ssaidi@eecs.umich.edu RESTORE_IPR(pt9,CNS_Q_PT+0x48,r1) 21628007Ssaidi@eecs.umich.edu RESTORE_IPR(pt10,CNS_Q_PT+0x50,r1) 21638007Ssaidi@eecs.umich.edu RESTORE_IPR(pt11,CNS_Q_PT+0x58,r1) 21648007Ssaidi@eecs.umich.edu RESTORE_IPR(pt12,CNS_Q_PT+0x60,r1) 21658007Ssaidi@eecs.umich.edu RESTORE_IPR(pt13,CNS_Q_PT+0x68,r1) 21668007Ssaidi@eecs.umich.edu RESTORE_IPR(pt14,CNS_Q_PT+0x70,r1) 21678007Ssaidi@eecs.umich.edu RESTORE_IPR(pt15,CNS_Q_PT+0x78,r1) 21688007Ssaidi@eecs.umich.edu RESTORE_IPR(pt16,CNS_Q_PT+0x80,r1) 21698007Ssaidi@eecs.umich.edu RESTORE_IPR(pt17,CNS_Q_PT+0x88,r1) 21708007Ssaidi@eecs.umich.edu RESTORE_IPR(pt18,CNS_Q_PT+0x90,r1) 21718007Ssaidi@eecs.umich.edu RESTORE_IPR(pt19,CNS_Q_PT+0x98,r1) 21728007Ssaidi@eecs.umich.edu RESTORE_IPR(pt20,CNS_Q_PT+0xA0,r1) 21738007Ssaidi@eecs.umich.edu RESTORE_IPR(pt21,CNS_Q_PT+0xA8,r1) 21748007Ssaidi@eecs.umich.edu RESTORE_IPR(pt22,CNS_Q_PT+0xB0,r1) 21758007Ssaidi@eecs.umich.edu RESTORE_IPR(pt23,CNS_Q_PT+0xB8,r1) 21768007Ssaidi@eecs.umich.edu 21778007Ssaidi@eecs.umich.edu 21788007Ssaidi@eecs.umich.edu//orig restore_reg exc_addr, ipr=1 // restore ipr 21798007Ssaidi@eecs.umich.edu//orig restore_reg pal_base, ipr=1 // restore ipr 21808007Ssaidi@eecs.umich.edu//orig restore_reg ipl, ipr=1 // restore ipr 21818007Ssaidi@eecs.umich.edu//orig restore_reg ps, ipr=1 // restore ipr 21828007Ssaidi@eecs.umich.edu//orig mtpr r0, dtb_cm // set current mode in mbox too 21838007Ssaidi@eecs.umich.edu//orig restore_reg itb_asn, ipr=1 21848007Ssaidi@eecs.umich.edu//orig srl r0, itb_asn_v_asn, r0 21858007Ssaidi@eecs.umich.edu//orig sll r0, dtb_asn_v_asn, r0 21868007Ssaidi@eecs.umich.edu//orig mtpr r0, dtb_asn // set ASN in Mbox too 21878007Ssaidi@eecs.umich.edu//orig restore_reg ivptbr, ipr=1 21888007Ssaidi@eecs.umich.edu//orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr 21898007Ssaidi@eecs.umich.edu//orig restore_reg mcsr, ipr=1 21908007Ssaidi@eecs.umich.edu//orig restore_reg aster, ipr=1 21918007Ssaidi@eecs.umich.edu//orig restore_reg astrr, ipr=1 21928007Ssaidi@eecs.umich.edu//orig restore_reg sirr, ipr=1 21938007Ssaidi@eecs.umich.edu//orig restore_reg maf_mode, ipr=1 // no mbox instruction for 3 cycles 21948007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // (may issue with mt maf_mode) 21958007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // bubble cycle 1 21968007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // bubble cycle 2 21978007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // bubble cycle 3 21988007Ssaidi@eecs.umich.edu//orig mfpr r31, pt0 // (may issue with following ld) 21998007Ssaidi@eecs.umich.edu 22008007Ssaidi@eecs.umich.edu // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag) 22018007Ssaidi@eecs.umich.edu RESTORE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) 22028007Ssaidi@eecs.umich.edu RESTORE_IPR(palBase,CNS_Q_PAL_BASE,r1) 22038007Ssaidi@eecs.umich.edu RESTORE_IPR(ipl,CNS_Q_IPL,r1) 22048007Ssaidi@eecs.umich.edu RESTORE_IPR(ips,CNS_Q_IPS,r1) 22058007Ssaidi@eecs.umich.edu mtpr r0, dtbCm // Set Mbox current mode too. 22068007Ssaidi@eecs.umich.edu RESTORE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) 22078007Ssaidi@eecs.umich.edu srl r0, 4, r0 22088007Ssaidi@eecs.umich.edu sll r0, 57, r0 22098007Ssaidi@eecs.umich.edu mtpr r0, dtbAsn // Set Mbox ASN too 22108007Ssaidi@eecs.umich.edu RESTORE_IPR(iVptBr,CNS_Q_IVPTBR,r1) 22118007Ssaidi@eecs.umich.edu mtpr r0, mVptBr // Set Mbox VptBr too 22128007Ssaidi@eecs.umich.edu RESTORE_IPR(mcsr,CNS_Q_MCSR,r1) 22138007Ssaidi@eecs.umich.edu RESTORE_IPR(aster,CNS_Q_ASTER,r1) 22148007Ssaidi@eecs.umich.edu RESTORE_IPR(astrr,CNS_Q_ASTRR,r1) 22158007Ssaidi@eecs.umich.edu RESTORE_IPR(sirr,CNS_Q_SIRR,r1) 22168007Ssaidi@eecs.umich.edu RESTORE_IPR(mafMode,CNS_Q_MAF_MODE,r1) 22178007Ssaidi@eecs.umich.edu STALL 22188007Ssaidi@eecs.umich.edu STALL 22198007Ssaidi@eecs.umich.edu STALL 22208007Ssaidi@eecs.umich.edu STALL 22218007Ssaidi@eecs.umich.edu STALL 22228007Ssaidi@eecs.umich.edu 22238007Ssaidi@eecs.umich.edu 22248007Ssaidi@eecs.umich.edu // restore all integer shadow regs 22258007Ssaidi@eecs.umich.edu RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code 22268007Ssaidi@eecs.umich.edu RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) 22278007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) 22288007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) 22298007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) 22308007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) 22318007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) 22328007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) 22338007Ssaidi@eecs.umich.edu RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1) 22348007Ssaidi@eecs.umich.edu 22358007Ssaidi@eecs.umich.edu // 22368007Ssaidi@eecs.umich.edu // Get out of shadow mode 22378007Ssaidi@eecs.umich.edu // 22388007Ssaidi@eecs.umich.edu 22398013Sbinkertn@umich.edu mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) 22408013Sbinkertn@umich.edu mfpr r31, pt0 // "" 22418013Sbinkertn@umich.edu mfpr r0, icsr // Get icsr 22428013Sbinkertn@umich.edu ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location 22438013Sbinkertn@umich.edu bic r0, r2, r2 // ICSR with SDE clear 22448013Sbinkertn@umich.edu mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles 22458013Sbinkertn@umich.edu 22468013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 1 22478013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 2 22488013Sbinkertn@umich.edu mfpr r31, pt0 // SDE bubble cycle 3 22498013Sbinkertn@umich.edu nop 22508013Sbinkertn@umich.edu 22518013Sbinkertn@umich.edu// switch impure pointer from ipr to gpr area -- 22528007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 22538007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 22548007Ssaidi@eecs.umich.edu 22558007Ssaidi@eecs.umich.edu// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ... 22568007Ssaidi@eecs.umich.edu 22578007Ssaidi@eecs.umich.edu lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area 22588007Ssaidi@eecs.umich.edu lda r1, 0x200(r1) // Point to center of CPU segment 22598007Ssaidi@eecs.umich.edu 22608013Sbinkertn@umich.edu // restore all integer regs 22618007Ssaidi@eecs.umich.edu RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1) 22628007Ssaidi@eecs.umich.edu RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1) 22638007Ssaidi@eecs.umich.edu RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1) 22648007Ssaidi@eecs.umich.edu RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1) 22658007Ssaidi@eecs.umich.edu RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1) 22668007Ssaidi@eecs.umich.edu RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1) 22678007Ssaidi@eecs.umich.edu RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1) 22688007Ssaidi@eecs.umich.edu RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1) 22698007Ssaidi@eecs.umich.edu RESTORE_GPR(r12,CNS_Q_GPR+0x60,r1) 22708007Ssaidi@eecs.umich.edu RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1) 22718007Ssaidi@eecs.umich.edu RESTORE_GPR(r14,CNS_Q_GPR+0x70,r1) 22728007Ssaidi@eecs.umich.edu RESTORE_GPR(r15,CNS_Q_GPR+0x78,r1) 22738007Ssaidi@eecs.umich.edu RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1) 22748007Ssaidi@eecs.umich.edu RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1) 22758007Ssaidi@eecs.umich.edu RESTORE_GPR(r18,CNS_Q_GPR+0x90,r1) 22768007Ssaidi@eecs.umich.edu RESTORE_GPR(r19,CNS_Q_GPR+0x98,r1) 22778007Ssaidi@eecs.umich.edu RESTORE_GPR(r20,CNS_Q_GPR+0xA0,r1) 22788007Ssaidi@eecs.umich.edu RESTORE_GPR(r21,CNS_Q_GPR+0xA8,r1) 22798007Ssaidi@eecs.umich.edu RESTORE_GPR(r22,CNS_Q_GPR+0xB0,r1) 22808007Ssaidi@eecs.umich.edu RESTORE_GPR(r23,CNS_Q_GPR+0xB8,r1) 22818007Ssaidi@eecs.umich.edu RESTORE_GPR(r24,CNS_Q_GPR+0xC0,r1) 22828007Ssaidi@eecs.umich.edu RESTORE_GPR(r25,CNS_Q_GPR+0xC8,r1) 22838007Ssaidi@eecs.umich.edu RESTORE_GPR(r26,CNS_Q_GPR+0xD0,r1) 22848007Ssaidi@eecs.umich.edu RESTORE_GPR(r27,CNS_Q_GPR+0xD8,r1) 22858007Ssaidi@eecs.umich.edu RESTORE_GPR(r28,CNS_Q_GPR+0xE0,r1) 22868007Ssaidi@eecs.umich.edu RESTORE_GPR(r29,CNS_Q_GPR+0xE8,r1) 22878007Ssaidi@eecs.umich.edu RESTORE_GPR(r30,CNS_Q_GPR+0xF0,r1) 22888007Ssaidi@eecs.umich.edu RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1) 22898007Ssaidi@eecs.umich.edu 22908007Ssaidi@eecs.umich.edu//orig // switch impure pointer from gpr to ipr area -- 22918007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 22928007Ssaidi@eecs.umich.edu//orig fix_impure_ipr r1 22938007Ssaidi@eecs.umich.edu//orig restore_reg icsr, ipr=1 // restore original icsr- 4 bubbles to hw_rei 22948007Ssaidi@eecs.umich.edu 22958007Ssaidi@eecs.umich.edu lda t0, -0x200(t0) // Restore base address of impure area. 22968007Ssaidi@eecs.umich.edu lda t0, CNS_Q_IPR(t0) // Point to base of IPR area again. 22978007Ssaidi@eecs.umich.edu RESTORE_IPR(icsr,CNS_Q_ICSR,r1) 22988007Ssaidi@eecs.umich.edu 22998007Ssaidi@eecs.umich.edu//orig // and back again -- 23008007Ssaidi@eecs.umich.edu//orig unfix_impure_ipr r1 23018007Ssaidi@eecs.umich.edu//orig fix_impure_gpr r1 23028007Ssaidi@eecs.umich.edu//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag 23038007Ssaidi@eecs.umich.edu//orig mb 23048007Ssaidi@eecs.umich.edu 23058007Ssaidi@eecs.umich.edu lda t0, -CNS_Q_IPR(t0) // Back to base of impure area again, 23068007Ssaidi@eecs.umich.edu lda t0, 0x200(t0) // and back to center of CPU segment 23078007Ssaidi@eecs.umich.edu SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag 23088007Ssaidi@eecs.umich.edu mb 23098007Ssaidi@eecs.umich.edu 23108007Ssaidi@eecs.umich.edu//orig // and back we go 23118007Ssaidi@eecs.umich.edu//orig// restore_reg 3 23128007Ssaidi@eecs.umich.edu//orig restore_reg 2 23138007Ssaidi@eecs.umich.edu//orig// restore_reg 1 23148007Ssaidi@eecs.umich.edu//orig restore_reg 0 23158007Ssaidi@eecs.umich.edu//orig // restore impure area base 23168007Ssaidi@eecs.umich.edu//orig unfix_impure_gpr r1 23178007Ssaidi@eecs.umich.edu 23188007Ssaidi@eecs.umich.edu RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1) 23198007Ssaidi@eecs.umich.edu RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1) 23208007Ssaidi@eecs.umich.edu lda r1, -0x200(r1) // Restore impure base address 23218007Ssaidi@eecs.umich.edu 23228013Sbinkertn@umich.edu mfpr r31, pt0 // stall for ldq_p above //orig 23238007Ssaidi@eecs.umich.edu 23248007Ssaidi@eecs.umich.edu mtpr r31, dtb_ia // clear the tb //orig 23258007Ssaidi@eecs.umich.edu mtpr r31, itb_ia // clear the itb //orig 23268007Ssaidi@eecs.umich.edu 23278007Ssaidi@eecs.umich.edu//orig pvc_jsr rststa, bsr=1, dest=1 23288007Ssaidi@eecs.umich.edu ret r31, (r3) // back we go //orig 23298013Sbinkertn@umich.edu 23308013Sbinkertn@umich.edu 23318013Sbinkertn@umich.edu// 23328007Ssaidi@eecs.umich.edu// pal_pal_bug_check -- code has found a bugcheck situation. 23338007Ssaidi@eecs.umich.edu// Set things up and join common machine check flow. 23348007Ssaidi@eecs.umich.edu// 23358007Ssaidi@eecs.umich.edu// Input: 23368007Ssaidi@eecs.umich.edu// r14 - exc_addr 23378007Ssaidi@eecs.umich.edu// 23388007Ssaidi@eecs.umich.edu// On exit: 23398007Ssaidi@eecs.umich.edu// pt0 - saved r0 23408007Ssaidi@eecs.umich.edu// pt1 - saved r1 23418007Ssaidi@eecs.umich.edu// pt4 - saved r4 23428007Ssaidi@eecs.umich.edu// pt5 - saved r5 23438007Ssaidi@eecs.umich.edu// pt6 - saved r6 23448007Ssaidi@eecs.umich.edu// pt10 - saved exc_addr 23458007Ssaidi@eecs.umich.edu// pt_misc<47:32> - mchk code 23468007Ssaidi@eecs.umich.edu// pt_misc<31:16> - scb vector 23478007Ssaidi@eecs.umich.edu// r14 - base of Cbox IPRs in IO space 23488007Ssaidi@eecs.umich.edu// MCES<mchk> is set 23498013Sbinkertn@umich.edu// 23508007Ssaidi@eecs.umich.edu 23518007Ssaidi@eecs.umich.edu ALIGN_BLOCK 23528007Ssaidi@eecs.umich.edu .globl pal_pal_bug_check_from_int 23538007Ssaidi@eecs.umich.edupal_pal_bug_check_from_int: 23548007Ssaidi@eecs.umich.edu DEBUGSTORE(0x79) 23558007Ssaidi@eecs.umich.edu//simos DEBUG_EXC_ADDR() 23568007Ssaidi@eecs.umich.edu DEBUGSTORE(0x20) 23578007Ssaidi@eecs.umich.edu//simos bsr r25, put_hex 23588007Ssaidi@eecs.umich.edu lda r25, mchk_c_bugcheck(r31) 23598007Ssaidi@eecs.umich.edu addq r25, 1, r25 // set flag indicating we came from interrupt and stack is already pushed 23608007Ssaidi@eecs.umich.edu br r31, pal_pal_mchk 23618007Ssaidi@eecs.umich.edu nop 23628007Ssaidi@eecs.umich.edu 23638007Ssaidi@eecs.umich.edupal_pal_bug_check: 23648007Ssaidi@eecs.umich.edu lda r25, mchk_c_bugcheck(r31) 23658007Ssaidi@eecs.umich.edu 23668007Ssaidi@eecs.umich.edupal_pal_mchk: 23678007Ssaidi@eecs.umich.edu sll r25, 32, r25 // Move mchk code to position 23688007Ssaidi@eecs.umich.edu 23698007Ssaidi@eecs.umich.edu mtpr r14, pt10 // Stash exc_addr 23708007Ssaidi@eecs.umich.edu mtpr r14, exc_addr 23718007Ssaidi@eecs.umich.edu 23728007Ssaidi@eecs.umich.edu mfpr r12, pt_misc // Get MCES and scratch 23738007Ssaidi@eecs.umich.edu zap r12, 0x3c, r12 23748007Ssaidi@eecs.umich.edu 23758007Ssaidi@eecs.umich.edu or r12, r25, r12 // Combine mchk code 23768007Ssaidi@eecs.umich.edu lda r25, scb_v_procmchk(r31) // Get SCB vector 23778007Ssaidi@eecs.umich.edu 23788007Ssaidi@eecs.umich.edu sll r25, 16, r25 // Move SCBv to position 23798007Ssaidi@eecs.umich.edu or r12, r25, r25 // Combine SCBv 23808007Ssaidi@eecs.umich.edu 23818007Ssaidi@eecs.umich.edu mtpr r0, pt0 // Stash for scratch 23828007Ssaidi@eecs.umich.edu bis r25, mces_m_mchk, r25 // Set MCES<MCHK> bit 23838007Ssaidi@eecs.umich.edu 23848007Ssaidi@eecs.umich.edu mtpr r25, pt_misc // Save mchk code!scbv!whami!mces 23858007Ssaidi@eecs.umich.edu ldah r14, 0xfff0(r31) 23868007Ssaidi@eecs.umich.edu 23878007Ssaidi@eecs.umich.edu mtpr r1, pt1 // Stash for scratch 23888007Ssaidi@eecs.umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 23898007Ssaidi@eecs.umich.edu 23908007Ssaidi@eecs.umich.edu mtpr r4, pt4 23918007Ssaidi@eecs.umich.edu mtpr r5, pt5 23928007Ssaidi@eecs.umich.edu 23938007Ssaidi@eecs.umich.edu mtpr r6, pt6 23948007Ssaidi@eecs.umich.edu blbs r12, sys_double_machine_check // MCHK halt if double machine check 23958007Ssaidi@eecs.umich.edu 23968007Ssaidi@eecs.umich.edu br r31, sys_mchk_collect_iprs // Join common machine check flow 23978007Ssaidi@eecs.umich.edu 23988013Sbinkertn@umich.edu 23998013Sbinkertn@umich.edu 24008013Sbinkertn@umich.edu// align_to_call_pal_section 24018013Sbinkertn@umich.edu// Align to address of first call_pal entry point - 2000 24028013Sbinkertn@umich.edu 24038013Sbinkertn@umich.edu// 24048013Sbinkertn@umich.edu// HALT - PALcode for HALT instruction 24058007Ssaidi@eecs.umich.edu// 24068007Ssaidi@eecs.umich.edu// Entry: 24078007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 24088007Ssaidi@eecs.umich.edu// 24098007Ssaidi@eecs.umich.edu// Function: 24108007Ssaidi@eecs.umich.edu// GO to console code 24118007Ssaidi@eecs.umich.edu// 24128013Sbinkertn@umich.edu// 24138007Ssaidi@eecs.umich.edu 24148007Ssaidi@eecs.umich.edu .text 1 24158007Ssaidi@eecs.umich.edu// . = 0x2000 24168007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_HALT_ENTRY) 24178007Ssaidi@eecs.umich.educall_pal_halt: 24188007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad exc_addr read 24198007Ssaidi@eecs.umich.edu mfpr r31, pt0 24208007Ssaidi@eecs.umich.edu 24218007Ssaidi@eecs.umich.edu mfpr r12, exc_addr // get PC 24228007Ssaidi@eecs.umich.edu subq r12, 4, r12 // Point to the HALT 24238007Ssaidi@eecs.umich.edu 24248007Ssaidi@eecs.umich.edu mtpr r12, exc_addr 24258007Ssaidi@eecs.umich.edu mtpr r0, pt0 24268007Ssaidi@eecs.umich.edu 24278007Ssaidi@eecs.umich.edu//orig pvc_jsr updpcb, bsr=1 24288007Ssaidi@eecs.umich.edu bsr r0, pal_update_pcb // update the pcb 24298007Ssaidi@eecs.umich.edu lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt 24308007Ssaidi@eecs.umich.edu br r31, sys_enter_console // enter the console 24318007Ssaidi@eecs.umich.edu 24328013Sbinkertn@umich.edu// 24338013Sbinkertn@umich.edu// CFLUSH - PALcode for CFLUSH instruction 24348007Ssaidi@eecs.umich.edu// 24358007Ssaidi@eecs.umich.edu// Entry: 24368007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 24378007Ssaidi@eecs.umich.edu// 24388007Ssaidi@eecs.umich.edu// R16 - contains the PFN of the page to be flushed 24398007Ssaidi@eecs.umich.edu// 24408007Ssaidi@eecs.umich.edu// Function: 24418007Ssaidi@eecs.umich.edu// Flush all Dstream caches of 1 entire page 24428007Ssaidi@eecs.umich.edu// The CFLUSH routine is in the system specific module. 24438007Ssaidi@eecs.umich.edu// 24448013Sbinkertn@umich.edu// 24458007Ssaidi@eecs.umich.edu 24468007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_CFLUSH_ENTRY) 24478007Ssaidi@eecs.umich.eduCall_Pal_Cflush: 24488007Ssaidi@eecs.umich.edu br r31, sys_cflush 24498007Ssaidi@eecs.umich.edu 24508013Sbinkertn@umich.edu// 24518013Sbinkertn@umich.edu// DRAINA - PALcode for DRAINA instruction 24528007Ssaidi@eecs.umich.edu// 24538007Ssaidi@eecs.umich.edu// Entry: 24548007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 24558007Ssaidi@eecs.umich.edu// Implicit TRAPB performed by hardware. 24568007Ssaidi@eecs.umich.edu// 24578007Ssaidi@eecs.umich.edu// Function: 24588007Ssaidi@eecs.umich.edu// Stall instruction issue until all prior instructions are guaranteed to 24598007Ssaidi@eecs.umich.edu// complete without incurring aborts. For the EV5 implementation, this 24608007Ssaidi@eecs.umich.edu// means waiting until all pending DREADS are returned. 24618007Ssaidi@eecs.umich.edu// 24628013Sbinkertn@umich.edu// 24638007Ssaidi@eecs.umich.edu 24648007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_DRAINA_ENTRY) 24658007Ssaidi@eecs.umich.eduCall_Pal_Draina: 24668007Ssaidi@eecs.umich.edu ldah r14, 0x100(r31) // Init counter. Value? 24678007Ssaidi@eecs.umich.edu nop 24688007Ssaidi@eecs.umich.edu 24698007Ssaidi@eecs.umich.eduDRAINA_LOOP: 24708007Ssaidi@eecs.umich.edu subq r14, 1, r14 // Decrement counter 24718007Ssaidi@eecs.umich.edu mfpr r13, ev5__maf_mode // Fetch status bit 24728007Ssaidi@eecs.umich.edu 24738007Ssaidi@eecs.umich.edu srl r13, maf_mode_v_dread_pending, r13 24748007Ssaidi@eecs.umich.edu ble r14, DRAINA_LOOP_TOO_LONG 24758007Ssaidi@eecs.umich.edu 24768007Ssaidi@eecs.umich.edu nop 24778007Ssaidi@eecs.umich.edu blbs r13, DRAINA_LOOP // Wait until all DREADS clear 24788007Ssaidi@eecs.umich.edu 24798007Ssaidi@eecs.umich.edu hw_rei 24808007Ssaidi@eecs.umich.edu 24818007Ssaidi@eecs.umich.eduDRAINA_LOOP_TOO_LONG: 24828007Ssaidi@eecs.umich.edu br r31, call_pal_halt 24838007Ssaidi@eecs.umich.edu 24848013Sbinkertn@umich.edu// CALL_PAL OPCDECs 24858007Ssaidi@eecs.umich.edu 24868007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0003) 24878007Ssaidi@eecs.umich.eduCallPal_OpcDec03: 24888007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 24898007Ssaidi@eecs.umich.edu 24908007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0004) 24918007Ssaidi@eecs.umich.eduCallPal_OpcDec04: 24928007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 24938007Ssaidi@eecs.umich.edu 24948007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0005) 24958007Ssaidi@eecs.umich.eduCallPal_OpcDec05: 24968007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 24978007Ssaidi@eecs.umich.edu 24988007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0006) 24998007Ssaidi@eecs.umich.eduCallPal_OpcDec06: 25008007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 25018007Ssaidi@eecs.umich.edu 25028007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0007) 25038007Ssaidi@eecs.umich.eduCallPal_OpcDec07: 25048007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 25058007Ssaidi@eecs.umich.edu 25068007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0008) 25078007Ssaidi@eecs.umich.eduCallPal_OpcDec08: 25088007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 25098007Ssaidi@eecs.umich.edu 25108013Sbinkertn@umich.edu// 25118013Sbinkertn@umich.edu// CSERVE - PALcode for CSERVE instruction 25128007Ssaidi@eecs.umich.edu// 25138007Ssaidi@eecs.umich.edu// Entry: 25148007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 25158007Ssaidi@eecs.umich.edu// 25168007Ssaidi@eecs.umich.edu// Function: 25178007Ssaidi@eecs.umich.edu// Various functions for private use of console software 25188007Ssaidi@eecs.umich.edu// 25198007Ssaidi@eecs.umich.edu// option selector in r0 25208007Ssaidi@eecs.umich.edu// arguments in r16.... 25218007Ssaidi@eecs.umich.edu// The CSERVE routine is in the system specific module. 25228007Ssaidi@eecs.umich.edu// 25238013Sbinkertn@umich.edu// 25248007Ssaidi@eecs.umich.edu 25258007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_CSERVE_ENTRY) 25268007Ssaidi@eecs.umich.eduCall_Pal_Cserve: 25278007Ssaidi@eecs.umich.edu br r31, sys_cserve 25288007Ssaidi@eecs.umich.edu 25298013Sbinkertn@umich.edu// 25308013Sbinkertn@umich.edu// swppal - PALcode for swppal instruction 25318007Ssaidi@eecs.umich.edu// 25328007Ssaidi@eecs.umich.edu// Entry: 25338007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 25348007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 25358007Ssaidi@eecs.umich.edu// R16 contains the new PAL identifier 25368007Ssaidi@eecs.umich.edu// R17:R21 contain implementation-specific entry parameters 25378007Ssaidi@eecs.umich.edu// 25388007Ssaidi@eecs.umich.edu// R0 receives status: 25398007Ssaidi@eecs.umich.edu// 0 success (PAL was switched) 25408007Ssaidi@eecs.umich.edu// 1 unknown PAL variant 25418007Ssaidi@eecs.umich.edu// 2 known PAL variant, but PAL not loaded 25428007Ssaidi@eecs.umich.edu// 25438007Ssaidi@eecs.umich.edu// 25448007Ssaidi@eecs.umich.edu// Function: 25458007Ssaidi@eecs.umich.edu// Swap control to another PAL. 25468013Sbinkertn@umich.edu// 25478007Ssaidi@eecs.umich.edu 25488007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_SWPPAL_ENTRY) 25498007Ssaidi@eecs.umich.eduCall_Pal_Swppal: 25508007Ssaidi@eecs.umich.edu cmpule r16, 255, r0 // see if a kibble was passed 25518007Ssaidi@eecs.umich.edu cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59) 25528007Ssaidi@eecs.umich.edu 25538007Ssaidi@eecs.umich.edu or r16, r31, r3 // set r3 incase this is a address 25548007Ssaidi@eecs.umich.edu blbc r0, swppal_cont // nope, try it as an address 25558007Ssaidi@eecs.umich.edu 25568007Ssaidi@eecs.umich.edu cmpeq r16, 2, r0 // is it our friend OSF? 25578007Ssaidi@eecs.umich.edu blbc r0, swppal_fail // nope, don't know this fellow 25588007Ssaidi@eecs.umich.edu 25598007Ssaidi@eecs.umich.edu br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF 25608007Ssaidi@eecs.umich.edu 25618007Ssaidi@eecs.umich.edu// .global osfpal_hw_entry_reset 25628007Ssaidi@eecs.umich.edu// .weak osfpal_hw_entry_reset 25638007Ssaidi@eecs.umich.edu// .long <osfpal_hw_entry_reset-pal_start> 25648007Ssaidi@eecs.umich.edu//orig halt // don't know how to get the address here - kludge ok, load pal at 0 25658007Ssaidi@eecs.umich.edu .long 0 // ?? hack upon hack...pb 25668007Ssaidi@eecs.umich.edu 25678013Sbinkertn@umich.eduCALL_PAL_SWPPAL_10_: ldl_p r3, 0(r2) // fetch target addr 25688007Ssaidi@eecs.umich.edu// ble r3, swppal_fail ; if OSF not linked in say not loaded. 25698007Ssaidi@eecs.umich.edu mfpr r2, pal_base // fetch pal base 25708007Ssaidi@eecs.umich.edu 25718007Ssaidi@eecs.umich.edu addq r2, r3, r3 // add pal base 25728007Ssaidi@eecs.umich.edu lda r2, 0x3FFF(r31) // get pal base checker mask 25738007Ssaidi@eecs.umich.edu 25748007Ssaidi@eecs.umich.edu and r3, r2, r2 // any funky bits set? 25758007Ssaidi@eecs.umich.edu cmpeq r2, 0, r0 // 25768007Ssaidi@eecs.umich.edu 25778007Ssaidi@eecs.umich.edu blbc r0, swppal_fail // return unknown if bad bit set. 25788007Ssaidi@eecs.umich.edu br r31, swppal_cont 25798007Ssaidi@eecs.umich.edu 25808007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 25818007Ssaidi@eecs.umich.edu 25828007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x000B) 25838007Ssaidi@eecs.umich.eduCallPal_OpcDec0B: 25848007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 25858007Ssaidi@eecs.umich.edu 25868007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x000C) 25878007Ssaidi@eecs.umich.eduCallPal_OpcDec0C: 25888007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 25898007Ssaidi@eecs.umich.edu 25908013Sbinkertn@umich.edu// 25918013Sbinkertn@umich.edu// wripir - PALcode for wripir instruction 25928007Ssaidi@eecs.umich.edu// 25938007Ssaidi@eecs.umich.edu// Entry: 25948007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 25958007Ssaidi@eecs.umich.edu// r16 = processor number to interrupt 25968007Ssaidi@eecs.umich.edu// 25978007Ssaidi@eecs.umich.edu// Function: 25988007Ssaidi@eecs.umich.edu// IPIR <- R16 25998007Ssaidi@eecs.umich.edu// Handled in system-specific code 26008007Ssaidi@eecs.umich.edu// 26018007Ssaidi@eecs.umich.edu// Exit: 26028007Ssaidi@eecs.umich.edu// interprocessor interrupt is recorded on the target processor 26038007Ssaidi@eecs.umich.edu// and is initiated when the proper enabling conditions are present. 26048013Sbinkertn@umich.edu// 26058007Ssaidi@eecs.umich.edu 26068007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRIPIR_ENTRY) 26078007Ssaidi@eecs.umich.eduCall_Pal_Wrpir: 26088007Ssaidi@eecs.umich.edu br r31, sys_wripir 26098007Ssaidi@eecs.umich.edu 26108007Ssaidi@eecs.umich.edu// .sbttl "CALL_PAL OPCDECs" 26118007Ssaidi@eecs.umich.edu 26128007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x000E) 26138007Ssaidi@eecs.umich.eduCallPal_OpcDec0E: 26148007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 26158007Ssaidi@eecs.umich.edu 26168007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x000F) 26178007Ssaidi@eecs.umich.eduCallPal_OpcDec0F: 26188007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 26198007Ssaidi@eecs.umich.edu 26208013Sbinkertn@umich.edu// 26218013Sbinkertn@umich.edu// rdmces - PALcode for rdmces instruction 26228007Ssaidi@eecs.umich.edu// 26238007Ssaidi@eecs.umich.edu// Entry: 26248007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 26258007Ssaidi@eecs.umich.edu// 26268007Ssaidi@eecs.umich.edu// Function: 26278007Ssaidi@eecs.umich.edu// R0 <- ZEXT(MCES) 26288013Sbinkertn@umich.edu// 26298007Ssaidi@eecs.umich.edu 26308007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RDMCES_ENTRY) 26318007Ssaidi@eecs.umich.eduCall_Pal_Rdmces: 26328007Ssaidi@eecs.umich.edu mfpr r0, pt_mces // Read from PALtemp 26338007Ssaidi@eecs.umich.edu and r0, mces_m_all, r0 // Clear other bits 26348007Ssaidi@eecs.umich.edu 26358007Ssaidi@eecs.umich.edu hw_rei 26368007Ssaidi@eecs.umich.edu 26378013Sbinkertn@umich.edu// 26388013Sbinkertn@umich.edu// wrmces - PALcode for wrmces instruction 26398007Ssaidi@eecs.umich.edu// 26408007Ssaidi@eecs.umich.edu// Entry: 26418007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 26428007Ssaidi@eecs.umich.edu// 26438007Ssaidi@eecs.umich.edu// Function: 26448007Ssaidi@eecs.umich.edu// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK) 26458007Ssaidi@eecs.umich.edu// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE) 26468007Ssaidi@eecs.umich.edu// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE) 26478007Ssaidi@eecs.umich.edu// MCES<3> <- R16<3> (DPC) 26488007Ssaidi@eecs.umich.edu// MCES<4> <- R16<4> (DSC) 26498007Ssaidi@eecs.umich.edu// 26508013Sbinkertn@umich.edu// 26518007Ssaidi@eecs.umich.edu 26528007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRMCES_ENTRY) 26538007Ssaidi@eecs.umich.eduCall_Pal_Wrmces: 26548007Ssaidi@eecs.umich.edu and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE 26558007Ssaidi@eecs.umich.edu mfpr r14, pt_mces // Get current value 26568007Ssaidi@eecs.umich.edu 26578007Ssaidi@eecs.umich.edu ornot r31, r13, r13 // Flip all the bits 26588007Ssaidi@eecs.umich.edu and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17 26598007Ssaidi@eecs.umich.edu 26608007Ssaidi@eecs.umich.edu and r14, r13, r1 // Update MCHK, SCE, PCE 26618007Ssaidi@eecs.umich.edu bic r1, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r1 // Clear old DPC, DSC 26628007Ssaidi@eecs.umich.edu 26638007Ssaidi@eecs.umich.edu or r1, r17, r1 // Update DPC and DSC 26648007Ssaidi@eecs.umich.edu mtpr r1, pt_mces // Write MCES back 26658007Ssaidi@eecs.umich.edu 26668007Ssaidi@eecs.umich.edu nop // Pad to fix PT write->read restriction 26678007Ssaidi@eecs.umich.edu 26688007Ssaidi@eecs.umich.edu nop 26698007Ssaidi@eecs.umich.edu hw_rei 26708007Ssaidi@eecs.umich.edu 26718007Ssaidi@eecs.umich.edu 26728007Ssaidi@eecs.umich.edu 26738013Sbinkertn@umich.edu// CALL_PAL OPCDECs 26748007Ssaidi@eecs.umich.edu 26758007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0012) 26768007Ssaidi@eecs.umich.eduCallPal_OpcDec12: 26778007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 26788007Ssaidi@eecs.umich.edu 26798007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0013) 26808007Ssaidi@eecs.umich.eduCallPal_OpcDec13: 26818007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 26828007Ssaidi@eecs.umich.edu 26838007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0014) 26848007Ssaidi@eecs.umich.eduCallPal_OpcDec14: 26858007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 26868007Ssaidi@eecs.umich.edu 26878007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0015) 26888007Ssaidi@eecs.umich.eduCallPal_OpcDec15: 26898007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 26908007Ssaidi@eecs.umich.edu 26918007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0016) 26928007Ssaidi@eecs.umich.eduCallPal_OpcDec16: 26938007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 26948007Ssaidi@eecs.umich.edu 26958007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0017) 26968007Ssaidi@eecs.umich.eduCallPal_OpcDec17: 26978007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 26988007Ssaidi@eecs.umich.edu 26998007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0018) 27008007Ssaidi@eecs.umich.eduCallPal_OpcDec18: 27018007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27028007Ssaidi@eecs.umich.edu 27038007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0019) 27048007Ssaidi@eecs.umich.eduCallPal_OpcDec19: 27058007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27068007Ssaidi@eecs.umich.edu 27078007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001A) 27088007Ssaidi@eecs.umich.eduCallPal_OpcDec1A: 27098007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27108007Ssaidi@eecs.umich.edu 27118007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001B) 27128007Ssaidi@eecs.umich.eduCallPal_OpcDec1B: 27138007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27148007Ssaidi@eecs.umich.edu 27158007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001C) 27168007Ssaidi@eecs.umich.eduCallPal_OpcDec1C: 27178007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27188007Ssaidi@eecs.umich.edu 27198007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001D) 27208007Ssaidi@eecs.umich.eduCallPal_OpcDec1D: 27218007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27228007Ssaidi@eecs.umich.edu 27238007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001E) 27248007Ssaidi@eecs.umich.eduCallPal_OpcDec1E: 27258007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27268007Ssaidi@eecs.umich.edu 27278007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x001F) 27288007Ssaidi@eecs.umich.eduCallPal_OpcDec1F: 27298007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27308007Ssaidi@eecs.umich.edu 27318007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0020) 27328007Ssaidi@eecs.umich.eduCallPal_OpcDec20: 27338007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27348007Ssaidi@eecs.umich.edu 27358007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0021) 27368007Ssaidi@eecs.umich.eduCallPal_OpcDec21: 27378007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27388007Ssaidi@eecs.umich.edu 27398007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0022) 27408007Ssaidi@eecs.umich.eduCallPal_OpcDec22: 27418007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27428007Ssaidi@eecs.umich.edu 27438007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0023) 27448007Ssaidi@eecs.umich.eduCallPal_OpcDec23: 27458007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27468007Ssaidi@eecs.umich.edu 27478007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0024) 27488007Ssaidi@eecs.umich.eduCallPal_OpcDec24: 27498007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27508007Ssaidi@eecs.umich.edu 27518007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0025) 27528007Ssaidi@eecs.umich.eduCallPal_OpcDec25: 27538007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27548007Ssaidi@eecs.umich.edu 27558007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0026) 27568007Ssaidi@eecs.umich.eduCallPal_OpcDec26: 27578007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27588007Ssaidi@eecs.umich.edu 27598007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0027) 27608007Ssaidi@eecs.umich.eduCallPal_OpcDec27: 27618007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27628007Ssaidi@eecs.umich.edu 27638007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0028) 27648007Ssaidi@eecs.umich.eduCallPal_OpcDec28: 27658007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27668007Ssaidi@eecs.umich.edu 27678007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0029) 27688007Ssaidi@eecs.umich.eduCallPal_OpcDec29: 27698007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27708007Ssaidi@eecs.umich.edu 27718007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x002A) 27728007Ssaidi@eecs.umich.eduCallPal_OpcDec2A: 27738007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 27748007Ssaidi@eecs.umich.edu 27758013Sbinkertn@umich.edu// 27768013Sbinkertn@umich.edu// wrfen - PALcode for wrfen instruction 27778007Ssaidi@eecs.umich.edu// 27788007Ssaidi@eecs.umich.edu// Entry: 27798007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 27808007Ssaidi@eecs.umich.edu// 27818007Ssaidi@eecs.umich.edu// Function: 27828007Ssaidi@eecs.umich.edu// a0<0> -> ICSR<FPE> 27838007Ssaidi@eecs.umich.edu// Store new FEN in PCB 27848013Sbinkertn@umich.edu// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) 27858013Sbinkertn@umich.edu// are UNPREDICTABLE 27868007Ssaidi@eecs.umich.edu// 27878007Ssaidi@eecs.umich.edu// Issue: What about pending FP loads when FEN goes from on->off???? 27888013Sbinkertn@umich.edu// 27898007Ssaidi@eecs.umich.edu 27908007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRFEN_ENTRY) 27918007Ssaidi@eecs.umich.eduCall_Pal_Wrfen: 27928007Ssaidi@eecs.umich.edu or r31, 1, r13 // Get a one 27938007Ssaidi@eecs.umich.edu mfpr r1, ev5__icsr // Get current FPE 27948007Ssaidi@eecs.umich.edu 27958007Ssaidi@eecs.umich.edu sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0 27968007Ssaidi@eecs.umich.edu and r16, 1, r16 // clean new fen 27978007Ssaidi@eecs.umich.edu 27988007Ssaidi@eecs.umich.edu sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position 27998007Ssaidi@eecs.umich.edu bic r1, r13, r1 // zero icsr<fpe> 28008007Ssaidi@eecs.umich.edu 28018007Ssaidi@eecs.umich.edu or r1, r12, r1 // Or new FEN into ICSR 28028007Ssaidi@eecs.umich.edu mfpr r12, pt_pcbb // Get PCBB - E1 28038007Ssaidi@eecs.umich.edu 28048007Ssaidi@eecs.umich.edu mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI 28058013Sbinkertn@umich.edu stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB. 28068007Ssaidi@eecs.umich.edu 28078007Ssaidi@eecs.umich.edu mfpr r31, pt0 // Pad ICSR<FPE> write. 28088007Ssaidi@eecs.umich.edu mfpr r31, pt0 28098007Ssaidi@eecs.umich.edu 28108007Ssaidi@eecs.umich.edu mfpr r31, pt0 28118007Ssaidi@eecs.umich.edu// pvc_violate 225 // cuz PVC can't distinguish which bits changed 28128007Ssaidi@eecs.umich.edu hw_rei 28138007Ssaidi@eecs.umich.edu 28148007Ssaidi@eecs.umich.edu 28158007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x002C) 28168007Ssaidi@eecs.umich.eduCallPal_OpcDec2C: 28178007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 28188007Ssaidi@eecs.umich.edu 28198013Sbinkertn@umich.edu// 28208013Sbinkertn@umich.edu// wrvptpr - PALcode for wrvptpr instruction 28218007Ssaidi@eecs.umich.edu// 28228007Ssaidi@eecs.umich.edu// Entry: 28238007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 28248007Ssaidi@eecs.umich.edu// 28258007Ssaidi@eecs.umich.edu// Function: 28268007Ssaidi@eecs.umich.edu// vptptr <- a0 (r16) 28278013Sbinkertn@umich.edu// 28288007Ssaidi@eecs.umich.edu 28298007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY) 28308007Ssaidi@eecs.umich.eduCall_Pal_Wrvptptr: 28318007Ssaidi@eecs.umich.edu mtpr r16, ev5__mvptbr // Load Mbox copy 28328007Ssaidi@eecs.umich.edu mtpr r16, ev5__ivptbr // Load Ibox copy 28338007Ssaidi@eecs.umich.edu nop // Pad IPR write 28348007Ssaidi@eecs.umich.edu nop 28358007Ssaidi@eecs.umich.edu hw_rei 28368007Ssaidi@eecs.umich.edu 28378007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x002E) 28388007Ssaidi@eecs.umich.eduCallPal_OpcDec2E: 28398007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 28408007Ssaidi@eecs.umich.edu 28418007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x002F) 28428007Ssaidi@eecs.umich.eduCallPal_OpcDec2F: 28438007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 28448007Ssaidi@eecs.umich.edu 28458013Sbinkertn@umich.edu 28468013Sbinkertn@umich.edu// 28478013Sbinkertn@umich.edu// swpctx - PALcode for swpctx instruction 28488007Ssaidi@eecs.umich.edu// 28498007Ssaidi@eecs.umich.edu// Entry: 28508007Ssaidi@eecs.umich.edu// hardware dispatch via callPal instruction 28518007Ssaidi@eecs.umich.edu// R16 -> new pcb 28528007Ssaidi@eecs.umich.edu// 28538007Ssaidi@eecs.umich.edu// Function: 28548007Ssaidi@eecs.umich.edu// dynamic state moved to old pcb 28558007Ssaidi@eecs.umich.edu// new state loaded from new pcb 28568007Ssaidi@eecs.umich.edu// pcbb pointer set 28578007Ssaidi@eecs.umich.edu// old pcbb returned in R0 28588007Ssaidi@eecs.umich.edu// 28598007Ssaidi@eecs.umich.edu// Note: need to add perf monitor stuff 28608013Sbinkertn@umich.edu// 28618007Ssaidi@eecs.umich.edu 28628007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_SWPCTX_ENTRY) 28638007Ssaidi@eecs.umich.eduCall_Pal_Swpctx: 28648007Ssaidi@eecs.umich.edu rpcc r13 // get cyccounter 28658007Ssaidi@eecs.umich.edu mfpr r0, pt_pcbb // get pcbb 28668007Ssaidi@eecs.umich.edu 28678013Sbinkertn@umich.edu ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme 28688013Sbinkertn@umich.edu ldq_p r23, osfpcb_l_cc(r16) // get new asn 28698007Ssaidi@eecs.umich.edu 28708007Ssaidi@eecs.umich.edu srl r13, 32, r25 // move offset 28718007Ssaidi@eecs.umich.edu mfpr r24, pt_usp // get usp 28728007Ssaidi@eecs.umich.edu 28738013Sbinkertn@umich.edu stq_p r30, osfpcb_q_ksp(r0) // store old ksp 28748013Sbinkertn@umich.edu// pvc_violate 379 // stq_p can't trap except replay. only problem if mf same ipr in same shadow. 28758007Ssaidi@eecs.umich.edu mtpr r16, pt_pcbb // set new pcbb 28768007Ssaidi@eecs.umich.edu 28778013Sbinkertn@umich.edu stq_p r24, osfpcb_q_usp(r0) // store usp 28788007Ssaidi@eecs.umich.edu addl r13, r25, r25 // merge for new time 28798007Ssaidi@eecs.umich.edu 28808013Sbinkertn@umich.edu stl_p r25, osfpcb_l_cc(r0) // save time 28818007Ssaidi@eecs.umich.edu ldah r24, (1<<(icsr_v_fpe-16))(r31) 28828007Ssaidi@eecs.umich.edu 28838007Ssaidi@eecs.umich.edu and r22, 1, r12 // isolate fen 28848007Ssaidi@eecs.umich.edu mfpr r25, icsr // get current icsr 28858007Ssaidi@eecs.umich.edu 28868013Sbinkertn@umich.edu lda r24, (1<<icsr_v_pmp)(r24) 28878007Ssaidi@eecs.umich.edu br r31, swpctx_cont 28888007Ssaidi@eecs.umich.edu 28898013Sbinkertn@umich.edu// 28908013Sbinkertn@umich.edu// wrval - PALcode for wrval instruction 28918007Ssaidi@eecs.umich.edu// 28928007Ssaidi@eecs.umich.edu// Entry: 28938007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 28948007Ssaidi@eecs.umich.edu// 28958007Ssaidi@eecs.umich.edu// Function: 28968007Ssaidi@eecs.umich.edu// sysvalue <- a0 (r16) 28978013Sbinkertn@umich.edu// 28988007Ssaidi@eecs.umich.edu 28998007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRVAL_ENTRY) 29008007Ssaidi@eecs.umich.eduCall_Pal_Wrval: 29018007Ssaidi@eecs.umich.edu nop 29028007Ssaidi@eecs.umich.edu mtpr r16, pt_sysval // Pad paltemp write 29038007Ssaidi@eecs.umich.edu nop 29048007Ssaidi@eecs.umich.edu nop 29058007Ssaidi@eecs.umich.edu hw_rei 29068007Ssaidi@eecs.umich.edu 29078013Sbinkertn@umich.edu// 29088013Sbinkertn@umich.edu// rdval - PALcode for rdval instruction 29098007Ssaidi@eecs.umich.edu// 29108007Ssaidi@eecs.umich.edu// Entry: 29118007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 29128007Ssaidi@eecs.umich.edu// 29138007Ssaidi@eecs.umich.edu// Function: 29148007Ssaidi@eecs.umich.edu// v0 (r0) <- sysvalue 29158013Sbinkertn@umich.edu// 29168007Ssaidi@eecs.umich.edu 29178007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RDVAL_ENTRY) 29188007Ssaidi@eecs.umich.eduCall_Pal_Rdval: 29198007Ssaidi@eecs.umich.edu nop 29208007Ssaidi@eecs.umich.edu mfpr r0, pt_sysval 29218007Ssaidi@eecs.umich.edu nop 29228007Ssaidi@eecs.umich.edu hw_rei 29238007Ssaidi@eecs.umich.edu 29248013Sbinkertn@umich.edu// 29258013Sbinkertn@umich.edu// tbi - PALcode for tbi instruction 29268007Ssaidi@eecs.umich.edu// 29278007Ssaidi@eecs.umich.edu// Entry: 29288007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 29298007Ssaidi@eecs.umich.edu// 29308007Ssaidi@eecs.umich.edu// Function: 29318007Ssaidi@eecs.umich.edu// TB invalidate 29328007Ssaidi@eecs.umich.edu// r16/a0 = TBI type 29338007Ssaidi@eecs.umich.edu// r17/a1 = Va for TBISx instructions 29348013Sbinkertn@umich.edu// 29358007Ssaidi@eecs.umich.edu 29368007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_TBI_ENTRY) 29378007Ssaidi@eecs.umich.eduCall_Pal_Tbi: 29388007Ssaidi@eecs.umich.edu addq r16, 2, r16 // change range to 0-2 29398007Ssaidi@eecs.umich.edu br r23, CALL_PAL_tbi_10_ // get our address 29408007Ssaidi@eecs.umich.edu 29418007Ssaidi@eecs.umich.eduCALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range 29428007Ssaidi@eecs.umich.edu lda r23, tbi_tbl-CALL_PAL_tbi_10_(r23) // set base to start of table 29438007Ssaidi@eecs.umich.edu sll r16, 4, r16 // * 16 29448007Ssaidi@eecs.umich.edu blbc r22, CALL_PAL_tbi_30_ // go rei, if not 29458007Ssaidi@eecs.umich.edu 29468007Ssaidi@eecs.umich.edu addq r23, r16, r23 // addr of our code 29478007Ssaidi@eecs.umich.edu//orig pvc_jsr tbi 29488007Ssaidi@eecs.umich.edu jmp r31, (r23) // and go do it 29498007Ssaidi@eecs.umich.edu 29508007Ssaidi@eecs.umich.eduCALL_PAL_tbi_30_: 29518007Ssaidi@eecs.umich.edu hw_rei 29528007Ssaidi@eecs.umich.edu nop 29538007Ssaidi@eecs.umich.edu 29548013Sbinkertn@umich.edu// 29558013Sbinkertn@umich.edu// wrent - PALcode for wrent instruction 29568007Ssaidi@eecs.umich.edu// 29578007Ssaidi@eecs.umich.edu// Entry: 29588007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 29598007Ssaidi@eecs.umich.edu// 29608007Ssaidi@eecs.umich.edu// Function: 29618007Ssaidi@eecs.umich.edu// Update ent* in paltemps 29628007Ssaidi@eecs.umich.edu// r16/a0 = Address of entry routine 29638007Ssaidi@eecs.umich.edu// r17/a1 = Entry Number 0..5 29648007Ssaidi@eecs.umich.edu// 29658007Ssaidi@eecs.umich.edu// r22, r23 trashed 29668013Sbinkertn@umich.edu// 29678007Ssaidi@eecs.umich.edu 29688007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRENT_ENTRY) 29698007Ssaidi@eecs.umich.eduCall_Pal_Wrent: 29708007Ssaidi@eecs.umich.edu cmpult r17, 6, r22 // see if in range 29718007Ssaidi@eecs.umich.edu br r23, CALL_PAL_wrent_10_ // get our address 29728007Ssaidi@eecs.umich.edu 29738007Ssaidi@eecs.umich.eduCALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc 29748007Ssaidi@eecs.umich.edu blbc r22, CALL_PAL_wrent_30_ // go rei, if not in range 29758007Ssaidi@eecs.umich.edu 29768007Ssaidi@eecs.umich.edu lda r23, wrent_tbl-CALL_PAL_wrent_10_(r23) // set base to start of table 29778007Ssaidi@eecs.umich.edu sll r17, 4, r17 // *16 29788007Ssaidi@eecs.umich.edu 29798007Ssaidi@eecs.umich.edu addq r17, r23, r23 // Get address in table 29808007Ssaidi@eecs.umich.edu//orig pvc_jsr wrent 29818007Ssaidi@eecs.umich.edu jmp r31, (r23) // and go do it 29828007Ssaidi@eecs.umich.edu 29838007Ssaidi@eecs.umich.eduCALL_PAL_wrent_30_: 29848007Ssaidi@eecs.umich.edu hw_rei // out of range, just return 29858007Ssaidi@eecs.umich.edu 29868013Sbinkertn@umich.edu// 29878013Sbinkertn@umich.edu// swpipl - PALcode for swpipl instruction 29888007Ssaidi@eecs.umich.edu// 29898007Ssaidi@eecs.umich.edu// Entry: 29908007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 29918007Ssaidi@eecs.umich.edu// 29928007Ssaidi@eecs.umich.edu// Function: 29938007Ssaidi@eecs.umich.edu// v0 (r0) <- PS<IPL> 29948007Ssaidi@eecs.umich.edu// PS<IPL> <- a0<2:0> (r16) 29958007Ssaidi@eecs.umich.edu// 29968007Ssaidi@eecs.umich.edu// t8 (r22) is scratch 29978013Sbinkertn@umich.edu// 29988007Ssaidi@eecs.umich.edu 29998007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_SWPIPL_ENTRY) 30008007Ssaidi@eecs.umich.eduCall_Pal_Swpipl: 30018007Ssaidi@eecs.umich.edu and r16, osfps_m_ipl, r16 // clean New ipl 30028007Ssaidi@eecs.umich.edu mfpr r22, pt_intmask // get int mask 30038007Ssaidi@eecs.umich.edu 30048007Ssaidi@eecs.umich.edu extbl r22, r16, r22 // get mask for this ipl 30058007Ssaidi@eecs.umich.edu bis r11, r31, r0 // return old ipl 30068007Ssaidi@eecs.umich.edu 30078007Ssaidi@eecs.umich.edu bis r16, r31, r11 // set new ps 30088007Ssaidi@eecs.umich.edu mtpr r22, ev5__ipl // set new mask 30098007Ssaidi@eecs.umich.edu 30108007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad ipl write 30118007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad ipl write 30128007Ssaidi@eecs.umich.edu 30138007Ssaidi@eecs.umich.edu hw_rei // back 30148007Ssaidi@eecs.umich.edu 30158013Sbinkertn@umich.edu// 30168013Sbinkertn@umich.edu// rdps - PALcode for rdps instruction 30178007Ssaidi@eecs.umich.edu// 30188007Ssaidi@eecs.umich.edu// Entry: 30198007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 30208007Ssaidi@eecs.umich.edu// 30218007Ssaidi@eecs.umich.edu// Function: 30228007Ssaidi@eecs.umich.edu// v0 (r0) <- ps 30238013Sbinkertn@umich.edu// 30248007Ssaidi@eecs.umich.edu 30258007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RDPS_ENTRY) 30268007Ssaidi@eecs.umich.eduCall_Pal_Rdps: 30278007Ssaidi@eecs.umich.edu bis r11, r31, r0 // Fetch PALshadow PS 30288007Ssaidi@eecs.umich.edu nop // Must be 2 cycles long 30298007Ssaidi@eecs.umich.edu hw_rei 30308007Ssaidi@eecs.umich.edu 30318013Sbinkertn@umich.edu// 30328013Sbinkertn@umich.edu// wrkgp - PALcode for wrkgp instruction 30338007Ssaidi@eecs.umich.edu// 30348007Ssaidi@eecs.umich.edu// Entry: 30358007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 30368007Ssaidi@eecs.umich.edu// 30378007Ssaidi@eecs.umich.edu// Function: 30388007Ssaidi@eecs.umich.edu// kgp <- a0 (r16) 30398013Sbinkertn@umich.edu// 30408007Ssaidi@eecs.umich.edu 30418007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRKGP_ENTRY) 30428007Ssaidi@eecs.umich.eduCall_Pal_Wrkgp: 30438007Ssaidi@eecs.umich.edu nop 30448007Ssaidi@eecs.umich.edu mtpr r16, pt_kgp 30458007Ssaidi@eecs.umich.edu nop // Pad for pt write->read restriction 30468007Ssaidi@eecs.umich.edu nop 30478007Ssaidi@eecs.umich.edu hw_rei 30488007Ssaidi@eecs.umich.edu 30498013Sbinkertn@umich.edu// 30508013Sbinkertn@umich.edu// wrusp - PALcode for wrusp instruction 30518007Ssaidi@eecs.umich.edu// 30528007Ssaidi@eecs.umich.edu// Entry: 30538007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 30548007Ssaidi@eecs.umich.edu// 30558007Ssaidi@eecs.umich.edu// Function: 30568007Ssaidi@eecs.umich.edu// usp <- a0 (r16) 30578013Sbinkertn@umich.edu// 30588007Ssaidi@eecs.umich.edu 30598007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WRUSP_ENTRY) 30608007Ssaidi@eecs.umich.eduCall_Pal_Wrusp: 30618007Ssaidi@eecs.umich.edu nop 30628007Ssaidi@eecs.umich.edu mtpr r16, pt_usp 30638007Ssaidi@eecs.umich.edu nop // Pad possible pt write->read restriction 30648007Ssaidi@eecs.umich.edu nop 30658007Ssaidi@eecs.umich.edu hw_rei 30668007Ssaidi@eecs.umich.edu 30678013Sbinkertn@umich.edu// 30688013Sbinkertn@umich.edu// wrperfmon - PALcode for wrperfmon instruction 30698007Ssaidi@eecs.umich.edu// 30708007Ssaidi@eecs.umich.edu// Entry: 30718007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 30728007Ssaidi@eecs.umich.edu// 30738007Ssaidi@eecs.umich.edu// 30748007Ssaidi@eecs.umich.edu// Function: 30758007Ssaidi@eecs.umich.edu// Various control functions for the onchip performance counters 30768007Ssaidi@eecs.umich.edu// 30778007Ssaidi@eecs.umich.edu// option selector in r16 30788007Ssaidi@eecs.umich.edu// option argument in r17 30798007Ssaidi@eecs.umich.edu// returned status in r0 30808007Ssaidi@eecs.umich.edu// 30818007Ssaidi@eecs.umich.edu// 30828007Ssaidi@eecs.umich.edu// r16 = 0 Disable performance monitoring for one or more cpu's 30838007Ssaidi@eecs.umich.edu// r17 = 0 disable no counters 30848007Ssaidi@eecs.umich.edu// r17 = bitmask disable counters specified in bit mask (1=disable) 30858007Ssaidi@eecs.umich.edu// 30868007Ssaidi@eecs.umich.edu// r16 = 1 Enable performance monitoring for one or more cpu's 30878007Ssaidi@eecs.umich.edu// r17 = 0 enable no counters 30888007Ssaidi@eecs.umich.edu// r17 = bitmask enable counters specified in bit mask (1=enable) 30898007Ssaidi@eecs.umich.edu// 30908007Ssaidi@eecs.umich.edu// r16 = 2 Mux select for one or more cpu's 30918007Ssaidi@eecs.umich.edu// r17 = Mux selection (cpu specific) 30928007Ssaidi@eecs.umich.edu// <24:19> bc_ctl<pm_mux_sel> field (see spec) 30938007Ssaidi@eecs.umich.edu// <31>,<7:4>,<3:0> pmctr <sel0>,<sel1>,<sel2> fields (see spec) 30948007Ssaidi@eecs.umich.edu// 30958007Ssaidi@eecs.umich.edu// r16 = 3 Options 30968007Ssaidi@eecs.umich.edu// r17 = (cpu specific) 30978007Ssaidi@eecs.umich.edu// <0> = 0 log all processes 30988007Ssaidi@eecs.umich.edu// <0> = 1 log only selected processes 30998007Ssaidi@eecs.umich.edu// <30,9,8> mode select - ku,kp,kk 31008007Ssaidi@eecs.umich.edu// 31018007Ssaidi@eecs.umich.edu// r16 = 4 Interrupt frequency select 31028007Ssaidi@eecs.umich.edu// r17 = (cpu specific) indicates interrupt frequencies desired for each 31038007Ssaidi@eecs.umich.edu// counter, with "zero interrupts" being an option 31048007Ssaidi@eecs.umich.edu// frequency info in r17 bits as defined by PMCTR_CTL<FRQx> below 31058007Ssaidi@eecs.umich.edu// 31068007Ssaidi@eecs.umich.edu// r16 = 5 Read Counters 31078007Ssaidi@eecs.umich.edu// r17 = na 31088007Ssaidi@eecs.umich.edu// r0 = value (same format as ev5 pmctr) 31098007Ssaidi@eecs.umich.edu// <0> = 0 Read failed 31108007Ssaidi@eecs.umich.edu// <0> = 1 Read succeeded 31118007Ssaidi@eecs.umich.edu// 31128007Ssaidi@eecs.umich.edu// r16 = 6 Write Counters 31138007Ssaidi@eecs.umich.edu// r17 = value (same format as ev5 pmctr; all counters written simultaneously) 31148007Ssaidi@eecs.umich.edu// 31158007Ssaidi@eecs.umich.edu// r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0 31168007Ssaidi@eecs.umich.edu// r17 = 0 enable no counters 31178007Ssaidi@eecs.umich.edu// r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear) 31188007Ssaidi@eecs.umich.edu// 31198007Ssaidi@eecs.umich.edu//============================================================================= 31208007Ssaidi@eecs.umich.edu//Assumptions: 31218007Ssaidi@eecs.umich.edu//PMCTR_CTL: 31228007Ssaidi@eecs.umich.edu// 31238007Ssaidi@eecs.umich.edu// <15:14> CTL0 -- encoded frequency select and enable - CTR0 31248007Ssaidi@eecs.umich.edu// <13:12> CTL1 -- " - CTR1 31258007Ssaidi@eecs.umich.edu// <11:10> CTL2 -- " - CTR2 31268007Ssaidi@eecs.umich.edu// 31278007Ssaidi@eecs.umich.edu// <9:8> FRQ0 -- frequency select for CTR0 (no enable info) 31288007Ssaidi@eecs.umich.edu// <7:6> FRQ1 -- frequency select for CTR1 31298007Ssaidi@eecs.umich.edu// <5:4> FRQ2 -- frequency select for CTR2 31308007Ssaidi@eecs.umich.edu// 31318007Ssaidi@eecs.umich.edu// <0> all vs. select processes (0=all,1=select) 31328007Ssaidi@eecs.umich.edu// 31338007Ssaidi@eecs.umich.edu// where 31348007Ssaidi@eecs.umich.edu// FRQx<1:0> 31358007Ssaidi@eecs.umich.edu// 0 1 disable interrupt 31368007Ssaidi@eecs.umich.edu// 1 0 frequency = 65536 (16384 for ctr2) 31378007Ssaidi@eecs.umich.edu// 1 1 frequency = 256 31388007Ssaidi@eecs.umich.edu// note: FRQx<1:0> = 00 will keep counters from ever being enabled. 31398007Ssaidi@eecs.umich.edu// 31408007Ssaidi@eecs.umich.edu//============================================================================= 31418007Ssaidi@eecs.umich.edu// 31428007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x0039) 31438007Ssaidi@eecs.umich.edu// unsupported in Hudson code .. pboyle Nov/95 31448007Ssaidi@eecs.umich.eduCALL_PAL_Wrperfmon: 31458007Ssaidi@eecs.umich.edu // "real" performance monitoring code 31468007Ssaidi@eecs.umich.edu cmpeq r16, 1, r0 // check for enable 31478007Ssaidi@eecs.umich.edu bne r0, perfmon_en // br if requested to enable 31488007Ssaidi@eecs.umich.edu 31498007Ssaidi@eecs.umich.edu cmpeq r16, 2, r0 // check for mux ctl 31508007Ssaidi@eecs.umich.edu bne r0, perfmon_muxctl // br if request to set mux controls 31518007Ssaidi@eecs.umich.edu 31528007Ssaidi@eecs.umich.edu cmpeq r16, 3, r0 // check for options 31538007Ssaidi@eecs.umich.edu bne r0, perfmon_ctl // br if request to set options 31548007Ssaidi@eecs.umich.edu 31558007Ssaidi@eecs.umich.edu cmpeq r16, 4, r0 // check for interrupt frequency select 31568007Ssaidi@eecs.umich.edu bne r0, perfmon_freq // br if request to change frequency select 31578007Ssaidi@eecs.umich.edu 31588007Ssaidi@eecs.umich.edu cmpeq r16, 5, r0 // check for counter read request 31598007Ssaidi@eecs.umich.edu bne r0, perfmon_rd // br if request to read counters 31608007Ssaidi@eecs.umich.edu 31618007Ssaidi@eecs.umich.edu cmpeq r16, 6, r0 // check for counter write request 31628007Ssaidi@eecs.umich.edu bne r0, perfmon_wr // br if request to write counters 31638007Ssaidi@eecs.umich.edu 31648007Ssaidi@eecs.umich.edu cmpeq r16, 7, r0 // check for counter clear/enable request 31658007Ssaidi@eecs.umich.edu bne r0, perfmon_enclr // br if request to clear/enable counters 31668007Ssaidi@eecs.umich.edu 31678007Ssaidi@eecs.umich.edu beq r16, perfmon_dis // br if requested to disable (r16=0) 31688007Ssaidi@eecs.umich.edu br r31, perfmon_unknown // br if unknown request 31698013Sbinkertn@umich.edu 31708013Sbinkertn@umich.edu// 31718013Sbinkertn@umich.edu// rdusp - PALcode for rdusp instruction 31728007Ssaidi@eecs.umich.edu// 31738007Ssaidi@eecs.umich.edu// Entry: 31748007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 31758007Ssaidi@eecs.umich.edu// 31768007Ssaidi@eecs.umich.edu// Function: 31778007Ssaidi@eecs.umich.edu// v0 (r0) <- usp 31788013Sbinkertn@umich.edu// 31798007Ssaidi@eecs.umich.edu 31808007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RDUSP_ENTRY) 31818007Ssaidi@eecs.umich.eduCall_Pal_Rdusp: 31828007Ssaidi@eecs.umich.edu nop 31838007Ssaidi@eecs.umich.edu mfpr r0, pt_usp 31848007Ssaidi@eecs.umich.edu hw_rei 31858007Ssaidi@eecs.umich.edu 31868007Ssaidi@eecs.umich.edu 31878007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x003B) 31888007Ssaidi@eecs.umich.eduCallPal_OpcDec3B: 31898007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 31908007Ssaidi@eecs.umich.edu 31918013Sbinkertn@umich.edu// 31928013Sbinkertn@umich.edu// whami - PALcode for whami instruction 31938007Ssaidi@eecs.umich.edu// 31948007Ssaidi@eecs.umich.edu// Entry: 31958007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 31968007Ssaidi@eecs.umich.edu// 31978007Ssaidi@eecs.umich.edu// Function: 31988007Ssaidi@eecs.umich.edu// v0 (r0) <- whami 31998013Sbinkertn@umich.edu// 32008007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_WHAMI_ENTRY) 32018007Ssaidi@eecs.umich.eduCall_Pal_Whami: 32028007Ssaidi@eecs.umich.edu nop 32038007Ssaidi@eecs.umich.edu mfpr r0, pt_whami // Get Whami 32048007Ssaidi@eecs.umich.edu extbl r0, 1, r0 // Isolate just whami bits 32058007Ssaidi@eecs.umich.edu hw_rei 32068007Ssaidi@eecs.umich.edu 32078013Sbinkertn@umich.edu// 32088013Sbinkertn@umich.edu// retsys - PALcode for retsys instruction 32098007Ssaidi@eecs.umich.edu// 32108007Ssaidi@eecs.umich.edu// Entry: 32118007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 32128007Ssaidi@eecs.umich.edu// 00(sp) contains return pc 32138007Ssaidi@eecs.umich.edu// 08(sp) contains r29 32148007Ssaidi@eecs.umich.edu// 32158007Ssaidi@eecs.umich.edu// Function: 32168007Ssaidi@eecs.umich.edu// Return from system call. 32178007Ssaidi@eecs.umich.edu// mode switched from kern to user. 32188007Ssaidi@eecs.umich.edu// stacks swapped, ugp, upc restored. 32198007Ssaidi@eecs.umich.edu// r23, r25 junked 32208013Sbinkertn@umich.edu// 32218007Ssaidi@eecs.umich.edu 32228007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RETSYS_ENTRY) 32238007Ssaidi@eecs.umich.eduCall_Pal_Retsys: 32248007Ssaidi@eecs.umich.edu lda r25, osfsf_c_size(sp) // pop stack 32258007Ssaidi@eecs.umich.edu bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr 32268007Ssaidi@eecs.umich.edu 32278007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // save exc_addr in case of fault 32288007Ssaidi@eecs.umich.edu ldq r23, osfsf_pc(sp) // get pc 32298007Ssaidi@eecs.umich.edu 32308007Ssaidi@eecs.umich.edu ldq r29, osfsf_gp(sp) // get gp 32318007Ssaidi@eecs.umich.edu stl_c r31, -4(sp) // clear lock_flag 32328007Ssaidi@eecs.umich.edu 32338007Ssaidi@eecs.umich.edu lda r11, 1<<osfps_v_mode(r31)// new PS:mode=user 32348007Ssaidi@eecs.umich.edu mfpr r30, pt_usp // get users stack 32358007Ssaidi@eecs.umich.edu 32368007Ssaidi@eecs.umich.edu bic r23, 3, r23 // clean return pc 32378007Ssaidi@eecs.umich.edu mtpr r31, ev5__ipl // zero ibox IPL - 2 bubbles to hw_rei 32388007Ssaidi@eecs.umich.edu 32398007Ssaidi@eecs.umich.edu mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 32408007Ssaidi@eecs.umich.edu mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 32418007Ssaidi@eecs.umich.edu 32428007Ssaidi@eecs.umich.edu mtpr r23, exc_addr // set return address - 1 bubble to hw_rei 32438007Ssaidi@eecs.umich.edu mtpr r25, pt_ksp // save kern stack 32448007Ssaidi@eecs.umich.edu 32458007Ssaidi@eecs.umich.edu rc r31 // clear inter_flag 32468007Ssaidi@eecs.umich.edu// pvc_violate 248 // possible hidden mt->mf pt violation ok in callpal 32478007Ssaidi@eecs.umich.edu hw_rei_spe // and back 32488007Ssaidi@eecs.umich.edu 32498007Ssaidi@eecs.umich.edu 32508007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(0x003E) 32518007Ssaidi@eecs.umich.eduCallPal_OpcDec3E: 32528007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 32538007Ssaidi@eecs.umich.edu 32548013Sbinkertn@umich.edu// 32558013Sbinkertn@umich.edu// rti - PALcode for rti instruction 32568007Ssaidi@eecs.umich.edu// 32578007Ssaidi@eecs.umich.edu// Entry: 32588007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 32598007Ssaidi@eecs.umich.edu// 32608007Ssaidi@eecs.umich.edu// Function: 32618007Ssaidi@eecs.umich.edu// 00(sp) -> ps 32628007Ssaidi@eecs.umich.edu// 08(sp) -> pc 32638007Ssaidi@eecs.umich.edu// 16(sp) -> r29 (gp) 32648007Ssaidi@eecs.umich.edu// 24(sp) -> r16 (a0) 32658007Ssaidi@eecs.umich.edu// 32(sp) -> r17 (a1) 32668007Ssaidi@eecs.umich.edu// 40(sp) -> r18 (a3) 32678013Sbinkertn@umich.edu// 32688007Ssaidi@eecs.umich.edu 32698007Ssaidi@eecs.umich.edu CALL_PAL_PRIV(PAL_RTI_ENTRY) 32708007Ssaidi@eecs.umich.edu /* called once by platform_tlaser */ 32718007Ssaidi@eecs.umich.edu .globl Call_Pal_Rti 32728007Ssaidi@eecs.umich.eduCall_Pal_Rti: 32738007Ssaidi@eecs.umich.edu lda r25, osfsf_c_size(sp) // get updated sp 32748007Ssaidi@eecs.umich.edu bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr 32758007Ssaidi@eecs.umich.edu 32768007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // save PC in case of fault 32778007Ssaidi@eecs.umich.edu rc r31 // clear intr_flag 32788007Ssaidi@eecs.umich.edu 32798007Ssaidi@eecs.umich.edu ldq r12, -6*8(r25) // get ps 32808007Ssaidi@eecs.umich.edu ldq r13, -5*8(r25) // pc 32818007Ssaidi@eecs.umich.edu 32828007Ssaidi@eecs.umich.edu ldq r18, -1*8(r25) // a2 32838007Ssaidi@eecs.umich.edu ldq r17, -2*8(r25) // a1 32848007Ssaidi@eecs.umich.edu 32858007Ssaidi@eecs.umich.edu ldq r16, -3*8(r25) // a0 32868007Ssaidi@eecs.umich.edu ldq r29, -4*8(r25) // gp 32878007Ssaidi@eecs.umich.edu 32888007Ssaidi@eecs.umich.edu bic r13, 3, r13 // clean return pc 32898007Ssaidi@eecs.umich.edu stl_c r31, -4(r25) // clear lock_flag 32908007Ssaidi@eecs.umich.edu 32918007Ssaidi@eecs.umich.edu and r12, osfps_m_mode, r11 // get mode 32928007Ssaidi@eecs.umich.edu mtpr r13, exc_addr // set return address 32938007Ssaidi@eecs.umich.edu 32948007Ssaidi@eecs.umich.edu beq r11, rti_to_kern // br if rti to Kern 32958007Ssaidi@eecs.umich.edu br r31, rti_to_user // out of call_pal space 32968007Ssaidi@eecs.umich.edu 32978007Ssaidi@eecs.umich.edu 32988013Sbinkertn@umich.edu/////////////////////////////////////////////////// 32998013Sbinkertn@umich.edu// Start the Unprivileged CALL_PAL Entry Points 33008013Sbinkertn@umich.edu/////////////////////////////////////////////////// 33018013Sbinkertn@umich.edu 33028013Sbinkertn@umich.edu// 33038013Sbinkertn@umich.edu// bpt - PALcode for bpt instruction 33048007Ssaidi@eecs.umich.edu// 33058007Ssaidi@eecs.umich.edu// Entry: 33068007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 33078007Ssaidi@eecs.umich.edu// 33088007Ssaidi@eecs.umich.edu// Function: 33098007Ssaidi@eecs.umich.edu// Build stack frame 33108007Ssaidi@eecs.umich.edu// a0 <- code 33118007Ssaidi@eecs.umich.edu// a1 <- unpred 33128007Ssaidi@eecs.umich.edu// a2 <- unpred 33138007Ssaidi@eecs.umich.edu// vector via entIF 33148007Ssaidi@eecs.umich.edu// 33158013Sbinkertn@umich.edu// 33168007Ssaidi@eecs.umich.edu// 33178007Ssaidi@eecs.umich.edu .text 1 33188007Ssaidi@eecs.umich.edu// . = 0x3000 33198007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_BPT_ENTRY) 33208007Ssaidi@eecs.umich.eduCall_Pal_Bpt: 33218007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 33228007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 33238007Ssaidi@eecs.umich.edu 33248007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 33258007Ssaidi@eecs.umich.edu bge r25, CALL_PAL_bpt_10_ // no stack swap needed if cm=kern 33268007Ssaidi@eecs.umich.edu 33278007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 33288007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 33298007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 33308007Ssaidi@eecs.umich.edu 33318007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 33328007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 33338007Ssaidi@eecs.umich.edu 33348007Ssaidi@eecs.umich.eduCALL_PAL_bpt_10_: 33358007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 33368007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 33378007Ssaidi@eecs.umich.edu 33388007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 33398007Ssaidi@eecs.umich.edu bis r31, osf_a0_bpt, r16 // set a0 33408007Ssaidi@eecs.umich.edu 33418007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 33428007Ssaidi@eecs.umich.edu br r31, bpt_bchk_common // out of call_pal space 33438007Ssaidi@eecs.umich.edu 33448007Ssaidi@eecs.umich.edu 33458013Sbinkertn@umich.edu// 33468013Sbinkertn@umich.edu// bugchk - PALcode for bugchk instruction 33478007Ssaidi@eecs.umich.edu// 33488007Ssaidi@eecs.umich.edu// Entry: 33498007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 33508007Ssaidi@eecs.umich.edu// 33518007Ssaidi@eecs.umich.edu// Function: 33528007Ssaidi@eecs.umich.edu// Build stack frame 33538007Ssaidi@eecs.umich.edu// a0 <- code 33548007Ssaidi@eecs.umich.edu// a1 <- unpred 33558007Ssaidi@eecs.umich.edu// a2 <- unpred 33568007Ssaidi@eecs.umich.edu// vector via entIF 33578007Ssaidi@eecs.umich.edu// 33588013Sbinkertn@umich.edu// 33598007Ssaidi@eecs.umich.edu// 33608007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY) 33618007Ssaidi@eecs.umich.eduCall_Pal_Bugchk: 33628007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 33638007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 33648007Ssaidi@eecs.umich.edu 33658007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 33668007Ssaidi@eecs.umich.edu bge r25, CALL_PAL_bugchk_10_ // no stack swap needed if cm=kern 33678007Ssaidi@eecs.umich.edu 33688007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 33698007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 33708007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 33718007Ssaidi@eecs.umich.edu 33728007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 33738007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 33748007Ssaidi@eecs.umich.edu 33758007Ssaidi@eecs.umich.eduCALL_PAL_bugchk_10_: 33768007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 33778007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 33788007Ssaidi@eecs.umich.edu 33798007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 33808007Ssaidi@eecs.umich.edu bis r31, osf_a0_bugchk, r16 // set a0 33818007Ssaidi@eecs.umich.edu 33828007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 33838007Ssaidi@eecs.umich.edu br r31, bpt_bchk_common // out of call_pal space 33848007Ssaidi@eecs.umich.edu 33858007Ssaidi@eecs.umich.edu 33868007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0082) 33878007Ssaidi@eecs.umich.eduCallPal_OpcDec82: 33888007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 33898007Ssaidi@eecs.umich.edu 33908013Sbinkertn@umich.edu// 33918013Sbinkertn@umich.edu// callsys - PALcode for callsys instruction 33928007Ssaidi@eecs.umich.edu// 33938007Ssaidi@eecs.umich.edu// Entry: 33948007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 33958007Ssaidi@eecs.umich.edu// 33968007Ssaidi@eecs.umich.edu// Function: 33978007Ssaidi@eecs.umich.edu// Switch mode to kernel and build a callsys stack frame. 33988007Ssaidi@eecs.umich.edu// sp = ksp 33998007Ssaidi@eecs.umich.edu// gp = kgp 34008007Ssaidi@eecs.umich.edu// t8 - t10 (r22-r24) trashed 34018007Ssaidi@eecs.umich.edu// 34028013Sbinkertn@umich.edu// 34038007Ssaidi@eecs.umich.edu// 34048007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY) 34058007Ssaidi@eecs.umich.eduCall_Pal_Callsys: 34068007Ssaidi@eecs.umich.edu 34078007Ssaidi@eecs.umich.edu and r11, osfps_m_mode, r24 // get mode 34088007Ssaidi@eecs.umich.edu mfpr r22, pt_ksp // get ksp 34098007Ssaidi@eecs.umich.edu 34108007Ssaidi@eecs.umich.edu beq r24, sys_from_kern // sysCall from kern is not allowed 34118007Ssaidi@eecs.umich.edu mfpr r12, pt_entsys // get address of callSys routine 34128007Ssaidi@eecs.umich.edu 34138013Sbinkertn@umich.edu// 34148007Ssaidi@eecs.umich.edu// from here on we know we are in user going to Kern 34158013Sbinkertn@umich.edu// 34168007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles 34178007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei 34188007Ssaidi@eecs.umich.edu 34198007Ssaidi@eecs.umich.edu bis r31, r31, r11 // PS=0 (mode=kern) 34208007Ssaidi@eecs.umich.edu mfpr r23, exc_addr // get pc 34218007Ssaidi@eecs.umich.edu 34228007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save usp 34238007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(r22)// set new sp 34248007Ssaidi@eecs.umich.edu 34258007Ssaidi@eecs.umich.edu stq r29, osfsf_gp(sp) // save user gp/r29 34268007Ssaidi@eecs.umich.edu stq r24, osfsf_ps(sp) // save ps 34278007Ssaidi@eecs.umich.edu 34288007Ssaidi@eecs.umich.edu stq r23, osfsf_pc(sp) // save pc 34298007Ssaidi@eecs.umich.edu mtpr r12, exc_addr // set address 34308007Ssaidi@eecs.umich.edu // 1 cycle to hw_rei 34318007Ssaidi@eecs.umich.edu 34328007Ssaidi@eecs.umich.edu mfpr r29, pt_kgp // get the kern gp/r29 34338007Ssaidi@eecs.umich.edu 34348007Ssaidi@eecs.umich.edu hw_rei_spe // and off we go! 34358007Ssaidi@eecs.umich.edu 34368007Ssaidi@eecs.umich.edu 34378007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0084) 34388007Ssaidi@eecs.umich.eduCallPal_OpcDec84: 34398007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34408007Ssaidi@eecs.umich.edu 34418007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0085) 34428007Ssaidi@eecs.umich.eduCallPal_OpcDec85: 34438007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34448007Ssaidi@eecs.umich.edu 34458013Sbinkertn@umich.edu// 34468013Sbinkertn@umich.edu// imb - PALcode for imb instruction 34478007Ssaidi@eecs.umich.edu// 34488007Ssaidi@eecs.umich.edu// Entry: 34498007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 34508007Ssaidi@eecs.umich.edu// 34518007Ssaidi@eecs.umich.edu// Function: 34528007Ssaidi@eecs.umich.edu// Flush the writebuffer and flush the Icache 34538007Ssaidi@eecs.umich.edu// 34548013Sbinkertn@umich.edu// 34558007Ssaidi@eecs.umich.edu// 34568007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_IMB_ENTRY) 34578007Ssaidi@eecs.umich.eduCall_Pal_Imb: 34588007Ssaidi@eecs.umich.edu mb // Clear the writebuffer 34598007Ssaidi@eecs.umich.edu mfpr r31, ev5__mcsr // Sync with clear 34608007Ssaidi@eecs.umich.edu nop 34618007Ssaidi@eecs.umich.edu nop 34628007Ssaidi@eecs.umich.edu br r31, pal_ic_flush // Flush Icache 34638007Ssaidi@eecs.umich.edu 34648007Ssaidi@eecs.umich.edu 34658013Sbinkertn@umich.edu// CALL_PAL OPCDECs 34668007Ssaidi@eecs.umich.edu 34678007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0087) 34688007Ssaidi@eecs.umich.eduCallPal_OpcDec87: 34698007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34708007Ssaidi@eecs.umich.edu 34718007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0088) 34728007Ssaidi@eecs.umich.eduCallPal_OpcDec88: 34738007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34748007Ssaidi@eecs.umich.edu 34758007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0089) 34768007Ssaidi@eecs.umich.eduCallPal_OpcDec89: 34778007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34788007Ssaidi@eecs.umich.edu 34798007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008A) 34808007Ssaidi@eecs.umich.eduCallPal_OpcDec8A: 34818007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34828007Ssaidi@eecs.umich.edu 34838007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008B) 34848007Ssaidi@eecs.umich.eduCallPal_OpcDec8B: 34858007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34868007Ssaidi@eecs.umich.edu 34878007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008C) 34888007Ssaidi@eecs.umich.eduCallPal_OpcDec8C: 34898007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34908007Ssaidi@eecs.umich.edu 34918007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008D) 34928007Ssaidi@eecs.umich.eduCallPal_OpcDec8D: 34938007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34948007Ssaidi@eecs.umich.edu 34958007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008E) 34968007Ssaidi@eecs.umich.eduCallPal_OpcDec8E: 34978007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 34988007Ssaidi@eecs.umich.edu 34998007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x008F) 35008007Ssaidi@eecs.umich.eduCallPal_OpcDec8F: 35018007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35028007Ssaidi@eecs.umich.edu 35038007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0090) 35048007Ssaidi@eecs.umich.eduCallPal_OpcDec90: 35058007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35068007Ssaidi@eecs.umich.edu 35078007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0091) 35088007Ssaidi@eecs.umich.eduCallPal_OpcDec91: 35098007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35108007Ssaidi@eecs.umich.edu 35118007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0092) 35128007Ssaidi@eecs.umich.eduCallPal_OpcDec92: 35138007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35148007Ssaidi@eecs.umich.edu 35158007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0093) 35168007Ssaidi@eecs.umich.eduCallPal_OpcDec93: 35178007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35188007Ssaidi@eecs.umich.edu 35198007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0094) 35208007Ssaidi@eecs.umich.eduCallPal_OpcDec94: 35218007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35228007Ssaidi@eecs.umich.edu 35238007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0095) 35248007Ssaidi@eecs.umich.eduCallPal_OpcDec95: 35258007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35268007Ssaidi@eecs.umich.edu 35278007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0096) 35288007Ssaidi@eecs.umich.eduCallPal_OpcDec96: 35298007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35308007Ssaidi@eecs.umich.edu 35318007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0097) 35328007Ssaidi@eecs.umich.eduCallPal_OpcDec97: 35338007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35348007Ssaidi@eecs.umich.edu 35358007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0098) 35368007Ssaidi@eecs.umich.eduCallPal_OpcDec98: 35378007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35388007Ssaidi@eecs.umich.edu 35398007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x0099) 35408007Ssaidi@eecs.umich.eduCallPal_OpcDec99: 35418007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35428007Ssaidi@eecs.umich.edu 35438007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x009A) 35448007Ssaidi@eecs.umich.eduCallPal_OpcDec9A: 35458007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35468007Ssaidi@eecs.umich.edu 35478007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x009B) 35488007Ssaidi@eecs.umich.eduCallPal_OpcDec9B: 35498007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35508007Ssaidi@eecs.umich.edu 35518007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x009C) 35528007Ssaidi@eecs.umich.eduCallPal_OpcDec9C: 35538007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35548007Ssaidi@eecs.umich.edu 35558007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x009D) 35568007Ssaidi@eecs.umich.eduCallPal_OpcDec9D: 35578007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 35588007Ssaidi@eecs.umich.edu 35598013Sbinkertn@umich.edu// 35608013Sbinkertn@umich.edu// rdunique - PALcode for rdunique instruction 35618007Ssaidi@eecs.umich.edu// 35628007Ssaidi@eecs.umich.edu// Entry: 35638007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 35648007Ssaidi@eecs.umich.edu// 35658007Ssaidi@eecs.umich.edu// Function: 35668007Ssaidi@eecs.umich.edu// v0 (r0) <- unique 35678007Ssaidi@eecs.umich.edu// 35688013Sbinkertn@umich.edu// 35698007Ssaidi@eecs.umich.edu// 35708007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY) 35718007Ssaidi@eecs.umich.eduCALL_PALrdunique_: 35728007Ssaidi@eecs.umich.edu mfpr r0, pt_pcbb // get pcb pointer 35738013Sbinkertn@umich.edu ldq_p r0, osfpcb_q_unique(r0) // get new value 35748007Ssaidi@eecs.umich.edu 35758007Ssaidi@eecs.umich.edu hw_rei 35768007Ssaidi@eecs.umich.edu 35778013Sbinkertn@umich.edu// 35788013Sbinkertn@umich.edu// wrunique - PALcode for wrunique instruction 35798007Ssaidi@eecs.umich.edu// 35808007Ssaidi@eecs.umich.edu// Entry: 35818007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 35828007Ssaidi@eecs.umich.edu// 35838007Ssaidi@eecs.umich.edu// Function: 35848007Ssaidi@eecs.umich.edu// unique <- a0 (r16) 35858007Ssaidi@eecs.umich.edu// 35868013Sbinkertn@umich.edu// 35878007Ssaidi@eecs.umich.edu// 35888007Ssaidi@eecs.umich.eduCALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY) 35898007Ssaidi@eecs.umich.eduCALL_PAL_Wrunique: 35908007Ssaidi@eecs.umich.edu nop 35918007Ssaidi@eecs.umich.edu mfpr r12, pt_pcbb // get pcb pointer 35928013Sbinkertn@umich.edu stq_p r16, osfpcb_q_unique(r12)// get new value 35938007Ssaidi@eecs.umich.edu nop // Pad palshadow write 35948007Ssaidi@eecs.umich.edu hw_rei // back 35958007Ssaidi@eecs.umich.edu 35968013Sbinkertn@umich.edu// CALL_PAL OPCDECs 35978007Ssaidi@eecs.umich.edu 35988007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A0) 35998007Ssaidi@eecs.umich.eduCallPal_OpcDecA0: 36008007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36018007Ssaidi@eecs.umich.edu 36028007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A1) 36038007Ssaidi@eecs.umich.eduCallPal_OpcDecA1: 36048007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36058007Ssaidi@eecs.umich.edu 36068007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A2) 36078007Ssaidi@eecs.umich.eduCallPal_OpcDecA2: 36088007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36098007Ssaidi@eecs.umich.edu 36108007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A3) 36118007Ssaidi@eecs.umich.eduCallPal_OpcDecA3: 36128007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36138007Ssaidi@eecs.umich.edu 36148007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A4) 36158007Ssaidi@eecs.umich.eduCallPal_OpcDecA4: 36168007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36178007Ssaidi@eecs.umich.edu 36188007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A5) 36198007Ssaidi@eecs.umich.eduCallPal_OpcDecA5: 36208007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36218007Ssaidi@eecs.umich.edu 36228007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A6) 36238007Ssaidi@eecs.umich.eduCallPal_OpcDecA6: 36248007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36258007Ssaidi@eecs.umich.edu 36268007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A7) 36278007Ssaidi@eecs.umich.eduCallPal_OpcDecA7: 36288007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36298007Ssaidi@eecs.umich.edu 36308007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A8) 36318007Ssaidi@eecs.umich.eduCallPal_OpcDecA8: 36328007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36338007Ssaidi@eecs.umich.edu 36348007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00A9) 36358007Ssaidi@eecs.umich.eduCallPal_OpcDecA9: 36368007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36378007Ssaidi@eecs.umich.edu 36388007Ssaidi@eecs.umich.edu 36398013Sbinkertn@umich.edu// 36408013Sbinkertn@umich.edu// gentrap - PALcode for gentrap instruction 36418013Sbinkertn@umich.edu// 36428007Ssaidi@eecs.umich.edu// CALL_PAL_gentrap: 36438007Ssaidi@eecs.umich.edu// Entry: 36448007Ssaidi@eecs.umich.edu// Vectored into via hardware PALcode instruction dispatch. 36458007Ssaidi@eecs.umich.edu// 36468007Ssaidi@eecs.umich.edu// Function: 36478007Ssaidi@eecs.umich.edu// Build stack frame 36488007Ssaidi@eecs.umich.edu// a0 <- code 36498007Ssaidi@eecs.umich.edu// a1 <- unpred 36508007Ssaidi@eecs.umich.edu// a2 <- unpred 36518007Ssaidi@eecs.umich.edu// vector via entIF 36528007Ssaidi@eecs.umich.edu// 36538013Sbinkertn@umich.edu// 36548007Ssaidi@eecs.umich.edu 36558007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AA) 36568007Ssaidi@eecs.umich.edu// unsupported in Hudson code .. pboyle Nov/95 36578007Ssaidi@eecs.umich.eduCALL_PAL_gentrap: 36588007Ssaidi@eecs.umich.edu sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit 36598007Ssaidi@eecs.umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 36608007Ssaidi@eecs.umich.edu 36618007Ssaidi@eecs.umich.edu bis r11, r31, r12 // Save PS for stack write 36628007Ssaidi@eecs.umich.edu bge r25, CALL_PAL_gentrap_10_ // no stack swap needed if cm=kern 36638007Ssaidi@eecs.umich.edu 36648007Ssaidi@eecs.umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - 36658007Ssaidi@eecs.umich.edu // no virt ref for next 2 cycles 36668007Ssaidi@eecs.umich.edu mtpr r30, pt_usp // save user stack 36678007Ssaidi@eecs.umich.edu 36688007Ssaidi@eecs.umich.edu bis r31, r31, r11 // Set new PS 36698007Ssaidi@eecs.umich.edu mfpr r30, pt_ksp 36708007Ssaidi@eecs.umich.edu 36718007Ssaidi@eecs.umich.eduCALL_PAL_gentrap_10_: 36728007Ssaidi@eecs.umich.edu lda sp, 0-osfsf_c_size(sp)// allocate stack space 36738007Ssaidi@eecs.umich.edu mfpr r14, exc_addr // get pc 36748007Ssaidi@eecs.umich.edu 36758007Ssaidi@eecs.umich.edu stq r16, osfsf_a0(sp) // save regs 36768007Ssaidi@eecs.umich.edu bis r31, osf_a0_gentrap, r16// set a0 36778007Ssaidi@eecs.umich.edu 36788007Ssaidi@eecs.umich.edu stq r17, osfsf_a1(sp) // a1 36798007Ssaidi@eecs.umich.edu br r31, bpt_bchk_common // out of call_pal space 36808007Ssaidi@eecs.umich.edu 36818007Ssaidi@eecs.umich.edu 36828013Sbinkertn@umich.edu// CALL_PAL OPCDECs 36838007Ssaidi@eecs.umich.edu 36848007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AB) 36858007Ssaidi@eecs.umich.eduCallPal_OpcDecAB: 36868007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36878007Ssaidi@eecs.umich.edu 36888007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AC) 36898007Ssaidi@eecs.umich.eduCallPal_OpcDecAC: 36908007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36918007Ssaidi@eecs.umich.edu 36928007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AD) 36938007Ssaidi@eecs.umich.eduCallPal_OpcDecAD: 36948007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36958007Ssaidi@eecs.umich.edu 36968007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AE) 36978007Ssaidi@eecs.umich.eduCallPal_OpcDecAE: 36988007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 36998007Ssaidi@eecs.umich.edu 37008007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00AF) 37018007Ssaidi@eecs.umich.eduCallPal_OpcDecAF: 37028007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37038007Ssaidi@eecs.umich.edu 37048007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B0) 37058007Ssaidi@eecs.umich.eduCallPal_OpcDecB0: 37068007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37078007Ssaidi@eecs.umich.edu 37088007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B1) 37098007Ssaidi@eecs.umich.eduCallPal_OpcDecB1: 37108007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37118007Ssaidi@eecs.umich.edu 37128007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B2) 37138007Ssaidi@eecs.umich.eduCallPal_OpcDecB2: 37148007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37158007Ssaidi@eecs.umich.edu 37168007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B3) 37178007Ssaidi@eecs.umich.eduCallPal_OpcDecB3: 37188007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37198007Ssaidi@eecs.umich.edu 37208007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B4) 37218007Ssaidi@eecs.umich.eduCallPal_OpcDecB4: 37228007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37238007Ssaidi@eecs.umich.edu 37248007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B5) 37258007Ssaidi@eecs.umich.eduCallPal_OpcDecB5: 37268007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37278007Ssaidi@eecs.umich.edu 37288007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B6) 37298007Ssaidi@eecs.umich.eduCallPal_OpcDecB6: 37308007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37318007Ssaidi@eecs.umich.edu 37328007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B7) 37338007Ssaidi@eecs.umich.eduCallPal_OpcDecB7: 37348007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37358007Ssaidi@eecs.umich.edu 37368007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B8) 37378007Ssaidi@eecs.umich.eduCallPal_OpcDecB8: 37388007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37398007Ssaidi@eecs.umich.edu 37408007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00B9) 37418007Ssaidi@eecs.umich.eduCallPal_OpcDecB9: 37428007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37438007Ssaidi@eecs.umich.edu 37448007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BA) 37458007Ssaidi@eecs.umich.eduCallPal_OpcDecBA: 37468007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37478007Ssaidi@eecs.umich.edu 37488007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BB) 37498007Ssaidi@eecs.umich.eduCallPal_OpcDecBB: 37508007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37518007Ssaidi@eecs.umich.edu 37528007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BC) 37538007Ssaidi@eecs.umich.eduCallPal_OpcDecBC: 37548007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37558007Ssaidi@eecs.umich.edu 37568007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BD) 37578007Ssaidi@eecs.umich.eduCallPal_OpcDecBD: 37588007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37598007Ssaidi@eecs.umich.edu 37608007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BE) 37618007Ssaidi@eecs.umich.eduCallPal_OpcDecBE: 37628007Ssaidi@eecs.umich.edu br r31, osfpal_calpal_opcdec 37638007Ssaidi@eecs.umich.edu 37648007Ssaidi@eecs.umich.edu CALL_PAL_UNPRIV(0x00BF) 37658007Ssaidi@eecs.umich.eduCallPal_OpcDecBF: 37668007Ssaidi@eecs.umich.edu // MODIFIED BY EGH 2/25/04 37678007Ssaidi@eecs.umich.edu br r31, copypal_impl 37688007Ssaidi@eecs.umich.edu 37698007Ssaidi@eecs.umich.edu 37708007Ssaidi@eecs.umich.edu/*======================================================================*/ 37718007Ssaidi@eecs.umich.edu/* OSF/1 CALL_PAL CONTINUATION AREA */ 37728007Ssaidi@eecs.umich.edu/*======================================================================*/ 37738007Ssaidi@eecs.umich.edu 37748007Ssaidi@eecs.umich.edu .text 2 37758007Ssaidi@eecs.umich.edu 37768007Ssaidi@eecs.umich.edu . = 0x4000 37778007Ssaidi@eecs.umich.edu 37788007Ssaidi@eecs.umich.edu 37798013Sbinkertn@umich.edu// Continuation of MTPR_PERFMON 37808007Ssaidi@eecs.umich.edu ALIGN_BLOCK 37818007Ssaidi@eecs.umich.edu // "real" performance monitoring code 37828007Ssaidi@eecs.umich.edu// mux ctl 37838007Ssaidi@eecs.umich.eduperfmon_muxctl: 37848007Ssaidi@eecs.umich.edu lda r8, 1(r31) // get a 1 37858007Ssaidi@eecs.umich.edu sll r8, pmctr_v_sel0, r8 // move to sel0 position 37868007Ssaidi@eecs.umich.edu or r8, ((0xf<<pmctr_v_sel1) | (0xf<<pmctr_v_sel2)), r8 // build mux select mask 37878007Ssaidi@eecs.umich.edu and r17, r8, r25 // isolate pmctr mux select bits 37888007Ssaidi@eecs.umich.edu mfpr r0, ev5__pmctr 37898007Ssaidi@eecs.umich.edu bic r0, r8, r0 // clear old mux select bits 37908007Ssaidi@eecs.umich.edu or r0,r25, r25 // or in new mux select bits 37918007Ssaidi@eecs.umich.edu mtpr r25, ev5__pmctr 37928007Ssaidi@eecs.umich.edu 37938007Ssaidi@eecs.umich.edu // ok, now tackle cbox mux selects 37948007Ssaidi@eecs.umich.edu ldah r14, 0xfff0(r31) 37958007Ssaidi@eecs.umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 37968007Ssaidi@eecs.umich.edu//orig get_bc_ctl_shadow r16 // bc_ctl returned in lower longword 37978007Ssaidi@eecs.umich.edu// adapted from ev5_pal_macros.mar 37988007Ssaidi@eecs.umich.edu mfpr r16, pt_impure 37998007Ssaidi@eecs.umich.edu lda r16, CNS_Q_IPR(r16) 38008007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16); 38018007Ssaidi@eecs.umich.edu 38028007Ssaidi@eecs.umich.edu lda r8, 0x3F(r31) // build mux select mask 38038007Ssaidi@eecs.umich.edu sll r8, bc_ctl_v_pm_mux_sel, r8 38048007Ssaidi@eecs.umich.edu 38058007Ssaidi@eecs.umich.edu and r17, r8, r25 // isolate bc_ctl mux select bits 38068007Ssaidi@eecs.umich.edu bic r16, r8, r16 // isolate old mux select bits 38078007Ssaidi@eecs.umich.edu or r16, r25, r25 // create new bc_ctl 38088007Ssaidi@eecs.umich.edu mb // clear out cbox for future ipr write 38098013Sbinkertn@umich.edu stq_p r25, ev5__bc_ctl(r14) // store to cbox ipr 38108007Ssaidi@eecs.umich.edu mb // clear out cbox for future ipr write 38118007Ssaidi@eecs.umich.edu 38128007Ssaidi@eecs.umich.edu//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr 38138007Ssaidi@eecs.umich.edu// adapted from ev5_pal_macros.mar 38148007Ssaidi@eecs.umich.edu mfpr r16, pt_impure 38158007Ssaidi@eecs.umich.edu lda r16, CNS_Q_IPR(r16) 38168007Ssaidi@eecs.umich.edu SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16); 38178007Ssaidi@eecs.umich.edu 38188007Ssaidi@eecs.umich.edu br r31, perfmon_success 38198007Ssaidi@eecs.umich.edu 38208007Ssaidi@eecs.umich.edu 38218007Ssaidi@eecs.umich.edu// requested to disable perf monitoring 38228007Ssaidi@eecs.umich.eduperfmon_dis: 38238007Ssaidi@eecs.umich.edu mfpr r14, ev5__pmctr // read ibox pmctr ipr 38248007Ssaidi@eecs.umich.eduperfmon_dis_ctr0: // and begin with ctr0 38258007Ssaidi@eecs.umich.edu blbc r17, perfmon_dis_ctr1 // do not disable ctr0 38268007Ssaidi@eecs.umich.edu lda r8, 3(r31) 38278007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctl0, r8 38288007Ssaidi@eecs.umich.edu bic r14, r8, r14 // disable ctr0 38298007Ssaidi@eecs.umich.eduperfmon_dis_ctr1: 38308007Ssaidi@eecs.umich.edu srl r17, 1, r17 38318007Ssaidi@eecs.umich.edu blbc r17, perfmon_dis_ctr2 // do not disable ctr1 38328007Ssaidi@eecs.umich.edu lda r8, 3(r31) 38338007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctl1, r8 38348007Ssaidi@eecs.umich.edu bic r14, r8, r14 // disable ctr1 38358007Ssaidi@eecs.umich.eduperfmon_dis_ctr2: 38368007Ssaidi@eecs.umich.edu srl r17, 1, r17 38378007Ssaidi@eecs.umich.edu blbc r17, perfmon_dis_update // do not disable ctr2 38388007Ssaidi@eecs.umich.edu lda r8, 3(r31) 38398007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctl2, r8 38408007Ssaidi@eecs.umich.edu bic r14, r8, r14 // disable ctr2 38418007Ssaidi@eecs.umich.eduperfmon_dis_update: 38428007Ssaidi@eecs.umich.edu mtpr r14, ev5__pmctr // update pmctr ipr 38438007Ssaidi@eecs.umich.edu//;the following code is not needed for ev5 pass2 and later, but doesn't hurt anything to leave in 38448007Ssaidi@eecs.umich.edu// adapted from ev5_pal_macros.mar 38458007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r8, r25 // pmctr_ctl bit in r8. adjusted impure pointer in r25 38468007Ssaidi@eecs.umich.edu mfpr r25, pt_impure 38478007Ssaidi@eecs.umich.edu lda r25, CNS_Q_IPR(r25) 38488007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r8,CNS_Q_PM_CTL,r25); 38498007Ssaidi@eecs.umich.edu 38508007Ssaidi@eecs.umich.edu lda r17, 0x3F(r31) // build mask 38518007Ssaidi@eecs.umich.edu sll r17, pmctr_v_ctl2, r17 // shift mask to correct position 38528007Ssaidi@eecs.umich.edu and r14, r17, r14 // isolate ctl bits 38538007Ssaidi@eecs.umich.edu bic r8, r17, r8 // clear out old ctl bits 38548007Ssaidi@eecs.umich.edu or r14, r8, r14 // create shadow ctl bits 38558007Ssaidi@eecs.umich.edu//orig store_reg1 pmctr_ctl, r14, r25, ipr=1 // update pmctr_ctl register 38568007Ssaidi@eecs.umich.edu//adjusted impure pointer still in r25 38578007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_PM_CTL,r25); 38588007Ssaidi@eecs.umich.edu 38598007Ssaidi@eecs.umich.edu br r31, perfmon_success 38608007Ssaidi@eecs.umich.edu 38618007Ssaidi@eecs.umich.edu 38628007Ssaidi@eecs.umich.edu// requested to enable perf monitoring 38638007Ssaidi@eecs.umich.edu//;the following code can be greatly simplified for pass2, but should work fine as is. 38648007Ssaidi@eecs.umich.edu 38658007Ssaidi@eecs.umich.edu 38668007Ssaidi@eecs.umich.eduperfmon_enclr: 38678007Ssaidi@eecs.umich.edu lda r9, 1(r31) // set enclr flag 38688007Ssaidi@eecs.umich.edu br perfmon_en_cont 38698007Ssaidi@eecs.umich.edu 38708007Ssaidi@eecs.umich.eduperfmon_en: 38718007Ssaidi@eecs.umich.edu bis r31, r31, r9 // clear enclr flag 38728007Ssaidi@eecs.umich.edu 38738007Ssaidi@eecs.umich.eduperfmon_en_cont: 38748007Ssaidi@eecs.umich.edu mfpr r8, pt_pcbb // get PCB base 38758007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r25, r25 38768007Ssaidi@eecs.umich.edu mfpr r25, pt_impure 38778007Ssaidi@eecs.umich.edu lda r25, CNS_Q_IPR(r25) 38788007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25); 38798007Ssaidi@eecs.umich.edu 38808013Sbinkertn@umich.edu ldq_p r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword 38818007Ssaidi@eecs.umich.edu mfpr r14, ev5__pmctr // read ibox pmctr ipr 38828007Ssaidi@eecs.umich.edu srl r16, osfpcb_v_pme, r16 // get pme bit 38838007Ssaidi@eecs.umich.edu mfpr r13, icsr 38848007Ssaidi@eecs.umich.edu and r16, 1, r16 // isolate pme bit 38858007Ssaidi@eecs.umich.edu 38868007Ssaidi@eecs.umich.edu // this code only needed in pass2 and later 38878007Ssaidi@eecs.umich.edu lda r12, 1<<icsr_v_pmp(r31) // pb 38888007Ssaidi@eecs.umich.edu bic r13, r12, r13 // clear pmp bit 38898007Ssaidi@eecs.umich.edu sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position 38908007Ssaidi@eecs.umich.edu or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear 38918013Sbinkertn@umich.edu mtpr r13, icsr // update icsr 38928013Sbinkertn@umich.edu 38938007Ssaidi@eecs.umich.edu bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable) 38948007Ssaidi@eecs.umich.edu 38958007Ssaidi@eecs.umich.edu sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions 38968007Ssaidi@eecs.umich.edu bis r14, r31, r13 // copy pmctr 38978007Ssaidi@eecs.umich.edu 38988007Ssaidi@eecs.umich.eduperfmon_en_ctr0: // and begin with ctr0 38998007Ssaidi@eecs.umich.edu blbc r17, perfmon_en_ctr1 // do not enable ctr0 39008007Ssaidi@eecs.umich.edu 39018007Ssaidi@eecs.umich.edu blbc r9, perfmon_en_noclr0 // enclr flag set, clear ctr0 field 39028007Ssaidi@eecs.umich.edu lda r8, 0xffff(r31) 39038007Ssaidi@eecs.umich.edu zapnot r8, 3, r8 // ctr0<15:0> mask 39048007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctr0, r8 39058007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctr bits 39068007Ssaidi@eecs.umich.edu bic r13, r8, r13 // clear ctr bits 39078007Ssaidi@eecs.umich.edu 39088007Ssaidi@eecs.umich.eduperfmon_en_noclr0: 39098007Ssaidi@eecs.umich.edu//orig get_addr r8, 3<<pmctr_v_ctl0, r31 39108007Ssaidi@eecs.umich.edu LDLI(r8, (3<<pmctr_v_ctl0)) 39118007Ssaidi@eecs.umich.edu and r25, r8, r12 //isolate frequency select bits for ctr0 39128007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctl0 bits in preparation for enabling 39138007Ssaidi@eecs.umich.edu or r14,r12,r14 // or in new ctl0 bits 39148007Ssaidi@eecs.umich.edu 39158007Ssaidi@eecs.umich.eduperfmon_en_ctr1: // enable ctr1 39168007Ssaidi@eecs.umich.edu srl r17, 1, r17 // get ctr1 enable 39178007Ssaidi@eecs.umich.edu blbc r17, perfmon_en_ctr2 // do not enable ctr1 39188007Ssaidi@eecs.umich.edu 39198007Ssaidi@eecs.umich.edu blbc r9, perfmon_en_noclr1 // if enclr flag set, clear ctr1 field 39208007Ssaidi@eecs.umich.edu lda r8, 0xffff(r31) 39218007Ssaidi@eecs.umich.edu zapnot r8, 3, r8 // ctr1<15:0> mask 39228007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctr1, r8 39238007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctr bits 39248007Ssaidi@eecs.umich.edu bic r13, r8, r13 // clear ctr bits 39258007Ssaidi@eecs.umich.edu 39268007Ssaidi@eecs.umich.eduperfmon_en_noclr1: 39278007Ssaidi@eecs.umich.edu//orig get_addr r8, 3<<pmctr_v_ctl1, r31 39288007Ssaidi@eecs.umich.edu LDLI(r8, (3<<pmctr_v_ctl1)) 39298007Ssaidi@eecs.umich.edu and r25, r8, r12 //isolate frequency select bits for ctr1 39308007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctl1 bits in preparation for enabling 39318007Ssaidi@eecs.umich.edu or r14,r12,r14 // or in new ctl1 bits 39328007Ssaidi@eecs.umich.edu 39338007Ssaidi@eecs.umich.eduperfmon_en_ctr2: // enable ctr2 39348007Ssaidi@eecs.umich.edu srl r17, 1, r17 // get ctr2 enable 39358007Ssaidi@eecs.umich.edu blbc r17, perfmon_en_return // do not enable ctr2 - return 39368007Ssaidi@eecs.umich.edu 39378007Ssaidi@eecs.umich.edu blbc r9, perfmon_en_noclr2 // if enclr flag set, clear ctr2 field 39388007Ssaidi@eecs.umich.edu lda r8, 0x3FFF(r31) // ctr2<13:0> mask 39398007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctr2, r8 39408007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctr bits 39418007Ssaidi@eecs.umich.edu bic r13, r8, r13 // clear ctr bits 39428007Ssaidi@eecs.umich.edu 39438007Ssaidi@eecs.umich.eduperfmon_en_noclr2: 39448007Ssaidi@eecs.umich.edu//orig get_addr r8, 3<<pmctr_v_ctl2, r31 39458007Ssaidi@eecs.umich.edu LDLI(r8, (3<<pmctr_v_ctl2)) 39468007Ssaidi@eecs.umich.edu and r25, r8, r12 //isolate frequency select bits for ctr2 39478007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctl2 bits in preparation for enabling 39488007Ssaidi@eecs.umich.edu or r14,r12,r14 // or in new ctl2 bits 39498007Ssaidi@eecs.umich.edu 39508007Ssaidi@eecs.umich.eduperfmon_en_return: 39518007Ssaidi@eecs.umich.edu cmovlbs r16, r14, r13 // if pme enabled, move enables into pmctr 39528007Ssaidi@eecs.umich.edu // else only do the counter clears 39538007Ssaidi@eecs.umich.edu mtpr r13, ev5__pmctr // update pmctr ipr 39548007Ssaidi@eecs.umich.edu 39558007Ssaidi@eecs.umich.edu//;this code not needed for pass2 and later, but does not hurt to leave it in 39568007Ssaidi@eecs.umich.edu lda r8, 0x3F(r31) 39578007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r25, r12 // read pmctr ctl; r12=adjusted impure pointer 39588007Ssaidi@eecs.umich.edu mfpr r12, pt_impure 39598007Ssaidi@eecs.umich.edu lda r12, CNS_Q_IPR(r12) 39608007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r12); 39618007Ssaidi@eecs.umich.edu 39628007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctl2, r8 // build ctl mask 39638007Ssaidi@eecs.umich.edu and r8, r14, r14 // isolate new ctl bits 39648007Ssaidi@eecs.umich.edu bic r25, r8, r25 // clear out old ctl value 39658007Ssaidi@eecs.umich.edu or r25, r14, r14 // create new pmctr_ctl 39668007Ssaidi@eecs.umich.edu//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 39678007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr 39688007Ssaidi@eecs.umich.edu 39698007Ssaidi@eecs.umich.edu br r31, perfmon_success 39708007Ssaidi@eecs.umich.edu 39718007Ssaidi@eecs.umich.edu 39728007Ssaidi@eecs.umich.edu// options... 39738007Ssaidi@eecs.umich.eduperfmon_ctl: 39748007Ssaidi@eecs.umich.edu 39758007Ssaidi@eecs.umich.edu// set mode 39768007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer 39778007Ssaidi@eecs.umich.edu mfpr r12, pt_impure 39788007Ssaidi@eecs.umich.edu lda r12, CNS_Q_IPR(r12) 39798007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); 39808007Ssaidi@eecs.umich.edu 39818013Sbinkertn@umich.edu // build mode mask for pmctr register 39828007Ssaidi@eecs.umich.edu LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk))) 39838007Ssaidi@eecs.umich.edu mfpr r0, ev5__pmctr 39848007Ssaidi@eecs.umich.edu and r17, r8, r25 // isolate pmctr mode bits 39858007Ssaidi@eecs.umich.edu bic r0, r8, r0 // clear old mode bits 39868007Ssaidi@eecs.umich.edu or r0, r25, r25 // or in new mode bits 39878007Ssaidi@eecs.umich.edu mtpr r25, ev5__pmctr 39888007Ssaidi@eecs.umich.edu 39898013Sbinkertn@umich.edu // the following code will only be used in pass2, but should 39908013Sbinkertn@umich.edu // not hurt anything if run in pass1. 39918007Ssaidi@eecs.umich.edu mfpr r8, icsr 39928007Ssaidi@eecs.umich.edu lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0 39938007Ssaidi@eecs.umich.edu bic r8, r25, r8 // clear old pma bit 39948007Ssaidi@eecs.umich.edu cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1 39958007Ssaidi@eecs.umich.edu or r8, r25, r8 39968013Sbinkertn@umich.edu mtpr r8, icsr // 4 bubbles to hw_rei 39978007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad icsr write 39988007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad icsr write 39998007Ssaidi@eecs.umich.edu 40008013Sbinkertn@umich.edu // the following code not needed for pass2 and later, but 40018013Sbinkertn@umich.edu // should work anyway. 40028007Ssaidi@eecs.umich.edu bis r14, 1, r14 // set for select processes 40038007Ssaidi@eecs.umich.edu blbs r17, perfmon_sp // branch if select processes 40048007Ssaidi@eecs.umich.edu bic r14, 1, r14 // all processes 40058007Ssaidi@eecs.umich.eduperfmon_sp: 40068007Ssaidi@eecs.umich.edu//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register 40078007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr 40088007Ssaidi@eecs.umich.edu br r31, perfmon_success 40098007Ssaidi@eecs.umich.edu 40108007Ssaidi@eecs.umich.edu// counter frequency select 40118007Ssaidi@eecs.umich.eduperfmon_freq: 40128007Ssaidi@eecs.umich.edu//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer 40138007Ssaidi@eecs.umich.edu mfpr r12, pt_impure 40148007Ssaidi@eecs.umich.edu lda r12, CNS_Q_IPR(r12) 40158007Ssaidi@eecs.umich.edu RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); 40168007Ssaidi@eecs.umich.edu 40178007Ssaidi@eecs.umich.edu lda r8, 0x3F(r31) 40188007Ssaidi@eecs.umich.edu//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field 40198013Sbinkertn@umich.edu// I guess this should be a shift of 4 bits from the above control register structure 40208007Ssaidi@eecs.umich.edu#define pmctr_ctl_v_frq2_SHIFT 4 40218007Ssaidi@eecs.umich.edu sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field 40228007Ssaidi@eecs.umich.edu 40238007Ssaidi@eecs.umich.edu and r8, r17, r17 40248007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear out old frequency select bits 40258007Ssaidi@eecs.umich.edu 40268007Ssaidi@eecs.umich.edu or r17, r14, r14 // or in new frequency select info 40278007Ssaidi@eecs.umich.edu//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register 40288007Ssaidi@eecs.umich.edu SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr 40298007Ssaidi@eecs.umich.edu 40308007Ssaidi@eecs.umich.edu br r31, perfmon_success 40318007Ssaidi@eecs.umich.edu 40328007Ssaidi@eecs.umich.edu// read counters 40338007Ssaidi@eecs.umich.eduperfmon_rd: 40348007Ssaidi@eecs.umich.edu mfpr r0, ev5__pmctr 40358007Ssaidi@eecs.umich.edu or r0, 1, r0 // or in return status 40368007Ssaidi@eecs.umich.edu hw_rei // back to user 40378007Ssaidi@eecs.umich.edu 40388007Ssaidi@eecs.umich.edu// write counters 40398007Ssaidi@eecs.umich.eduperfmon_wr: 40408007Ssaidi@eecs.umich.edu mfpr r14, ev5__pmctr 40418007Ssaidi@eecs.umich.edu lda r8, 0x3FFF(r31) // ctr2<13:0> mask 40428007Ssaidi@eecs.umich.edu sll r8, pmctr_v_ctr2, r8 40438007Ssaidi@eecs.umich.edu 40448013Sbinkertn@umich.edu LDLI(r9, (0xFFFFFFFF)) // ctr2<15:0>,ctr1<15:0> mask 40458007Ssaidi@eecs.umich.edu sll r9, pmctr_v_ctr1, r9 40468007Ssaidi@eecs.umich.edu or r8, r9, r8 // or ctr2, ctr1, ctr0 mask 40478007Ssaidi@eecs.umich.edu bic r14, r8, r14 // clear ctr fields 40488007Ssaidi@eecs.umich.edu and r17, r8, r25 // clear all but ctr fields 40498007Ssaidi@eecs.umich.edu or r25, r14, r14 // write ctr fields 40508007Ssaidi@eecs.umich.edu mtpr r14, ev5__pmctr // update pmctr ipr 40518007Ssaidi@eecs.umich.edu 40528007Ssaidi@eecs.umich.edu mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy) 40538007Ssaidi@eecs.umich.edu 40548007Ssaidi@eecs.umich.eduperfmon_success: 40558007Ssaidi@eecs.umich.edu or r31, 1, r0 // set success 40568007Ssaidi@eecs.umich.edu hw_rei // back to user 40578007Ssaidi@eecs.umich.edu 40588007Ssaidi@eecs.umich.eduperfmon_unknown: 40598007Ssaidi@eecs.umich.edu or r31, r31, r0 // set fail 40608007Ssaidi@eecs.umich.edu hw_rei // back to user 40618007Ssaidi@eecs.umich.edu 40628013Sbinkertn@umich.edu 40638013Sbinkertn@umich.edu////////////////////////////////////////////////////////// 40648013Sbinkertn@umich.edu// Copy code 40658013Sbinkertn@umich.edu////////////////////////////////////////////////////////// 40668007Ssaidi@eecs.umich.edu 40678007Ssaidi@eecs.umich.educopypal_impl: 40688007Ssaidi@eecs.umich.edu mov r16, r0 40698013Sbinkertn@umich.edu#ifdef CACHE_COPY 40708013Sbinkertn@umich.edu#ifndef CACHE_COPY_UNALIGNED 40718013Sbinkertn@umich.edu and r16, 63, r8 40728013Sbinkertn@umich.edu and r17, 63, r9 40738013Sbinkertn@umich.edu bis r8, r9, r8 40748013Sbinkertn@umich.edu bne r8, cache_copy_done 40758013Sbinkertn@umich.edu#endif 40768013Sbinkertn@umich.edu bic r18, 63, r8 40778013Sbinkertn@umich.edu and r18, 63, r18 40788013Sbinkertn@umich.edu beq r8, cache_copy_done 40798013Sbinkertn@umich.educache_loop: 40808013Sbinkertn@umich.edu ldf f17, 0(r16) 40818013Sbinkertn@umich.edu stf f17, 0(r16) 40828013Sbinkertn@umich.edu addq r17, 64, r17 40838013Sbinkertn@umich.edu addq r16, 64, r16 40848013Sbinkertn@umich.edu subq r8, 64, r8 40858013Sbinkertn@umich.edu bne r8, cache_loop 40868013Sbinkertn@umich.educache_copy_done: 40878013Sbinkertn@umich.edu#endif 40888013Sbinkertn@umich.edu ble r18, finished // if len <=0 we are finished 40898007Ssaidi@eecs.umich.edu ldq_u r8, 0(r17) 40908007Ssaidi@eecs.umich.edu xor r17, r16, r9 40918007Ssaidi@eecs.umich.edu and r9, 7, r9 40928007Ssaidi@eecs.umich.edu and r16, 7, r10 40938007Ssaidi@eecs.umich.edu bne r9, unaligned 40948007Ssaidi@eecs.umich.edu beq r10, aligned 40958007Ssaidi@eecs.umich.edu ldq_u r9, 0(r16) 40968007Ssaidi@eecs.umich.edu addq r18, r10, r18 40978007Ssaidi@eecs.umich.edu mskqh r8, r17, r8 40988007Ssaidi@eecs.umich.edu mskql r9, r17, r9 40998007Ssaidi@eecs.umich.edu bis r8, r9, r8 41008007Ssaidi@eecs.umich.edualigned: 41018007Ssaidi@eecs.umich.edu subq r18, 1, r10 41028007Ssaidi@eecs.umich.edu bic r10, 7, r10 41038007Ssaidi@eecs.umich.edu and r18, 7, r18 41048007Ssaidi@eecs.umich.edu beq r10, aligned_done 41058007Ssaidi@eecs.umich.eduloop: 41068007Ssaidi@eecs.umich.edu stq_u r8, 0(r16) 41078007Ssaidi@eecs.umich.edu ldq_u r8, 8(r17) 41088007Ssaidi@eecs.umich.edu subq r10, 8, r10 41098007Ssaidi@eecs.umich.edu lda r16,8(r16) 41108007Ssaidi@eecs.umich.edu lda r17,8(r17) 41118007Ssaidi@eecs.umich.edu bne r10, loop 41128007Ssaidi@eecs.umich.edualigned_done: 41138007Ssaidi@eecs.umich.edu bne r18, few_left 41148007Ssaidi@eecs.umich.edu stq_u r8, 0(r16) 41158007Ssaidi@eecs.umich.edu br r31, finished 41168007Ssaidi@eecs.umich.edu few_left: 41178007Ssaidi@eecs.umich.edu mskql r8, r18, r10 41188007Ssaidi@eecs.umich.edu ldq_u r9, 0(r16) 41198007Ssaidi@eecs.umich.edu mskqh r9, r18, r9 41208007Ssaidi@eecs.umich.edu bis r10, r9, r10 41218007Ssaidi@eecs.umich.edu stq_u r10, 0(r16) 41228007Ssaidi@eecs.umich.edu br r31, finished 41238007Ssaidi@eecs.umich.eduunaligned: 41248007Ssaidi@eecs.umich.edu addq r17, r18, r25 41258007Ssaidi@eecs.umich.edu cmpule r18, 8, r9 41268007Ssaidi@eecs.umich.edu bne r9, unaligned_few_left 41278007Ssaidi@eecs.umich.edu beq r10, unaligned_dest_aligned 41288007Ssaidi@eecs.umich.edu and r16, 7, r10 41298007Ssaidi@eecs.umich.edu subq r31, r10, r10 41308007Ssaidi@eecs.umich.edu addq r10, 8, r10 41318007Ssaidi@eecs.umich.edu ldq_u r9, 7(r17) 41328007Ssaidi@eecs.umich.edu extql r8, r17, r8 41338007Ssaidi@eecs.umich.edu extqh r9, r17, r9 41348007Ssaidi@eecs.umich.edu bis r8, r9, r12 41358007Ssaidi@eecs.umich.edu insql r12, r16, r12 41368007Ssaidi@eecs.umich.edu ldq_u r13, 0(r16) 41378007Ssaidi@eecs.umich.edu mskql r13, r16, r13 41388007Ssaidi@eecs.umich.edu bis r12, r13, r12 41398007Ssaidi@eecs.umich.edu stq_u r12, 0(r16) 41408007Ssaidi@eecs.umich.edu addq r16, r10, r16 41418007Ssaidi@eecs.umich.edu addq r17, r10, r17 41428007Ssaidi@eecs.umich.edu subq r18, r10, r18 41438007Ssaidi@eecs.umich.edu ldq_u r8, 0(r17) 41448007Ssaidi@eecs.umich.eduunaligned_dest_aligned: 41458007Ssaidi@eecs.umich.edu subq r18, 1, r10 41468007Ssaidi@eecs.umich.edu bic r10, 7, r10 41478007Ssaidi@eecs.umich.edu and r18, 7, r18 41488007Ssaidi@eecs.umich.edu beq r10, unaligned_partial_left 41498007Ssaidi@eecs.umich.eduunaligned_loop: 41508007Ssaidi@eecs.umich.edu ldq_u r9, 7(r17) 41518007Ssaidi@eecs.umich.edu lda r17, 8(r17) 41528007Ssaidi@eecs.umich.edu extql r8, r17, r12 41538007Ssaidi@eecs.umich.edu extqh r9, r17, r13 41548007Ssaidi@eecs.umich.edu subq r10, 8, r10 41558007Ssaidi@eecs.umich.edu bis r12, r13, r13 41568007Ssaidi@eecs.umich.edu stq r13, 0(r16) 41578007Ssaidi@eecs.umich.edu lda r16, 8(r16) 41588007Ssaidi@eecs.umich.edu beq r10, unaligned_second_partial_left 41598007Ssaidi@eecs.umich.edu ldq_u r8, 7(r17) 41608007Ssaidi@eecs.umich.edu lda r17, 8(r17) 41618007Ssaidi@eecs.umich.edu extql r9, r17, r12 41628007Ssaidi@eecs.umich.edu extqh r8, r17, r13 41638007Ssaidi@eecs.umich.edu bis r12, r13, r13 41648007Ssaidi@eecs.umich.edu subq r10, 8, r10 41658007Ssaidi@eecs.umich.edu stq r13, 0(r16) 41668007Ssaidi@eecs.umich.edu lda r16, 8(r16) 41678007Ssaidi@eecs.umich.edu bne r10, unaligned_loop 41688007Ssaidi@eecs.umich.eduunaligned_partial_left: 41698007Ssaidi@eecs.umich.edu mov r8, r9 41708007Ssaidi@eecs.umich.eduunaligned_second_partial_left: 41718007Ssaidi@eecs.umich.edu ldq_u r8, -1(r25) 41728007Ssaidi@eecs.umich.edu extql r9, r17, r9 41738007Ssaidi@eecs.umich.edu extqh r8, r17, r8 41748007Ssaidi@eecs.umich.edu bis r8, r9, r8 41758007Ssaidi@eecs.umich.edu bne r18, few_left 41768007Ssaidi@eecs.umich.edu stq_u r8, 0(r16) 41778007Ssaidi@eecs.umich.edu br r31, finished 41788007Ssaidi@eecs.umich.eduunaligned_few_left: 41798007Ssaidi@eecs.umich.edu ldq_u r9, -1(r25) 41808007Ssaidi@eecs.umich.edu extql r8, r17, r8 41818007Ssaidi@eecs.umich.edu extqh r9, r17, r9 41828007Ssaidi@eecs.umich.edu bis r8, r9, r8 41838007Ssaidi@eecs.umich.edu insqh r8, r16, r9 41848007Ssaidi@eecs.umich.edu insql r8, r16, r8 41858007Ssaidi@eecs.umich.edu lda r12, -1(r31) 41868007Ssaidi@eecs.umich.edu mskql r12, r18, r13 41878007Ssaidi@eecs.umich.edu cmovne r13, r13, r12 41888007Ssaidi@eecs.umich.edu insqh r12, r16, r13 41898007Ssaidi@eecs.umich.edu insql r12, r16, r12 41908007Ssaidi@eecs.umich.edu addq r16, r18, r10 41918007Ssaidi@eecs.umich.edu ldq_u r14, 0(r16) 41928007Ssaidi@eecs.umich.edu ldq_u r25, -1(r10) 41938007Ssaidi@eecs.umich.edu bic r14, r12, r14 41948007Ssaidi@eecs.umich.edu bic r25, r13, r25 41958007Ssaidi@eecs.umich.edu and r8, r12, r8 41968007Ssaidi@eecs.umich.edu and r9, r13, r9 41978007Ssaidi@eecs.umich.edu bis r8, r14, r8 41988007Ssaidi@eecs.umich.edu bis r9, r25, r9 41998007Ssaidi@eecs.umich.edu stq_u r9, -1(r10) 42008007Ssaidi@eecs.umich.edu stq_u r8, 0(r16) 42018007Ssaidi@eecs.umich.edufinished: 42028007Ssaidi@eecs.umich.edu hw_rei 4203