18013Sbinkertn@umich.edu/* 28029Snate@binkert.org * Copyright (c) 2003-2005 The Regents of The University of Michigan 38029Snate@binkert.org * Copyright (c) 1993 Hewlett-Packard Development Company 48029Snate@binkert.org * All rights reserved. 58013Sbinkertn@umich.edu * 68029Snate@binkert.org * Redistribution and use in source and binary forms, with or without 78029Snate@binkert.org * modification, are permitted provided that the following conditions are 88029Snate@binkert.org * met: redistributions of source code must retain the above copyright 98029Snate@binkert.org * notice, this list of conditions and the following disclaimer; 108029Snate@binkert.org * redistributions in binary form must reproduce the above copyright 118029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 128029Snate@binkert.org * documentation and/or other materials provided with the distribution; 138029Snate@binkert.org * neither the name of the copyright holders nor the names of its 148029Snate@binkert.org * contributors may be used to endorse or promote products derived from 158029Snate@binkert.org * this software without specific prior written permission. 168013Sbinkertn@umich.edu * 178029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 188029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 198029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 208029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 218029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 228029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 238029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 248029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 258029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 268029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 278029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 288013Sbinkertn@umich.edu * 298029Snate@binkert.org * Authors: Ali G. Saidi 308029Snate@binkert.org * Nathan L. Binkert 318013Sbinkertn@umich.edu */ 328013Sbinkertn@umich.edu 338013Sbinkertn@umich.edu#define max_cpuid 1 348013Sbinkertn@umich.edu#define hw_rei_spe hw_rei 358013Sbinkertn@umich.edu 368013Sbinkertn@umich.edu#include "ev5_defs.h" 378013Sbinkertn@umich.edu#include "ev5_impure.h" 388013Sbinkertn@umich.edu#include "ev5_alpha_defs.h" 398013Sbinkertn@umich.edu#include "ev5_paldef.h" 408013Sbinkertn@umich.edu#include "ev5_osfalpha_defs.h" 418013Sbinkertn@umich.edu#include "fromHudsonMacros.h" 428013Sbinkertn@umich.edu#include "fromHudsonOsf.h" 438013Sbinkertn@umich.edu#include "dc21164FromGasSources.h" 448013Sbinkertn@umich.edu#include "cserve.h" 458013Sbinkertn@umich.edu#include "tlaser.h" 468013Sbinkertn@umich.edu 478013Sbinkertn@umich.edu#define pt_entInt pt_entint 488013Sbinkertn@umich.edu#define pt_entArith pt_entarith 498013Sbinkertn@umich.edu#define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8) 508013Sbinkertn@umich.edu#define mchk_flag CNS_Q_FLAG 518013Sbinkertn@umich.edu#define mchk_sys_base 56 528013Sbinkertn@umich.edu#define mchk_cpu_base (CNS_Q_LD_LOCK + 8) 538013Sbinkertn@umich.edu#define mchk_offsets CNS_Q_EXC_ADDR 548013Sbinkertn@umich.edu#define mchk_mchk_code 8 558013Sbinkertn@umich.edu#define mchk_ic_perr_stat CNS_Q_ICPERR_STAT 568013Sbinkertn@umich.edu#define mchk_dc_perr_stat CNS_Q_DCPERR_STAT 578013Sbinkertn@umich.edu#define mchk_sc_addr CNS_Q_SC_ADDR 588013Sbinkertn@umich.edu#define mchk_sc_stat CNS_Q_SC_STAT 598013Sbinkertn@umich.edu#define mchk_ei_addr CNS_Q_EI_ADDR 608013Sbinkertn@umich.edu#define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR 618013Sbinkertn@umich.edu#define mchk_fill_syn CNS_Q_FILL_SYN 628013Sbinkertn@umich.edu#define mchk_ei_stat CNS_Q_EI_STAT 638013Sbinkertn@umich.edu#define mchk_exc_addr CNS_Q_EXC_ADDR 648013Sbinkertn@umich.edu#define mchk_ld_lock CNS_Q_LD_LOCK 658013Sbinkertn@umich.edu#define osfpcb_q_Ksp pcb_q_ksp 668013Sbinkertn@umich.edu#define pal_impure_common_size ((0x200 + 7) & 0xfff8) 678013Sbinkertn@umich.edu 688013Sbinkertn@umich.edu#if defined(BIG_TSUNAMI) 698013Sbinkertn@umich.edu#define MAXPROC 0x3f 708013Sbinkertn@umich.edu#define IPIQ_addr 0x800 718013Sbinkertn@umich.edu#define IPIQ_shift 0 728013Sbinkertn@umich.edu#define IPIR_addr 0x840 738013Sbinkertn@umich.edu#define IPIR_shift 0 748013Sbinkertn@umich.edu#define RTC_addr 0x880 758013Sbinkertn@umich.edu#define RTC_shift 0 768013Sbinkertn@umich.edu#define DIR_addr 0xa2 778013Sbinkertn@umich.edu#elif defined(TSUNAMI) 788013Sbinkertn@umich.edu#define MAXPROC 0x3 798013Sbinkertn@umich.edu#define IPIQ_addr 0x080 808013Sbinkertn@umich.edu#define IPIQ_shift 12 818013Sbinkertn@umich.edu#define IPIR_addr 0x080 828013Sbinkertn@umich.edu#define IPIR_shift 8 838013Sbinkertn@umich.edu#define RTC_addr 0x080 848013Sbinkertn@umich.edu#define RTC_shift 4 858013Sbinkertn@umich.edu#define DIR_addr 0xa0 868013Sbinkertn@umich.edu#elif defined(TLASER) 878013Sbinkertn@umich.edu#define MAXPROC 0xf 888013Sbinkertn@umich.edu#else 898013Sbinkertn@umich.edu#error Must define BIG_TSUNAMI, TSUNAMI, or TLASER 908013Sbinkertn@umich.edu#endif 918013Sbinkertn@umich.edu 928013Sbinkertn@umich.edu#define ALIGN_BLOCK \ 938013Sbinkertn@umich.edu .align 5 948013Sbinkertn@umich.edu 958013Sbinkertn@umich.edu#define ALIGN_BRANCH \ 968013Sbinkertn@umich.edu .align 3 978013Sbinkertn@umich.edu 988013Sbinkertn@umich.edu#define EXPORT(_x) \ 998013Sbinkertn@umich.edu .align 5; \ 1008013Sbinkertn@umich.edu .globl _x; \ 1018013Sbinkertn@umich.edu_x: 1028013Sbinkertn@umich.edu 1038013Sbinkertn@umich.edu// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 1048013Sbinkertn@umich.edu// XXX the following is 'made up' 1058013Sbinkertn@umich.edu// XXX bugnion 1068013Sbinkertn@umich.edu 1078013Sbinkertn@umich.edu// XXX bugnion not sure how to align 'quad' 1088013Sbinkertn@umich.edu#define ALIGN_QUAD \ 1098013Sbinkertn@umich.edu .align 3 1108013Sbinkertn@umich.edu 1118013Sbinkertn@umich.edu#define ALIGN_128 \ 1128013Sbinkertn@umich.edu .align 7 1138013Sbinkertn@umich.edu 1148013Sbinkertn@umich.edu 1158013Sbinkertn@umich.edu#define GET_IMPURE(_r) mfpr _r,pt_impure 1168013Sbinkertn@umich.edu#define GET_ADDR(_r1,_off,_r2) lda _r1,_off(_r2) 1178013Sbinkertn@umich.edu 1188013Sbinkertn@umich.edu 1198013Sbinkertn@umich.edu#define BIT(_x) (1<<(_x)) 1208013Sbinkertn@umich.edu 1218013Sbinkertn@umich.edu 1228013Sbinkertn@umich.edu// System specific code - beh model version 1238013Sbinkertn@umich.edu// 1248013Sbinkertn@umich.edu// 1258013Sbinkertn@umich.edu// Entry points 1268013Sbinkertn@umich.edu// SYS_CFLUSH - Cache flush 1278013Sbinkertn@umich.edu// SYS_CSERVE - Console service 1288013Sbinkertn@umich.edu// SYS_WRIPIR - interprocessor interrupts 1298013Sbinkertn@umich.edu// SYS_HALT_INTERRUPT - Halt interrupt 1308013Sbinkertn@umich.edu// SYS_PASSIVE_RELEASE - Interrupt, passive release 1318013Sbinkertn@umich.edu// SYS_INTERRUPT - Interrupt 1328013Sbinkertn@umich.edu// SYS_RESET - Reset 1338013Sbinkertn@umich.edu// SYS_ENTER_CONSOLE 1348013Sbinkertn@umich.edu// 1358013Sbinkertn@umich.edu// 1368013Sbinkertn@umich.edu// Macro to read TLINTRSUMx 1378013Sbinkertn@umich.edu// 1388013Sbinkertn@umich.edu// Based on the CPU_NUMBER, read either the TLINTRSUM0 or TLINTRSUM1 register 1398013Sbinkertn@umich.edu// 1408013Sbinkertn@umich.edu// Assumed register usage: 1418013Sbinkertn@umich.edu// rsum TLINTRSUMx contents 1428013Sbinkertn@umich.edu// raddr node space address 1438013Sbinkertn@umich.edu// scratch scratch register 1448013Sbinkertn@umich.edu// 1458013Sbinkertn@umich.edu#define Read_TLINTRSUMx(_rsum, _raddr, _scratch) \ 1468013Sbinkertn@umich.edu nop; \ 1478013Sbinkertn@umich.edu mfpr _scratch, pt_whami; /* Get our whami (VID) */ \ 1488013Sbinkertn@umich.edu extbl _scratch, 1, _scratch; /* shift down to bit 0 */ \ 1498013Sbinkertn@umich.edu lda _raddr, 0xff88(zero); /* Get base node space address bits */ \ 1508013Sbinkertn@umich.edu sll _raddr, 24, _raddr; /* Shift up to proper position */ \ 1518013Sbinkertn@umich.edu srl _scratch, 1, _rsum; /* Shift off the cpu number */ \ 1528013Sbinkertn@umich.edu sll _rsum, 22, _rsum; /* Get our node offset */ \ 1538013Sbinkertn@umich.edu addq _raddr, _rsum, _raddr; /* Get our base node space address */ \ 1548013Sbinkertn@umich.edu blbs _scratch, 1f; \ 1558013Sbinkertn@umich.edu lda _raddr, 0x1180(_raddr); \ 1568013Sbinkertn@umich.edu br r31, 2f; \ 1578013Sbinkertn@umich.edu1: lda _raddr, 0x11c0(_raddr); \ 1588013Sbinkertn@umich.edu2: ldl_p _rsum, 0(_raddr) /* read the right tlintrsum reg */ 1598013Sbinkertn@umich.edu 1608013Sbinkertn@umich.edu// 1618013Sbinkertn@umich.edu// Macro to write TLINTRSUMx 1628013Sbinkertn@umich.edu// 1638013Sbinkertn@umich.edu// Based on the CPU_NUMBER, write either the TLINTRSUM0 or TLINTRSUM1 register 1648013Sbinkertn@umich.edu// 1658013Sbinkertn@umich.edu// Assumed register usage: 1668013Sbinkertn@umich.edu// rsum TLINTRSUMx write data 1678013Sbinkertn@umich.edu// raddr node space address 1688013Sbinkertn@umich.edu// scratch scratch register 1698013Sbinkertn@umich.edu// 1708013Sbinkertn@umich.edu#define Write_TLINTRSUMx(_rsum,_raddr,_whami) \ 1718013Sbinkertn@umich.edu nop; \ 1728013Sbinkertn@umich.edu mfpr _whami, pt_whami; /* Get our whami (VID) */ \ 1738013Sbinkertn@umich.edu extbl _whami, 1, _whami; /* shift down to bit 0 */ \ 1748013Sbinkertn@umich.edu lda _raddr, 0xff88(zero); /* Get base node space address bits */ \ 1758013Sbinkertn@umich.edu sll _raddr, 24, _raddr; /* Shift up to proper position */ \ 1768013Sbinkertn@umich.edu blbs _whami, 1f; \ 1778013Sbinkertn@umich.edu lda _raddr, 0x1180(_raddr); \ 1788013Sbinkertn@umich.edu br zero, 2f; \ 1798013Sbinkertn@umich.edu1: lda _raddr, 0x11c0(_raddr); \ 1808013Sbinkertn@umich.edu2: srl _whami, 1, _whami; /* Get our node offset */ \ 1818013Sbinkertn@umich.edu addq _raddr, _whami, _raddr; /* Get our base node space address */ \ 1828013Sbinkertn@umich.edu mb; \ 1838013Sbinkertn@umich.edu stq_p _rsum, 0(_raddr); /* write the right tlintrsum reg */ \ 1848013Sbinkertn@umich.edu ldq_p _rsum, 0(_raddr); /* dummy read to tlintrsum */ \ 1858013Sbinkertn@umich.edu bis _rsum, _rsum, _rsum /* needed to complete the ldqp above */ 1868013Sbinkertn@umich.edu 1878013Sbinkertn@umich.edu 1888013Sbinkertn@umich.edu// 1898013Sbinkertn@umich.edu// Macro to determine highest priority TIOP Node ID from interrupt pending mask 1908013Sbinkertn@umich.edu// 1918013Sbinkertn@umich.edu// Assumed register usage: 1928013Sbinkertn@umich.edu// rmask - TLINTRSUMx contents, shifted to isolate IOx bits 1938013Sbinkertn@umich.edu// rid - TLSB Node ID of highest TIOP 1948013Sbinkertn@umich.edu// 1958013Sbinkertn@umich.edu#define Intr_Find_TIOP(_rmask,_rid) \ 1968013Sbinkertn@umich.edu srl _rmask,3,_rid; /* check IOP8 */ \ 1978013Sbinkertn@umich.edu blbc _rid,1f; /* not IOP8 */ \ 1988013Sbinkertn@umich.edu lda _rid,8(zero); /* IOP8 */ \ 1998013Sbinkertn@umich.edu br zero,6f; \ 2008013Sbinkertn@umich.edu1: srl _rmask,3,_rid; /* check IOP7 */ \ 2018013Sbinkertn@umich.edu blbc _rid, 2f; /* not IOP7 */ \ 2028013Sbinkertn@umich.edu lda _rid, 7(r31); /* IOP7 */ \ 2038013Sbinkertn@umich.edu br r31, 6f; \ 2048013Sbinkertn@umich.edu2: srl _rmask, 2, _rid; /* check IOP6 */ \ 2058013Sbinkertn@umich.edu blbc _rid, 3f; /* not IOP6 */ \ 2068013Sbinkertn@umich.edu lda _rid, 6(r31); /* IOP6 */ \ 2078013Sbinkertn@umich.edu br r31, 6f; \ 2088013Sbinkertn@umich.edu3: srl _rmask, 1, _rid; /* check IOP5 */ \ 2098013Sbinkertn@umich.edu blbc _rid, 4f; /* not IOP5 */ \ 2108013Sbinkertn@umich.edu lda _rid, 5(r31); /* IOP5 */ \ 2118013Sbinkertn@umich.edu br r31, 6f; \ 2128013Sbinkertn@umich.edu4: srl _rmask, 0, _rid; /* check IOP4 */ \ 2138013Sbinkertn@umich.edu blbc _rid, 5f; /* not IOP4 */ \ 2148013Sbinkertn@umich.edu lda r14, 4(r31); /* IOP4 */ \ 2158013Sbinkertn@umich.edu br r31, 6f; \ 2168013Sbinkertn@umich.edu5: lda r14, 0(r31); /* passive release */ \ 2178013Sbinkertn@umich.edu6: 2188013Sbinkertn@umich.edu 2198013Sbinkertn@umich.edu// 2208013Sbinkertn@umich.edu// Macro to calculate base node space address for given node id 2218013Sbinkertn@umich.edu// 2228013Sbinkertn@umich.edu// Assumed register usage: 2238013Sbinkertn@umich.edu// rid - TLSB node id 2248013Sbinkertn@umich.edu// raddr - base node space address 2258013Sbinkertn@umich.edu#define Get_TLSB_Node_Address(_rid,_raddr) \ 2268013Sbinkertn@umich.edu sll _rid, 22, _rid; \ 2278013Sbinkertn@umich.edu lda _raddr, 0xff88(zero); \ 2288013Sbinkertn@umich.edu sll _raddr, 24, _raddr; \ 2298013Sbinkertn@umich.edu addq _raddr, _rid, _raddr 2308013Sbinkertn@umich.edu 2318013Sbinkertn@umich.edu 2328013Sbinkertn@umich.edu#define OSFmchk_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ 2338013Sbinkertn@umich.edu lda _rs1, tlep_##_tlepreg(zero); \ 2348013Sbinkertn@umich.edu or _rs1, _nodebase, _rs1; \ 2358013Sbinkertn@umich.edu ldl_p _rs1, 0(_rs1); \ 2368013Sbinkertn@umich.edu stl_p _rs, mchk_##_tlepreg(_rlog) /* store in frame */ 2378013Sbinkertn@umich.edu 2388013Sbinkertn@umich.edu#define OSFmchk_TLEPstore(_tlepreg) \ 2398013Sbinkertn@umich.edu OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg) 2408013Sbinkertn@umich.edu 2418013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ 2428013Sbinkertn@umich.edu lda _rs1, tlep_##_tlepreg(zero); \ 2438013Sbinkertn@umich.edu or _rs1, _nodebase, _rs1; \ 2448013Sbinkertn@umich.edu ldl_p _rs1, 0(_rs1); \ 2458013Sbinkertn@umich.edu stl_p _rs, mchk_crd_##_tlepreg(_rlog) 2468013Sbinkertn@umich.edu 2478013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_tlsb_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ 2488013Sbinkertn@umich.edu lda _rs1, tlsb_##_tlepreg(zero); \ 2498013Sbinkertn@umich.edu or _rs1, _nodebase, _rs1; \ 2508013Sbinkertn@umich.edu ldl_p _rs1, 0(_rs1); \ 2518013Sbinkertn@umich.edu stl_p _rs,mchk_crd_##_tlepreg(_rlog) 2528013Sbinkertn@umich.edu 2538013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_tlsb_clr_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ 2548013Sbinkertn@umich.edu lda _rs1,tlsb_##_tlepreg(zero); \ 2558013Sbinkertn@umich.edu or _rs1, _nodebase,_rs1; \ 2568013Sbinkertn@umich.edu ldl_p _rs1, 0(_rs1); \ 2578013Sbinkertn@umich.edu stl_p _rs, mchk_crd_##_tlepreg(_rlog); \ 2588013Sbinkertn@umich.edu stl_p _rs, 0(_rs1) 2598013Sbinkertn@umich.edu 2608013Sbinkertn@umich.edu#define OSFcrd_TLEPstore(_tlepreg) \ 2618013Sbinkertn@umich.edu OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg) 2628013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_tlsb(_tlepreg) \ 2638013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg) 2648013Sbinkertn@umich.edu#define OSFcrd_TLEPstore_tlsb_clr(_tlepreg) \ 2658013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg) 2668013Sbinkertn@umich.edu 2678013Sbinkertn@umich.edu 2688013Sbinkertn@umich.edu#define save_pcia_intr(_irq) \ 2698013Sbinkertn@umich.edu and r13, 0xf, r25; /* isolate low 4 bits */ \ 2708013Sbinkertn@umich.edu addq r14, 4, r14; /* format the TIOP Node id field */ \ 2718013Sbinkertn@umich.edu sll r14, 4, r14; /* shift the TIOP Node id */ \ 2728013Sbinkertn@umich.edu or r14, r25, r10; /* merge Node id/hose/HPC */ \ 2738013Sbinkertn@umich.edu mfpr r14, pt14; /* get saved value */ \ 2748013Sbinkertn@umich.edu extbl r14, _irq, r25; /* confirm none outstanding */ \ 2758013Sbinkertn@umich.edu bne r25, sys_machine_check_while_in_pal; \ 2768013Sbinkertn@umich.edu insbl r10, _irq, r10; /* align new info */ \ 2778013Sbinkertn@umich.edu or r14, r10, r14; /* merge info */ \ 2788013Sbinkertn@umich.edu mtpr r14, pt14; /* save it */ \ 2798013Sbinkertn@umich.edu bic r13, 0xf, r13 /* clear low 4 bits of vector */ 2808013Sbinkertn@umich.edu 2818013Sbinkertn@umich.edu 2828013Sbinkertn@umich.edu// wripir - PALcode for wripir instruction 2838013Sbinkertn@umich.edu// R16 has the processor number. 2848013Sbinkertn@umich.edu// 2858013Sbinkertn@umich.edu ALIGN_BLOCK 2868013Sbinkertn@umich.eduEXPORT(sys_wripir) 2878013Sbinkertn@umich.edu // 2888013Sbinkertn@umich.edu // Convert the processor number to a CPU mask 2898013Sbinkertn@umich.edu // 2908013Sbinkertn@umich.edu and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported 2918013Sbinkertn@umich.edu bis r31, 0x1, r16 // get a one 2928013Sbinkertn@umich.edu sll r16, r14, r14 // shift the bit to the right place 2938017Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 2948017Sbinkertn@umich.edu sll r14,IPIQ_shift,r14 2958017Sbinkertn@umich.edu#endif 2968017Sbinkertn@umich.edu 2978013Sbinkertn@umich.edu 2988013Sbinkertn@umich.edu // 2998013Sbinkertn@umich.edu // Build the Broadcast Space base address 3008013Sbinkertn@umich.edu // 3018017Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 3028017Sbinkertn@umich.edu lda r16,0xf01(r31) 3038017Sbinkertn@umich.edu sll r16,32,r16 3048017Sbinkertn@umich.edu ldah r13,0xa0(r31) 3058017Sbinkertn@umich.edu sll r13,8,r13 3068017Sbinkertn@umich.edu bis r16,r13,r16 3078017Sbinkertn@umich.edu lda r16,IPIQ_addr(r16) 3088017Sbinkertn@umich.edu#elif defined(TLASER) 3098013Sbinkertn@umich.edu lda r13, 0xff8e(r31) // Load the upper address bits 3108013Sbinkertn@umich.edu sll r13, 24, r13 // shift them to the top 3118017Sbinkertn@umich.edu#endif 3128013Sbinkertn@umich.edu 3138013Sbinkertn@umich.edu // 3148013Sbinkertn@umich.edu // Send out the IP Intr 3158013Sbinkertn@umich.edu // 3168017Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 3178017Sbinkertn@umich.edu stq_p r14, 0(r16) // Tsunami MISC Register 3188017Sbinkertn@umich.edu#elif defined(TLASER) 3198013Sbinkertn@umich.edu stq_p r14, 0x40(r13) // Write to TLIPINTR reg 3208017Sbinkertn@umich.edu#endif 3218013Sbinkertn@umich.edu wmb // Push out the store 3228013Sbinkertn@umich.edu hw_rei 3238013Sbinkertn@umich.edu 3248013Sbinkertn@umich.edu 3258013Sbinkertn@umich.edu// cflush - PALcode for CFLUSH instruction 3268013Sbinkertn@umich.edu// 3278013Sbinkertn@umich.edu// SYS_CFLUSH 3288013Sbinkertn@umich.edu// Entry: 3298013Sbinkertn@umich.edu// R16 - contains the PFN of the page to be flushed 3308013Sbinkertn@umich.edu// 3318013Sbinkertn@umich.edu// Function: 3328013Sbinkertn@umich.edu// Flush all Dstream caches of 1 entire page 3338013Sbinkertn@umich.edu// 3348013Sbinkertn@umich.edu// 3358013Sbinkertn@umich.edu ALIGN_BLOCK 3368013Sbinkertn@umich.eduEXPORT(sys_cflush) 3378013Sbinkertn@umich.edu 3388013Sbinkertn@umich.edu// #convert pfn to addr, and clean off <63:20> 3398013Sbinkertn@umich.edu// #sll r16, <page_offset_size_bits>+<63-20>>, r12 3408013Sbinkertn@umich.edu sll r16, page_offset_size_bits+(63-20),r12 3418013Sbinkertn@umich.edu 3428013Sbinkertn@umich.edu// #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16> 3438013Sbinkertn@umich.edu// # stolen from srcmax code. XXX bugnion 3448013Sbinkertn@umich.edu lda r13, 0x10(r31) // assume 16Mbytes of cache 3458013Sbinkertn@umich.edu sll r13, 20, r13 // convert to bytes 3468013Sbinkertn@umich.edu 3478013Sbinkertn@umich.edu 3488013Sbinkertn@umich.edu srl r12, 63-20, r12 // shift back to normal position 3498013Sbinkertn@umich.edu xor r12, r13, r12 // xor addr<18> 3508013Sbinkertn@umich.edu 3518013Sbinkertn@umich.edu or r31, 8192/(32*8), r13 // get count of loads 3528013Sbinkertn@umich.edu nop 3538013Sbinkertn@umich.edu 3548013Sbinkertn@umich.educflush_loop: 3558013Sbinkertn@umich.edu subq r13, 1, r13 // decr counter 3568013Sbinkertn@umich.edu mfpr r25, ev5__intid // Fetch level of interruptor 3578013Sbinkertn@umich.edu 3588013Sbinkertn@umich.edu ldq_p r31, 32*0(r12) // do a load 3598013Sbinkertn@umich.edu ldq_p r31, 32*1(r12) // do next load 3608013Sbinkertn@umich.edu 3618013Sbinkertn@umich.edu ldq_p r31, 32*2(r12) // do next load 3628013Sbinkertn@umich.edu ldq_p r31, 32*3(r12) // do next load 3638013Sbinkertn@umich.edu 3648013Sbinkertn@umich.edu ldq_p r31, 32*4(r12) // do next load 3658013Sbinkertn@umich.edu ldq_p r31, 32*5(r12) // do next load 3668013Sbinkertn@umich.edu 3678013Sbinkertn@umich.edu ldq_p r31, 32*6(r12) // do next load 3688013Sbinkertn@umich.edu ldq_p r31, 32*7(r12) // do next load 3698013Sbinkertn@umich.edu 3708013Sbinkertn@umich.edu mfpr r14, ev5__ipl // Fetch current level 3718013Sbinkertn@umich.edu lda r12, (32*8)(r12) // skip to next cache block addr 3728013Sbinkertn@umich.edu 3738013Sbinkertn@umich.edu cmple r25, r14, r25 // R25 = 1 if intid .less than or eql ipl 3748013Sbinkertn@umich.edu beq r25, 1f // if any int's pending, re-queue CFLUSH -- need to check for hlt interrupt??? 3758013Sbinkertn@umich.edu 3768013Sbinkertn@umich.edu bne r13, cflush_loop // loop till done 3778013Sbinkertn@umich.edu hw_rei // back to user 3788013Sbinkertn@umich.edu 3798013Sbinkertn@umich.edu ALIGN_BRANCH 3808013Sbinkertn@umich.edu1: // Here if interrupted 3818013Sbinkertn@umich.edu mfpr r12, exc_addr 3828013Sbinkertn@umich.edu subq r12, 4, r12 // Backup PC to point to CFLUSH 3838013Sbinkertn@umich.edu 3848013Sbinkertn@umich.edu mtpr r12, exc_addr 3858013Sbinkertn@umich.edu nop 3868013Sbinkertn@umich.edu 3878013Sbinkertn@umich.edu mfpr r31, pt0 // Pad exc_addr write 3888013Sbinkertn@umich.edu hw_rei 3898013Sbinkertn@umich.edu 3908013Sbinkertn@umich.edu 3918013Sbinkertn@umich.edu ALIGN_BLOCK 3928013Sbinkertn@umich.edu// 3938013Sbinkertn@umich.edu// sys_cserve - PALcode for CSERVE instruction 3948013Sbinkertn@umich.edu// 3958013Sbinkertn@umich.edu// Function: 3968013Sbinkertn@umich.edu// Various functions for private use of console software 3978013Sbinkertn@umich.edu// 3988013Sbinkertn@umich.edu// option selector in r0 3998013Sbinkertn@umich.edu// arguments in r16.... 4008013Sbinkertn@umich.edu// 4018013Sbinkertn@umich.edu// 4028013Sbinkertn@umich.edu// r0 = 0 unknown 4038013Sbinkertn@umich.edu// 4048013Sbinkertn@umich.edu// r0 = 1 ldq_p 4058013Sbinkertn@umich.edu// r0 = 2 stq_p 4068013Sbinkertn@umich.edu// args, are as for normal STQ_P/LDQ_P in VMS PAL 4078013Sbinkertn@umich.edu// 4088013Sbinkertn@umich.edu// r0 = 3 dump_tb's 4098013Sbinkertn@umich.edu// r16 = detination PA to dump tb's to. 4108013Sbinkertn@umich.edu// 4118013Sbinkertn@umich.edu// r0<0> = 1, success 4128013Sbinkertn@umich.edu// r0<0> = 0, failure, or option not supported 4138013Sbinkertn@umich.edu// r0<63:1> = (generally 0, but may be function dependent) 4148013Sbinkertn@umich.edu// r0 - load data on ldq_p 4158013Sbinkertn@umich.edu// 4168013Sbinkertn@umich.edu// 4178013Sbinkertn@umich.eduEXPORT(sys_cserve) 4188013Sbinkertn@umich.edu 4198013Sbinkertn@umich.edu /* taken from scrmax */ 4208013Sbinkertn@umich.edu cmpeq r18, CSERVE_K_RD_IMPURE, r0 4218013Sbinkertn@umich.edu bne r0, Sys_Cserve_Rd_Impure 4228013Sbinkertn@umich.edu 4238013Sbinkertn@umich.edu cmpeq r18, CSERVE_K_JTOPAL, r0 4248013Sbinkertn@umich.edu bne r0, Sys_Cserve_Jtopal 4258013Sbinkertn@umich.edu call_pal 0 4268013Sbinkertn@umich.edu 4278013Sbinkertn@umich.edu or r31, r31, r0 4288013Sbinkertn@umich.edu hw_rei // and back we go 4298013Sbinkertn@umich.edu 4308013Sbinkertn@umich.eduSys_Cserve_Rd_Impure: 4318013Sbinkertn@umich.edu mfpr r0, pt_impure // Get base of impure scratch area. 4328013Sbinkertn@umich.edu hw_rei 4338013Sbinkertn@umich.edu 4348013Sbinkertn@umich.edu ALIGN_BRANCH 4358013Sbinkertn@umich.edu 4368013Sbinkertn@umich.eduSys_Cserve_Jtopal: 4378013Sbinkertn@umich.edu bic a0, 3, t8 // Clear out low 2 bits of address 4388013Sbinkertn@umich.edu bis t8, 1, t8 // Or in PAL mode bit 4398013Sbinkertn@umich.edu mtpr t8,exc_addr 4408013Sbinkertn@umich.edu hw_rei 4418013Sbinkertn@umich.edu 4428013Sbinkertn@umich.edu // ldq_p 4438013Sbinkertn@umich.edu ALIGN_QUAD 4448013Sbinkertn@umich.edu1: 4458013Sbinkertn@umich.edu ldq_p r0,0(r17) // get the data 4468013Sbinkertn@umich.edu nop // pad palshadow write 4478013Sbinkertn@umich.edu 4488013Sbinkertn@umich.edu hw_rei // and back we go 4498013Sbinkertn@umich.edu 4508013Sbinkertn@umich.edu 4518013Sbinkertn@umich.edu // stq_p 4528013Sbinkertn@umich.edu ALIGN_QUAD 4538013Sbinkertn@umich.edu2: 4548013Sbinkertn@umich.edu stq_p r18, 0(r17) // store the data 4558013Sbinkertn@umich.edu lda r0,17(r31) // bogus 4568013Sbinkertn@umich.edu hw_rei // and back we go 4578013Sbinkertn@umich.edu 4588013Sbinkertn@umich.edu 4598013Sbinkertn@umich.edu ALIGN_QUAD 4608013Sbinkertn@umich.educsrv_callback: 4618013Sbinkertn@umich.edu ldq r16, 0(r17) // restore r16 4628013Sbinkertn@umich.edu ldq r17, 8(r17) // restore r17 4638013Sbinkertn@umich.edu lda r0, hlt_c_callback(r31) 4648013Sbinkertn@umich.edu br r31, sys_enter_console 4658013Sbinkertn@umich.edu 4668013Sbinkertn@umich.edu 4678013Sbinkertn@umich.educsrv_identify: 4688013Sbinkertn@umich.edu mfpr r0, pal_base 4698013Sbinkertn@umich.edu ldq_p r0, 8(r0) 4708013Sbinkertn@umich.edu hw_rei 4718013Sbinkertn@umich.edu 4728013Sbinkertn@umich.edu 4738013Sbinkertn@umich.edu// dump tb's 4748013Sbinkertn@umich.edu ALIGN_QUAD 4758013Sbinkertn@umich.edu0: 4768013Sbinkertn@umich.edu // DTB PTEs - 64 entries 4778013Sbinkertn@umich.edu addq r31, 64, r0 // initialize loop counter 4788013Sbinkertn@umich.edu nop 4798013Sbinkertn@umich.edu 4808013Sbinkertn@umich.edu1: mfpr r12, ev5__dtb_pte_temp // read out next pte to temp 4818013Sbinkertn@umich.edu mfpr r12, ev5__dtb_pte // read out next pte to reg file 4828013Sbinkertn@umich.edu 4838013Sbinkertn@umich.edu subq r0, 1, r0 // decrement loop counter 4848013Sbinkertn@umich.edu nop // Pad - no Mbox instr in cycle after mfpr 4858013Sbinkertn@umich.edu 4868013Sbinkertn@umich.edu stq_p r12, 0(r16) // store out PTE 4878013Sbinkertn@umich.edu addq r16, 8 ,r16 // increment pointer 4888013Sbinkertn@umich.edu 4898013Sbinkertn@umich.edu bne r0, 1b 4908013Sbinkertn@umich.edu 4918013Sbinkertn@umich.edu ALIGN_BRANCH 4928013Sbinkertn@umich.edu // ITB PTEs - 48 entries 4938013Sbinkertn@umich.edu addq r31, 48, r0 // initialize loop counter 4948013Sbinkertn@umich.edu nop 4958013Sbinkertn@umich.edu 4968013Sbinkertn@umich.edu2: mfpr r12, ev5__itb_pte_temp // read out next pte to temp 4978013Sbinkertn@umich.edu mfpr r12, ev5__itb_pte // read out next pte to reg file 4988013Sbinkertn@umich.edu 4998013Sbinkertn@umich.edu subq r0, 1, r0 // decrement loop counter 5008013Sbinkertn@umich.edu nop // 5018013Sbinkertn@umich.edu 5028013Sbinkertn@umich.edu stq_p r12, 0(r16) // store out PTE 5038013Sbinkertn@umich.edu addq r16, 8 ,r16 // increment pointer 5048013Sbinkertn@umich.edu 5058013Sbinkertn@umich.edu bne r0, 2b 5068013Sbinkertn@umich.edu or r31, 1, r0 // set success 5078013Sbinkertn@umich.edu 5088013Sbinkertn@umich.edu hw_rei // and back we go 5098013Sbinkertn@umich.edu 5108013Sbinkertn@umich.edu 5118013Sbinkertn@umich.edu// 5128013Sbinkertn@umich.edu// SYS_INTERRUPT - Interrupt processing code 5138013Sbinkertn@umich.edu// 5148013Sbinkertn@umich.edu// Current state: 5158013Sbinkertn@umich.edu// Stack is pushed 5168013Sbinkertn@umich.edu// ps, sp and gp are updated 5178013Sbinkertn@umich.edu// r12, r14 - available 5188013Sbinkertn@umich.edu// r13 - INTID (new EV5 IPL) 5198013Sbinkertn@umich.edu// r25 - ISR 5208013Sbinkertn@umich.edu// r16, r17, r18 - available 5218013Sbinkertn@umich.edu// 5228013Sbinkertn@umich.edu// 5238013Sbinkertn@umich.eduEXPORT(sys_interrupt) 5248013Sbinkertn@umich.edu cmpeq r13, 31, r12 // Check for level 31 interrupt 5258013Sbinkertn@umich.edu bne r12, sys_int_mchk_or_crd // machine check or crd 5268013Sbinkertn@umich.edu 5278013Sbinkertn@umich.edu cmpeq r13, 30, r12 // Check for level 30 interrupt 5288013Sbinkertn@umich.edu bne r12, sys_int_powerfail // powerfail 5298013Sbinkertn@umich.edu 5308013Sbinkertn@umich.edu cmpeq r13, 29, r12 // Check for level 29 interrupt 5318013Sbinkertn@umich.edu bne r12, sys_int_perf_cnt // performance counters 5328013Sbinkertn@umich.edu 5338013Sbinkertn@umich.edu cmpeq r13, 23, r12 // Check for level 23 interrupt 5348013Sbinkertn@umich.edu bne r12, sys_int_23 // IPI in Tsunami 5358013Sbinkertn@umich.edu 5368013Sbinkertn@umich.edu cmpeq r13, 22, r12 // Check for level 22 interrupt 5378013Sbinkertn@umich.edu bne r12, sys_int_22 // timer interrupt 5388013Sbinkertn@umich.edu 5398013Sbinkertn@umich.edu cmpeq r13, 21, r12 // Check for level 21 interrupt 5408013Sbinkertn@umich.edu bne r12, sys_int_21 // I/O 5418013Sbinkertn@umich.edu 5428013Sbinkertn@umich.edu cmpeq r13, 20, r12 // Check for level 20 interrupt 5438013Sbinkertn@umich.edu bne r12, sys_int_20 // system error interrupt 5448013Sbinkertn@umich.edu // (might be corrected) 5458013Sbinkertn@umich.edu 5468013Sbinkertn@umich.edu mfpr r14, exc_addr // ooops, something is wrong 5478013Sbinkertn@umich.edu br r31, pal_pal_bug_check_from_int 5488013Sbinkertn@umich.edu 5498013Sbinkertn@umich.edu 5508013Sbinkertn@umich.edu// 5518013Sbinkertn@umich.edu//sys_int_2* 5528013Sbinkertn@umich.edu// Routines to handle device interrupts at IPL 23-20. 5538013Sbinkertn@umich.edu// System specific method to ack/clear the interrupt, detect passive 5548013Sbinkertn@umich.edu// release, detect interprocessor (22), interval clock (22), corrected 5558013Sbinkertn@umich.edu// system error (20) 5568013Sbinkertn@umich.edu// 5578013Sbinkertn@umich.edu// Current state: 5588013Sbinkertn@umich.edu// Stack is pushed 5598013Sbinkertn@umich.edu// ps, sp and gp are updated 5608013Sbinkertn@umich.edu// r12, r14 - available 5618013Sbinkertn@umich.edu// r13 - INTID (new EV5 IPL) 5628013Sbinkertn@umich.edu// r25 - ISR 5638013Sbinkertn@umich.edu// 5648013Sbinkertn@umich.edu// On exit: 5658013Sbinkertn@umich.edu// Interrupt has been ack'd/cleared 5668013Sbinkertn@umich.edu// a0/r16 - signals IO device interrupt 5678013Sbinkertn@umich.edu// a1/r17 - contains interrupt vector 5688013Sbinkertn@umich.edu// exit to ent_int address 5698013Sbinkertn@umich.edu// 5708013Sbinkertn@umich.edu// 5718013Sbinkertn@umich.edu 5728013Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 5738013Sbinkertn@umich.edu ALIGN_BRANCH 5748013Sbinkertn@umich.edusys_int_23: 5758013Sbinkertn@umich.edu or r31,0,r16 // IPI interrupt A0 = 0 5768013Sbinkertn@umich.edu lda r12,0xf01(r31) // build up an address for the MISC register 5778013Sbinkertn@umich.edu sll r12,16,r12 5788013Sbinkertn@umich.edu lda r12,0xa000(r12) 5798013Sbinkertn@umich.edu sll r12,16,r12 5808013Sbinkertn@umich.edu lda r12,IPIR_addr(r12) 5818013Sbinkertn@umich.edu 5828013Sbinkertn@umich.edu mfpr r10, pt_whami // get CPU ID 5838013Sbinkertn@umich.edu extbl r10, 1, r10 // Isolate just whami bits 5848013Sbinkertn@umich.edu or r31,0x1,r14 // load r14 with bit to clear 5858013Sbinkertn@umich.edu sll r14,r10,r14 // left shift by CPU ID 5868013Sbinkertn@umich.edu sll r14,IPIR_shift,r14 5878013Sbinkertn@umich.edu stq_p r14, 0(r12) // clear the ipi interrupt 5888013Sbinkertn@umich.edu 5898013Sbinkertn@umich.edu br r31, pal_post_interrupt // Notify the OS 5908013Sbinkertn@umich.edu 5918013Sbinkertn@umich.edu 5928013Sbinkertn@umich.edu ALIGN_BRANCH 5938013Sbinkertn@umich.edusys_int_22: 5948013Sbinkertn@umich.edu or r31,1,r16 // a0 means it is a clock interrupt 5958013Sbinkertn@umich.edu lda r12,0xf01(r31) // build up an address for the MISC register 5968013Sbinkertn@umich.edu sll r12,16,r12 5978013Sbinkertn@umich.edu lda r12,0xa000(r12) 5988013Sbinkertn@umich.edu sll r12,16,r12 5998013Sbinkertn@umich.edu lda r12,RTC_addr(r12) 6008013Sbinkertn@umich.edu 6018013Sbinkertn@umich.edu mfpr r10, pt_whami // get CPU ID 6028013Sbinkertn@umich.edu extbl r10, 1, r10 // Isolate just whami bits 6038013Sbinkertn@umich.edu or r31,0x1,r14 // load r14 with bit to clear 6048013Sbinkertn@umich.edu sll r14,r10,r14 // left shift by CPU ID 6058013Sbinkertn@umich.edu sll r14,RTC_shift,r14 // put the bits in the right position 6068013Sbinkertn@umich.edu stq_p r14, 0(r12) // clear the rtc interrupt 6078013Sbinkertn@umich.edu 6088013Sbinkertn@umich.edu br r31, pal_post_interrupt // Tell the OS 6098013Sbinkertn@umich.edu 6108013Sbinkertn@umich.edu 6118013Sbinkertn@umich.edu ALIGN_BRANCH 6128013Sbinkertn@umich.edusys_int_20: 6138013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 6148013Sbinkertn@umich.edu srl r13, 12, r13 // shift down to examine IPL15 6158013Sbinkertn@umich.edu 6168013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 6178013Sbinkertn@umich.edu beq r14, 1f 6188013Sbinkertn@umich.edu 6198013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 6208013Sbinkertn@umich.edu lda r10, 0xa40(r10) // Get base TLILID address 6218013Sbinkertn@umich.edu 6228013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 6238013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 6248013Sbinkertn@umich.edu beq r13, 1f 6258013Sbinkertn@umich.edu 6268013Sbinkertn@umich.edu and r13, 0x3, r10 // check for PCIA bits 6278013Sbinkertn@umich.edu beq r10, pal_post_dev_interrupt // done if nothing set 6288013Sbinkertn@umich.edu save_pcia_intr(1) 6298013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // 6308013Sbinkertn@umich.edu 6318013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 6328013Sbinkertn@umich.edu br r31, pal_post_interrupt // 6338013Sbinkertn@umich.edu 6348013Sbinkertn@umich.edu 6358013Sbinkertn@umich.edu ALIGN_BRANCH 6368013Sbinkertn@umich.edusys_int_21: 6378013Sbinkertn@umich.edu 6388013Sbinkertn@umich.edu lda r12,0xf01(r31) // calculate DIRn address 6398013Sbinkertn@umich.edu sll r12,32,r12 6408013Sbinkertn@umich.edu ldah r13,DIR_addr(r31) 6418013Sbinkertn@umich.edu sll r13,8,r13 6428013Sbinkertn@umich.edu bis r12,r13,r12 6438013Sbinkertn@umich.edu 6448013Sbinkertn@umich.edu mfpr r13, pt_whami // get CPU ID 6458013Sbinkertn@umich.edu extbl r13, 1, r13 // Isolate just whami bits 6468013Sbinkertn@umich.edu 6478013Sbinkertn@umich.edu#ifdef BIG_TSUNAMI 6488013Sbinkertn@umich.edu sll r13,4,r13 6498013Sbinkertn@umich.edu or r12,r13,r12 6508013Sbinkertn@umich.edu#else 6518013Sbinkertn@umich.edu lda r12,0x0080(r12) 6528013Sbinkertn@umich.edu and r13,0x1,r14 // grab LSB and shift left 6 6538013Sbinkertn@umich.edu sll r14,6,r14 6548013Sbinkertn@umich.edu and r13,0x2,r10 // grabl LSB+1 and shift left 9 6558013Sbinkertn@umich.edu sll r10,9,r10 6568013Sbinkertn@umich.edu 6578013Sbinkertn@umich.edu mskbl r12,0,r12 // calculate DIRn address 6588013Sbinkertn@umich.edu lda r13,0x280(r31) 6598013Sbinkertn@umich.edu bis r12,r13,r12 6608013Sbinkertn@umich.edu or r12,r14,r12 6618013Sbinkertn@umich.edu or r12,r10,r12 6628013Sbinkertn@umich.edu#endif 6638013Sbinkertn@umich.edu 6648013Sbinkertn@umich.edu ldq_p r13, 0(r12) // read DIRn 6658013Sbinkertn@umich.edu 6668013Sbinkertn@umich.edu or r31,1,r14 // set bit 55 (ISA Interrupt) 6678013Sbinkertn@umich.edu sll r14,55,r14 6688013Sbinkertn@umich.edu 6698013Sbinkertn@umich.edu and r13, r14, r14 // check if bit 55 is set 6708013Sbinkertn@umich.edu lda r16,0x900(r31) // load offset for normal into r13 6718013Sbinkertn@umich.edu beq r14, normal_int // if not compute the vector normally 6728013Sbinkertn@umich.edu 6738013Sbinkertn@umich.edu lda r16,0x800(r31) // replace with offset for pic 6748013Sbinkertn@umich.edu lda r12,0xf01(r31) // build an addr to access PIC 6758013Sbinkertn@umich.edu sll r12,32,r12 // at f01fc000000 6768013Sbinkertn@umich.edu ldah r13,0xfc(r31) 6778013Sbinkertn@umich.edu sll r13,8,r13 6788013Sbinkertn@umich.edu bis r12,r13,r12 6798013Sbinkertn@umich.edu ldq_p r13,0x0020(r12) // read PIC1 ISR for interrupting dev 6808013Sbinkertn@umich.edu 6818013Sbinkertn@umich.edunormal_int: 6828013Sbinkertn@umich.edu //ctlz r13,r14 // count the number of leading zeros 6838013Sbinkertn@umich.edu // EV5 doesn't have ctlz, but we do, so lets use it 6848013Sbinkertn@umich.edu .byte 0x4e 6858013Sbinkertn@umich.edu .byte 0x06 6868013Sbinkertn@umich.edu .byte 0xed 6878013Sbinkertn@umich.edu .byte 0x73 6888013Sbinkertn@umich.edu lda r10,63(r31) 6898013Sbinkertn@umich.edu subq r10,r14,r17 // subtract from 6908013Sbinkertn@umich.edu 6918013Sbinkertn@umich.edu lda r13,0x10(r31) 6928013Sbinkertn@umich.edu mulq r17,r13,r17 // compute 0x900 + (0x10 * Highest DIRn-bit) 6938013Sbinkertn@umich.edu addq r17,r16,r17 6948013Sbinkertn@umich.edu 6958013Sbinkertn@umich.edu or r31,3,r16 // a0 means it is a I/O interrupt 6968013Sbinkertn@umich.edu 6978013Sbinkertn@umich.edu br r31, pal_post_interrupt 6988013Sbinkertn@umich.edu 6998013Sbinkertn@umich.edu#elif defined(TLASER) 7008013Sbinkertn@umich.edu ALIGN_BRANCH 7018013Sbinkertn@umich.edusys_int_23: 7028013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 7038013Sbinkertn@umich.edu srl r13, 22, r13 // shift down to examine IPL17 7048013Sbinkertn@umich.edu 7058013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 7068013Sbinkertn@umich.edu beq r14, 1f 7078013Sbinkertn@umich.edu 7088013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 7098013Sbinkertn@umich.edu lda r10, 0xac0(r10) // Get base TLILID address 7108013Sbinkertn@umich.edu 7118013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 7128013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 7138013Sbinkertn@umich.edu 7148013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 7158013Sbinkertn@umich.edu br r31, pal_post_interrupt // 7168013Sbinkertn@umich.edu 7178013Sbinkertn@umich.edu 7188013Sbinkertn@umich.edu ALIGN_BRANCH 7198013Sbinkertn@umich.edusys_int_22: 7208013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 7218013Sbinkertn@umich.edu srl r13, 6, r14 // check the Intim bit 7228013Sbinkertn@umich.edu 7238013Sbinkertn@umich.edu blbs r14, tlep_intim // go service Intim 7248013Sbinkertn@umich.edu srl r13, 5, r14 // check the IP Int bit 7258013Sbinkertn@umich.edu 7268013Sbinkertn@umich.edu blbs r14, tlep_ipint // go service IP Int 7278013Sbinkertn@umich.edu srl r13, 17, r13 // shift down to examine IPL16 7288013Sbinkertn@umich.edu 7298013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 7308013Sbinkertn@umich.edu beq r14, 1f 7318013Sbinkertn@umich.edu 7328013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 7338013Sbinkertn@umich.edu lda r10, 0xa80(r10) // Get base TLILID address 7348013Sbinkertn@umich.edu 7358013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 7368013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 7378013Sbinkertn@umich.edu beq r13, 1f 7388013Sbinkertn@umich.edu 7398013Sbinkertn@umich.edu and r13, 0x3, r10 // check for PCIA bits 7408013Sbinkertn@umich.edu beq r10, pal_post_dev_interrupt // done if nothing set 7418013Sbinkertn@umich.edu save_pcia_intr(2) 7428013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // 7438013Sbinkertn@umich.edu 7448013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 7458013Sbinkertn@umich.edu br r31, pal_post_interrupt // 7468013Sbinkertn@umich.edu 7478013Sbinkertn@umich.edu 7488013Sbinkertn@umich.edu ALIGN_BRANCH 7498013Sbinkertn@umich.edusys_int_21: 7508013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 7518013Sbinkertn@umich.edu srl r13, 12, r13 // shift down to examine IPL15 7528013Sbinkertn@umich.edu 7538013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 7548013Sbinkertn@umich.edu beq r14, 1f 7558013Sbinkertn@umich.edu 7568013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 7578013Sbinkertn@umich.edu lda r10, 0xa40(r10) // Get base TLILID address 7588013Sbinkertn@umich.edu 7598013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 7608013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 7618013Sbinkertn@umich.edu beq r13, 1f 7628013Sbinkertn@umich.edu 7638013Sbinkertn@umich.edu and r13, 0x3, r10 // check for PCIA bits 7648013Sbinkertn@umich.edu beq r10, pal_post_dev_interrupt // done if nothing set 7658013Sbinkertn@umich.edu save_pcia_intr(1) 7668013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // 7678013Sbinkertn@umich.edu 7688013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 7698013Sbinkertn@umich.edu br r31, pal_post_interrupt // 7708013Sbinkertn@umich.edu 7718013Sbinkertn@umich.edu 7728013Sbinkertn@umich.edu ALIGN_BRANCH 7738013Sbinkertn@umich.edusys_int_20: 7748013Sbinkertn@umich.edu lda r13, 1(r31) // Duart0 bit 7758013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit 7768013Sbinkertn@umich.edu 7778013Sbinkertn@umich.edu Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx 7788013Sbinkertn@umich.edu blbs r13, tlep_uart0 // go service UART int 7798013Sbinkertn@umich.edu 7808013Sbinkertn@umich.edu srl r13, 7, r13 // shift down to examine IPL14 7818013Sbinkertn@umich.edu Intr_Find_TIOP(r13,r14) 7828013Sbinkertn@umich.edu 7838013Sbinkertn@umich.edu beq r14, tlep_ecc // Branch if not IPL14 7848013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) 7858013Sbinkertn@umich.edu 7868013Sbinkertn@umich.edu lda r10, 0xa00(r10) // Get base TLILID0 address 7878013Sbinkertn@umich.edu ldl_p r13, 0(r10) // Read the TLILID register 7888013Sbinkertn@umich.edu 7898013Sbinkertn@umich.edu bne r13, pal_post_dev_interrupt 7908013Sbinkertn@umich.edu beq r13, 1f 7918013Sbinkertn@umich.edu 7928013Sbinkertn@umich.edu and r13, 0x3, r10 // check for PCIA bits 7938013Sbinkertn@umich.edu beq r10, pal_post_dev_interrupt // done if nothing set 7948013Sbinkertn@umich.edu save_pcia_intr(0) 7958013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // 7968013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 7978013Sbinkertn@umich.edu br r31, pal_post_interrupt // 7988013Sbinkertn@umich.edu 7998013Sbinkertn@umich.edu 8008013Sbinkertn@umich.edu ALIGN_BRANCH 8018013Sbinkertn@umich.edutlep_intim: 8028013Sbinkertn@umich.edu lda r13, 0xffb(r31) // get upper GBUS address bits 8038013Sbinkertn@umich.edu sll r13, 28, r13 // shift up to top 8048013Sbinkertn@umich.edu 8058013Sbinkertn@umich.edu lda r13, (0x300)(r13) // full CSRC address (tlep watch csrc offset) 8068013Sbinkertn@umich.edu ldq_p r13, 0(r13) // read CSRC 8078013Sbinkertn@umich.edu 8088013Sbinkertn@umich.edu lda r13, 0x40(r31) // load Intim bit 8098013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the Intim bit 8108013Sbinkertn@umich.edu 8118013Sbinkertn@umich.edu lda r16, osfint_c_clk(r31) // passive release 8128013Sbinkertn@umich.edu br r31, pal_post_interrupt // Build the stack frame 8138013Sbinkertn@umich.edu 8148013Sbinkertn@umich.edu 8158013Sbinkertn@umich.edu ALIGN_BRANCH 8168013Sbinkertn@umich.edutlep_ipint: 8178013Sbinkertn@umich.edu lda r13, 0x20(r31) // load IP Int bit 8188013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the IP Int bit 8198013Sbinkertn@umich.edu 8208013Sbinkertn@umich.edu lda r16, osfint_c_ip(r31) // passive release 8218013Sbinkertn@umich.edu br r31, pal_post_interrupt // Build the stack frame 8228013Sbinkertn@umich.edu 8238013Sbinkertn@umich.edu 8248013Sbinkertn@umich.edu ALIGN_BRANCH 8258013Sbinkertn@umich.edutlep_uart0: 8268013Sbinkertn@umich.edu lda r13, 0xffa(r31) // get upper GBUS address bits 8278013Sbinkertn@umich.edu sll r13, 28, r13 // shift up to top 8288013Sbinkertn@umich.edu 8298013Sbinkertn@umich.edu ldl_p r14, 0x80(r13) // zero pointer register 8308013Sbinkertn@umich.edu lda r14, 3(r31) // index to RR3 8318013Sbinkertn@umich.edu 8328013Sbinkertn@umich.edu stl_p r14, 0x80(r13) // write pointer register 8338013Sbinkertn@umich.edu mb 8348013Sbinkertn@umich.edu 8358013Sbinkertn@umich.edu mb 8368013Sbinkertn@umich.edu ldl_p r14, 0x80(r13) // read RR3 8378013Sbinkertn@umich.edu 8388013Sbinkertn@umich.edu srl r14, 5, r10 // is it Channel A RX? 8398013Sbinkertn@umich.edu blbs r10, uart0_rx 8408013Sbinkertn@umich.edu 8418013Sbinkertn@umich.edu srl r14, 4, r10 // is it Channel A TX? 8428013Sbinkertn@umich.edu blbs r10, uart0_tx 8438013Sbinkertn@umich.edu 8448013Sbinkertn@umich.edu srl r14, 2, r10 // is it Channel B RX? 8458013Sbinkertn@umich.edu blbs r10, uart1_rx 8468013Sbinkertn@umich.edu 8478013Sbinkertn@umich.edu srl r14, 1, r10 // is it Channel B TX? 8488013Sbinkertn@umich.edu blbs r10, uart1_tx 8498013Sbinkertn@umich.edu 8508013Sbinkertn@umich.edu lda r8, 0(r31) // passive release 8518013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8528013Sbinkertn@umich.edu 8538013Sbinkertn@umich.edu 8548013Sbinkertn@umich.edu ALIGN_BRANCH 8558013Sbinkertn@umich.eduuart0_rx: 8568013Sbinkertn@umich.edu lda r8, 0x680(r31) // UART0 RX vector 8578013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8588013Sbinkertn@umich.edu 8598013Sbinkertn@umich.edu 8608013Sbinkertn@umich.edu ALIGN_BRANCH 8618013Sbinkertn@umich.eduuart0_tx: 8628013Sbinkertn@umich.edu lda r14, 0x28(r31) // Reset TX Int Pending code 8638013Sbinkertn@umich.edu mb 8648013Sbinkertn@umich.edu stl_p r14, 0x80(r13) // write Channel A WR0 8658013Sbinkertn@umich.edu mb 8668013Sbinkertn@umich.edu 8678013Sbinkertn@umich.edu lda r8, 0x6c0(r31) // UART0 TX vector 8688013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8698013Sbinkertn@umich.edu 8708013Sbinkertn@umich.edu 8718013Sbinkertn@umich.edu ALIGN_BRANCH 8728013Sbinkertn@umich.eduuart1_rx: 8738013Sbinkertn@umich.edu lda r8, 0x690(r31) // UART1 RX vector 8748013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8758013Sbinkertn@umich.edu 8768013Sbinkertn@umich.edu 8778013Sbinkertn@umich.edu ALIGN_BRANCH 8788013Sbinkertn@umich.eduuart1_tx: 8798013Sbinkertn@umich.edu lda r14, 0x28(r31) // Reset TX Int Pending code 8808013Sbinkertn@umich.edu stl_p r14, 0(r13) // write Channel B WR0 8818013Sbinkertn@umich.edu 8828013Sbinkertn@umich.edu lda r8, 0x6d0(r31) // UART1 TX vector 8838013Sbinkertn@umich.edu br r31, clear_duart0_int // clear tlintrsum and post 8848013Sbinkertn@umich.edu 8858013Sbinkertn@umich.edu 8868013Sbinkertn@umich.edu ALIGN_BRANCH 8878013Sbinkertn@umich.educlear_duart0_int: 8888013Sbinkertn@umich.edu lda r13, 1(r31) // load duart0 bit 8898013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit 8908013Sbinkertn@umich.edu 8918013Sbinkertn@umich.edu beq r8, 1f 8928013Sbinkertn@umich.edu or r8, r31, r13 // move vector to r13 8938013Sbinkertn@umich.edu br r31, pal_post_dev_interrupt // Build the stack frame 8948013Sbinkertn@umich.edu1: nop 8958013Sbinkertn@umich.edu nop 8968013Sbinkertn@umich.edu hw_rei 8978013Sbinkertn@umich.edu// lda r16, osfint_c_passrel(r31) // passive release 8988013Sbinkertn@umich.edu// br r31, pal_post_interrupt // 8998013Sbinkertn@umich.edu 9008013Sbinkertn@umich.edu 9018013Sbinkertn@umich.edu ALIGN_BRANCH 9028013Sbinkertn@umich.edutlep_ecc: 9038013Sbinkertn@umich.edu mfpr r14, pt_whami // get our node id 9048013Sbinkertn@umich.edu extbl r14, 1, r14 // shift to bit 0 9058013Sbinkertn@umich.edu 9068013Sbinkertn@umich.edu srl r14, 1, r14 // shift off cpu number 9078013Sbinkertn@umich.edu Get_TLSB_Node_Address(r14,r10) // compute our nodespace address 9088013Sbinkertn@umich.edu 9098013Sbinkertn@umich.edu ldl_p r13, 0x40(r10) // read our TLBER WAS tlsb_tlber_offset 9108013Sbinkertn@umich.edu srl r13, 17, r13 // shift down the CWDE/CRDE bits 9118013Sbinkertn@umich.edu 9128013Sbinkertn@umich.edu and r13, 3, r13 // mask the CWDE/CRDE bits 9138013Sbinkertn@umich.edu beq r13, 1f 9148013Sbinkertn@umich.edu 9158013Sbinkertn@umich.edu ornot r31, r31, r12 // set flag 9168013Sbinkertn@umich.edu lda r9, mchk_c_sys_ecc(r31) // System Correctable error MCHK code 9178013Sbinkertn@umich.edu br r31, sys_merge_sys_corr // jump to CRD logout frame code 9188013Sbinkertn@umich.edu 9198013Sbinkertn@umich.edu1: lda r16, osfint_c_passrel(r31) // passive release 9208013Sbinkertn@umich.edu 9218013Sbinkertn@umich.edu#endif // if TSUNAMI || BIG_TSUNAMI elif TLASER 9228013Sbinkertn@umich.edu 9238013Sbinkertn@umich.edu ALIGN_BRANCH 9248013Sbinkertn@umich.edupal_post_dev_interrupt: 9258013Sbinkertn@umich.edu or r13, r31, r17 // move vector to a1 9268013Sbinkertn@umich.edu or r31, osfint_c_dev, r16 // a0 signals IO device interrupt 9278013Sbinkertn@umich.edu 9288013Sbinkertn@umich.edupal_post_interrupt: 9298013Sbinkertn@umich.edu mfpr r12, pt_entint 9308013Sbinkertn@umich.edu 9318013Sbinkertn@umich.edu mtpr r12, exc_addr 9328013Sbinkertn@umich.edu 9338013Sbinkertn@umich.edu nop 9348013Sbinkertn@umich.edu nop 9358013Sbinkertn@umich.edu 9368013Sbinkertn@umich.edu hw_rei_spe 9378013Sbinkertn@umich.edu 9388013Sbinkertn@umich.edu 9398013Sbinkertn@umich.edu// 9408013Sbinkertn@umich.edu// sys_passive_release 9418013Sbinkertn@umich.edu// Just pretend the interrupt never occurred. 9428013Sbinkertn@umich.edu// 9438013Sbinkertn@umich.edu 9448013Sbinkertn@umich.eduEXPORT(sys_passive_release) 9458013Sbinkertn@umich.edu mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps 9468013Sbinkertn@umich.edu nop 9478013Sbinkertn@umich.edu 9488013Sbinkertn@umich.edu mfpr r31, pt0 // Pad write to dtb_cm 9498013Sbinkertn@umich.edu hw_rei 9508013Sbinkertn@umich.edu 9518013Sbinkertn@umich.edu// 9528013Sbinkertn@umich.edu// sys_int_powerfail 9538013Sbinkertn@umich.edu// A powerfail interrupt has been detected. The stack has been pushed. 9548013Sbinkertn@umich.edu// IPL and PS are updated as well. 9558013Sbinkertn@umich.edu// 9568013Sbinkertn@umich.edu// I'm not sure what to do here, I'm treating it as an IO device interrupt 9578013Sbinkertn@umich.edu// 9588013Sbinkertn@umich.edu// 9598013Sbinkertn@umich.edu 9608013Sbinkertn@umich.edu ALIGN_BLOCK 9618013Sbinkertn@umich.edusys_int_powerfail: 9628013Sbinkertn@umich.edu lda r12, 0xffc4(r31) // get GBUS_MISCR address bits 9638013Sbinkertn@umich.edu sll r12, 24, r12 // shift to proper position 9648013Sbinkertn@umich.edu ldq_p r12, 0(r12) // read GBUS_MISCR 9658013Sbinkertn@umich.edu srl r12, 5, r12 // isolate bit <5> 9668013Sbinkertn@umich.edu blbc r12, 1f // if clear, no missed mchk 9678013Sbinkertn@umich.edu 9688013Sbinkertn@umich.edu // Missed a CFAIL mchk 9698013Sbinkertn@umich.edu lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits 9708013Sbinkertn@umich.edu sll r13, 24, r13 // shift to proper position 9718013Sbinkertn@umich.edu lda r14, 0x40(r31) // get bit <6> mask 9728013Sbinkertn@umich.edu ldq_p r12, 0(r13) // read GBUS$SERNUM 9738013Sbinkertn@umich.edu or r12, r14, r14 // set bit <6> 9748013Sbinkertn@umich.edu stq_p r14, 0(r13) // clear GBUS$SERNUM<6> 9758013Sbinkertn@umich.edu mb 9768013Sbinkertn@umich.edu mb 9778013Sbinkertn@umich.edu 9788013Sbinkertn@umich.edu1: br r31, sys_int_mchk // do a machine check 9798013Sbinkertn@umich.edu 9808013Sbinkertn@umich.edu lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector 9818013Sbinkertn@umich.edu mfpr r25, pt_entint 9828013Sbinkertn@umich.edu 9838013Sbinkertn@umich.edu lda r16, osfint_c_dev(r31) // a0 to device code 9848013Sbinkertn@umich.edu mtpr r25, exc_addr 9858013Sbinkertn@umich.edu 9868013Sbinkertn@umich.edu nop // pad exc_addr write 9878013Sbinkertn@umich.edu nop 9888013Sbinkertn@umich.edu 9898013Sbinkertn@umich.edu hw_rei_spe 9908013Sbinkertn@umich.edu 9918013Sbinkertn@umich.edu// 9928013Sbinkertn@umich.edu// sys_halt_interrupt 9938013Sbinkertn@umich.edu// A halt interrupt has been detected. Pass control to the console. 9948013Sbinkertn@umich.edu// 9958013Sbinkertn@umich.edu// 9968013Sbinkertn@umich.edu// 9978013Sbinkertn@umich.edu EXPORT(sys_halt_interrupt) 9988013Sbinkertn@umich.edu 9998013Sbinkertn@umich.edu ldah r13, 0x1800(r31) // load Halt/^PHalt bits 10008013Sbinkertn@umich.edu Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits 10018013Sbinkertn@umich.edu 10028013Sbinkertn@umich.edu mtpr r11, dtb_cm // Restore Mbox current mode 10038013Sbinkertn@umich.edu nop 10048013Sbinkertn@umich.edu nop 10058013Sbinkertn@umich.edu mtpr r0, pt0 10068013Sbinkertn@umich.edu lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt 10078013Sbinkertn@umich.edu br r31, sys_enter_console // enter the console 10088013Sbinkertn@umich.edu 10098013Sbinkertn@umich.edu 10108013Sbinkertn@umich.edu 10118013Sbinkertn@umich.edu// 10128013Sbinkertn@umich.edu// sys_int_mchk_or_crd 10138013Sbinkertn@umich.edu// 10148013Sbinkertn@umich.edu// Current state: 10158013Sbinkertn@umich.edu// Stack is pushed 10168013Sbinkertn@umich.edu// ps, sp and gp are updated 10178013Sbinkertn@umich.edu// r12 10188013Sbinkertn@umich.edu// r13 - INTID (new EV5 IPL) 10198013Sbinkertn@umich.edu// r14 - exc_addr 10208013Sbinkertn@umich.edu// r25 - ISR 10218013Sbinkertn@umich.edu// r16, r17, r18 - available 10228013Sbinkertn@umich.edu// 10238013Sbinkertn@umich.edu// 10248013Sbinkertn@umich.edu ALIGN_BLOCK 10258013Sbinkertn@umich.edusys_int_mchk_or_crd: 10268013Sbinkertn@umich.edu srl r25, isr_v_mck, r12 10278013Sbinkertn@umich.edu blbs r12, sys_int_mchk 10288013Sbinkertn@umich.edu // 10298013Sbinkertn@umich.edu // Not a Machine check interrupt, so must be an Internal CRD interrupt 10308013Sbinkertn@umich.edu // 10318013Sbinkertn@umich.edu 10328013Sbinkertn@umich.edu mb //Clear out Cbox prior to reading IPRs 10338013Sbinkertn@umich.edu srl r25, isr_v_crd, r13 //Check for CRD 10348013Sbinkertn@umich.edu blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!! 10358013Sbinkertn@umich.edu 10368013Sbinkertn@umich.edu lda r9, 1(r31) 10378013Sbinkertn@umich.edu sll r9, hwint_clr_v_crdc, r9 // get ack bit for crd 10388013Sbinkertn@umich.edu mtpr r9, ev5__hwint_clr // ack the crd interrupt 10398013Sbinkertn@umich.edu 10408013Sbinkertn@umich.edu or r31, r31, r12 // clear flag 10418013Sbinkertn@umich.edu lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code 10428013Sbinkertn@umich.edu 10438013Sbinkertn@umich.edusys_merge_sys_corr: 10448013Sbinkertn@umich.edu ldah r14, 0xfff0(r31) 10458013Sbinkertn@umich.edu mtpr r0, pt0 // save r0 for scratch 10468013Sbinkertn@umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 10478013Sbinkertn@umich.edu mtpr r1, pt1 // save r0 for scratch 10488013Sbinkertn@umich.edu 10498013Sbinkertn@umich.edu ldq_p r0, ei_addr(r14) // EI_ADDR IPR 10508013Sbinkertn@umich.edu ldq_p r10, fill_syn(r14) // FILL_SYN IPR 10518013Sbinkertn@umich.edu bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub 10528013Sbinkertn@umich.edu 10538013Sbinkertn@umich.edu blbs r12, 1f // no scrubbing for IRQ0 case 10548013Sbinkertn@umich.edu// XXX bugnion pvc_jsr crd_scrub_mem, bsr=1 10558013Sbinkertn@umich.edu bsr r13, sys_crd_scrub_mem // and go scrub 10568013Sbinkertn@umich.edu 10578013Sbinkertn@umich.edu // ld/st pair in scrub routine will have finished due 10588013Sbinkertn@umich.edu // to ibox stall of stx_c. Don't need another mb. 10598013Sbinkertn@umich.edu ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN 10608013Sbinkertn@umich.edu or r8, r31, r12 // Must only be executed once in this flow, and must 10618013Sbinkertn@umich.edu br r31, 2f // be after the scrub routine. 10628013Sbinkertn@umich.edu 10638013Sbinkertn@umich.edu1: ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN 10648013Sbinkertn@umich.edu // For IRQ0 CRD case only - meaningless data. 10658013Sbinkertn@umich.edu 10668013Sbinkertn@umich.edu2: mfpr r13, pt_mces // Get MCES 10678013Sbinkertn@umich.edu srl r12, ei_stat_v_ei_es, r14 // Isolate EI_STAT:EI_ES 10688013Sbinkertn@umich.edu blbc r14, 6f // branch if 630 10698013Sbinkertn@umich.edu srl r13, mces_v_dsc, r14 // check if 620 reporting disabled 10708013Sbinkertn@umich.edu blbc r14, 5f // branch if enabled 10718013Sbinkertn@umich.edu or r13, r31, r14 // don't set SCE if disabled 10728013Sbinkertn@umich.edu br r31, 8f // continue 10738013Sbinkertn@umich.edu5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit 10748013Sbinkertn@umich.edu br r31, 8f 10758013Sbinkertn@umich.edu 10768013Sbinkertn@umich.edu6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled 10778013Sbinkertn@umich.edu blbc r14, 7f // branch if enabled 10788013Sbinkertn@umich.edu or r13, r31, r14 // don't set PCE if disabled 10798013Sbinkertn@umich.edu br r31, 8f // continue 10808013Sbinkertn@umich.edu7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit 10818013Sbinkertn@umich.edu 10828013Sbinkertn@umich.edu // Setup SCB if dpc is not set 10838013Sbinkertn@umich.edu8: mtpr r14, pt_mces // Store updated MCES 10848013Sbinkertn@umich.edu srl r13, mces_v_sce, r1 // Get SCE 10858013Sbinkertn@umich.edu srl r13, mces_v_pce, r14 // Get PCE 10868013Sbinkertn@umich.edu or r1, r14, r1 // SCE OR PCE, since they share 10878013Sbinkertn@umich.edu // the CRD logout frame 10888013Sbinkertn@umich.edu // Get base of the logout area. 10898013Sbinkertn@umich.edu GET_IMPURE(r14) // addr of per-cpu impure area 10908013Sbinkertn@umich.edu GET_ADDR(r14,(pal_logout_area+mchk_crd_base),r14) 10918013Sbinkertn@umich.edu 10928013Sbinkertn@umich.edu blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame 10938013Sbinkertn@umich.edu 10948013Sbinkertn@umich.edu // Set the 2nd error flag in the logout area: 10958013Sbinkertn@umich.edu 10968013Sbinkertn@umich.edu lda r1, 3(r31) // Set retry and 2nd error flags 10978013Sbinkertn@umich.edu sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword 10988013Sbinkertn@umich.edu stl_p r1, mchk_crd_flag+4(r14) // store flag longword 10998013Sbinkertn@umich.edu br sys_crd_ack 11008013Sbinkertn@umich.edu 11018013Sbinkertn@umich.edusys_crd_write_logout_frame: 11028013Sbinkertn@umich.edu // should only be here if neither the pce or sce bits are set 11038013Sbinkertn@umich.edu 11048013Sbinkertn@umich.edu // 11058013Sbinkertn@umich.edu // Write the mchk code to the logout area 11068013Sbinkertn@umich.edu // 11078013Sbinkertn@umich.edu stq_p r9, mchk_crd_mchk_code(r14) 11088013Sbinkertn@umich.edu 11098013Sbinkertn@umich.edu 11108013Sbinkertn@umich.edu // 11118013Sbinkertn@umich.edu // Write the first 2 quadwords of the logout area: 11128013Sbinkertn@umich.edu // 11138013Sbinkertn@umich.edu lda r1, 1(r31) // Set retry flag 11148013Sbinkertn@umich.edu sll r1, 63, r9 // Move retry flag to bit 63 11158013Sbinkertn@umich.edu lda r1, mchk_crd_size(r9) // Combine retry flag and frame size 11168013Sbinkertn@umich.edu stq_p r1, mchk_crd_flag(r14) // store flag/frame size 11178013Sbinkertn@umich.edu 11188013Sbinkertn@umich.edu // 11198013Sbinkertn@umich.edu // Write error IPRs already fetched to the logout area 11208013Sbinkertn@umich.edu // 11218013Sbinkertn@umich.edu stq_p r0, mchk_crd_ei_addr(r14) 11228013Sbinkertn@umich.edu stq_p r10, mchk_crd_fill_syn(r14) 11238013Sbinkertn@umich.edu stq_p r8, mchk_crd_ei_stat(r14) 11248013Sbinkertn@umich.edu stq_p r25, mchk_crd_isr(r14) 11258013Sbinkertn@umich.edu // 11268013Sbinkertn@umich.edu // Log system specific info here 11278013Sbinkertn@umich.edu // 11288013Sbinkertn@umich.educrd_storeTLEP_: 11298013Sbinkertn@umich.edu lda r1, 0xffc4(r31) // Get GBUS$MISCR address 11308013Sbinkertn@umich.edu sll r1, 24, r1 11318013Sbinkertn@umich.edu ldq_p r1, 0(r1) // Read GBUS$MISCR 11328013Sbinkertn@umich.edu sll r1, 16, r1 // shift up to proper field 11338013Sbinkertn@umich.edu mfpr r10, pt_whami // get our node id 11348013Sbinkertn@umich.edu extbl r10, 1, r10 // shift to bit 0 11358013Sbinkertn@umich.edu or r1, r10, r1 // merge MISCR and WHAMI 11368013Sbinkertn@umich.edu stl_p r1, mchk_crd_whami(r14) // write to crd logout area 11378013Sbinkertn@umich.edu srl r10, 1, r10 // shift off cpu number 11388013Sbinkertn@umich.edu 11398013Sbinkertn@umich.edu Get_TLSB_Node_Address(r10,r0) // compute our nodespace address 11408013Sbinkertn@umich.edu 11418013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb(tldev) 11428013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlber) 11438013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlesr0) 11448013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlesr1) 11458013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlesr2) 11468013Sbinkertn@umich.edu OSFcrd_TLEPstore_tlsb_clr(tlesr3) 11478013Sbinkertn@umich.edu 11488013Sbinkertn@umich.edusys_crd_ack: 11498013Sbinkertn@umich.edu mfpr r0, pt0 // restore r0 11508013Sbinkertn@umich.edu mfpr r1, pt1 // restore r1 11518013Sbinkertn@umich.edu 11528013Sbinkertn@umich.edu srl r12, ei_stat_v_ei_es, r12 11538013Sbinkertn@umich.edu blbc r12, 5f 11548013Sbinkertn@umich.edu srl r13, mces_v_dsc, r10 // logging enabled? 11558013Sbinkertn@umich.edu br r31, 6f 11568013Sbinkertn@umich.edu5: srl r13, mces_v_dpc, r10 // logging enabled? 11578013Sbinkertn@umich.edu6: blbc r10, sys_crd_post_interrupt // logging enabled -- report it 11588013Sbinkertn@umich.edu 11598013Sbinkertn@umich.edu // logging not enabled 11608013Sbinkertn@umich.edu // Get base of the logout area. 11618013Sbinkertn@umich.edu GET_IMPURE(r13) // addr of per-cpu impure area 11628013Sbinkertn@umich.edu GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13) 11638013Sbinkertn@umich.edu ldl_p r10, mchk_crd_rsvd(r13) // bump counter 11648013Sbinkertn@umich.edu addl r10, 1, r10 11658013Sbinkertn@umich.edu stl_p r10, mchk_crd_rsvd(r13) 11668013Sbinkertn@umich.edu mb 11678013Sbinkertn@umich.edu br r31, sys_crd_dismiss_interrupt // just return 11688013Sbinkertn@umich.edu 11698013Sbinkertn@umich.edu // 11708013Sbinkertn@umich.edu // The stack is pushed. Load up a0,a1,a2 and vector via entInt 11718013Sbinkertn@umich.edu // 11728013Sbinkertn@umich.edu // 11738013Sbinkertn@umich.edu 11748013Sbinkertn@umich.edu ALIGN_BRANCH 11758013Sbinkertn@umich.edusys_crd_post_interrupt: 11768013Sbinkertn@umich.edu lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0 11778013Sbinkertn@umich.edu lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector 11788013Sbinkertn@umich.edu 11798013Sbinkertn@umich.edu blbc r12, 1f 11808013Sbinkertn@umich.edu lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector 11818013Sbinkertn@umich.edu 11828013Sbinkertn@umich.edu1: subq r31, 1, r18 // get a -1 11838013Sbinkertn@umich.edu mfpr r25, pt_entInt 11848013Sbinkertn@umich.edu 11858013Sbinkertn@umich.edu srl r18, 42, r18 // shift off low bits of kseg addr 11868013Sbinkertn@umich.edu mtpr r25, exc_addr // load interrupt vector 11878013Sbinkertn@umich.edu 11888013Sbinkertn@umich.edu sll r18, 42, r18 // shift back into position 11898013Sbinkertn@umich.edu or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address 11908013Sbinkertn@umich.edu 11918013Sbinkertn@umich.edu hw_rei_spe // done 11928013Sbinkertn@umich.edu 11938013Sbinkertn@umich.edu 11948013Sbinkertn@umich.edu // 11958013Sbinkertn@umich.edu // The stack is pushed. Need to back out of it all. 11968013Sbinkertn@umich.edu // 11978013Sbinkertn@umich.edu 11988013Sbinkertn@umich.edusys_crd_dismiss_interrupt: 11998013Sbinkertn@umich.edu br r31, Call_Pal_Rti 12008013Sbinkertn@umich.edu 12018013Sbinkertn@umich.edu 12028013Sbinkertn@umich.edu// sys_crd_scrub_mem 12038013Sbinkertn@umich.edu// 12048013Sbinkertn@umich.edu// r0 = addr of cache block 12058013Sbinkertn@umich.edu// 12068013Sbinkertn@umich.edu ALIGN_BLOCK // align for branch target 12078013Sbinkertn@umich.edusys_crd_scrub_mem: 12088013Sbinkertn@umich.edu // now find error in memory, and attempt to scrub that cache block 12098013Sbinkertn@umich.edu // This routine just scrubs the failing octaword 12108013Sbinkertn@umich.edu // Only need to "touch" one quadword per octaword to accomplish the scrub 12118013Sbinkertn@umich.edu srl r0, 39, r8 // get high bit of bad pa 12128013Sbinkertn@umich.edu blbs r8, 1f // don't attempt fixup on IO space addrs 12138013Sbinkertn@umich.edu nop // needed to align the ldq_pl to octaword boundary 12148013Sbinkertn@umich.edu nop // " 12158013Sbinkertn@umich.edu 12168013Sbinkertn@umich.edu ldq_p r8, 0(r0) // attempt to read the bad memory 12178013Sbinkertn@umich.edu // location 12188013Sbinkertn@umich.edu // (Note bits 63:40,3:0 of ei_addr 12198013Sbinkertn@umich.edu // are set to 1, but as long as 12208013Sbinkertn@umich.edu // we are doing a phys ref, should 12218013Sbinkertn@umich.edu // be ok) 12228013Sbinkertn@umich.edu nop // Needed to keep the Ibox from swapping the ldq_p into E1 12238013Sbinkertn@umich.edu 12248013Sbinkertn@umich.edu stq_p r8, 0(r0) // Store it back if it is still there. 12258013Sbinkertn@umich.edu // If store fails, location already 12268013Sbinkertn@umich.edu // scrubbed by someone else 12278013Sbinkertn@umich.edu 12288013Sbinkertn@umich.edu nop // needed to align the ldq_p to octaword boundary 12298013Sbinkertn@umich.edu 12308013Sbinkertn@umich.edu lda r8, 0x20(r31) // flip bit 5 to touch next hexaword 12318013Sbinkertn@umich.edu xor r8, r0, r0 12328013Sbinkertn@umich.edu nop // needed to align the ldq_p to octaword boundary 12338013Sbinkertn@umich.edu nop // " 12348013Sbinkertn@umich.edu 12358013Sbinkertn@umich.edu ldq_p r8, 0(r0) // attempt to read the bad memory 12368013Sbinkertn@umich.edu // location 12378013Sbinkertn@umich.edu // (Note bits 63:40,3:0 of ei_addr 12388013Sbinkertn@umich.edu // are set to 1, but as long as 12398013Sbinkertn@umich.edu // we are doing a phys ref, should 12408013Sbinkertn@umich.edu // be ok) 12418013Sbinkertn@umich.edu nop // Needed to keep the Ibox from swapping the ldq_p into E1 12428013Sbinkertn@umich.edu 12438013Sbinkertn@umich.edu stq_p r8, 0(r0) // Store it back if it is still there. 12448013Sbinkertn@umich.edu // If store fails, location already 12458013Sbinkertn@umich.edu // scrubbed by someone else 12468013Sbinkertn@umich.edu 12478013Sbinkertn@umich.edu lda r8, 0x20(r31) // restore r0 to original address 12488013Sbinkertn@umich.edu xor r8, r0, r0 12498013Sbinkertn@umich.edu 12508013Sbinkertn@umich.edu //at this point, ei_stat could be locked due to a new corr error on the ld, 12518013Sbinkertn@umich.edu //so read ei_stat to unlock AFTER this routine. 12528013Sbinkertn@umich.edu 12538013Sbinkertn@umich.edu// XXX bugnion pvc$jsr crd_scrub_mem, bsr=1, dest=1 12548013Sbinkertn@umich.edu1: ret r31, (r13) // and back we go 12558013Sbinkertn@umich.edu 12568013Sbinkertn@umich.edu 12578013Sbinkertn@umich.edu// 12588013Sbinkertn@umich.edu// sys_int_mchk - MCHK Interrupt code 12598013Sbinkertn@umich.edu// 12608013Sbinkertn@umich.edu// Machine check interrupt from the system. Setup and join the 12618013Sbinkertn@umich.edu// regular machine check flow. 12628013Sbinkertn@umich.edu// On exit: 12638013Sbinkertn@umich.edu// pt0 - saved r0 12648013Sbinkertn@umich.edu// pt1 - saved r1 12658013Sbinkertn@umich.edu// pt4 - saved r4 12668013Sbinkertn@umich.edu// pt5 - saved r5 12678013Sbinkertn@umich.edu// pt6 - saved r6 12688013Sbinkertn@umich.edu// pt10 - saved exc_addr 12698013Sbinkertn@umich.edu// pt_misc<47:32> - mchk code 12708013Sbinkertn@umich.edu// pt_misc<31:16> - scb vector 12718013Sbinkertn@umich.edu// r14 - base of Cbox IPRs in IO space 12728013Sbinkertn@umich.edu// MCES<mchk> is set 12738013Sbinkertn@umich.edu// 12748013Sbinkertn@umich.edu ALIGN_BLOCK 12758013Sbinkertn@umich.edusys_int_mchk: 12768013Sbinkertn@umich.edu lda r14, mchk_c_sys_hrd_error(r31) 12778013Sbinkertn@umich.edu mfpr r12, exc_addr 12788013Sbinkertn@umich.edu 12798013Sbinkertn@umich.edu addq r14, 1, r14 // Flag as interrupt 12808013Sbinkertn@umich.edu nop 12818013Sbinkertn@umich.edu 12828013Sbinkertn@umich.edu sll r14, 32, r14 // Move mchk code to position 12838013Sbinkertn@umich.edu mtpr r12, pt10 // Stash exc_addr 12848013Sbinkertn@umich.edu 12858013Sbinkertn@umich.edu mfpr r12, pt_misc // Get MCES and scratch 12868013Sbinkertn@umich.edu mtpr r0, pt0 // Stash for scratch 12878013Sbinkertn@umich.edu 12888013Sbinkertn@umich.edu zap r12, 0x3c, r12 // Clear scratch 12898013Sbinkertn@umich.edu blbs r12, sys_double_machine_check // MCHK halt if double machine check 12908013Sbinkertn@umich.edu 12918013Sbinkertn@umich.edu or r12, r14, r12 // Combine mchk code 12928013Sbinkertn@umich.edu lda r14, scb_v_sysmchk(r31) // Get SCB vector 12938013Sbinkertn@umich.edu 12948013Sbinkertn@umich.edu sll r14, 16, r14 // Move SCBv to position 12958013Sbinkertn@umich.edu or r12, r14, r14 // Combine SCBv 12968013Sbinkertn@umich.edu 12978013Sbinkertn@umich.edu bis r14, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit 12988013Sbinkertn@umich.edu mtpr r14, pt_misc // Save mchk code!scbv!whami!mces 12998013Sbinkertn@umich.edu 13008013Sbinkertn@umich.edu ldah r14, 0xfff0(r31) 13018013Sbinkertn@umich.edu mtpr r1, pt1 // Stash for scratch 13028013Sbinkertn@umich.edu 13038013Sbinkertn@umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 13048013Sbinkertn@umich.edu mtpr r4, pt4 13058013Sbinkertn@umich.edu 13068013Sbinkertn@umich.edu mtpr r5, pt5 13078013Sbinkertn@umich.edu 13088013Sbinkertn@umich.edu mtpr r6, pt6 13098013Sbinkertn@umich.edu br r31, sys_mchk_collect_iprs // Join common machine check flow 13108013Sbinkertn@umich.edu 13118013Sbinkertn@umich.edu 13128013Sbinkertn@umich.edu// 13138013Sbinkertn@umich.edu// sys_int_perf_cnt - Performance counter interrupt code 13148013Sbinkertn@umich.edu// 13158013Sbinkertn@umich.edu// A performance counter interrupt has been detected. The stack 13168013Sbinkertn@umich.edu// has been pushed. IPL and PS are updated as well. 13178013Sbinkertn@umich.edu// 13188013Sbinkertn@umich.edu// on exit to interrupt entry point ENTINT:: 13198013Sbinkertn@umich.edu// a0 = osfint$c_perf 13208013Sbinkertn@umich.edu// a1 = scb$v_perfmon (650) 13218013Sbinkertn@umich.edu// a2 = 0 if performance counter 0 fired 13228013Sbinkertn@umich.edu// a2 = 1 if performance counter 1 fired 13238013Sbinkertn@umich.edu// a2 = 2 if performance counter 2 fired 13248013Sbinkertn@umich.edu// (if more than one counter overflowed, an interrupt will be 13258013Sbinkertn@umich.edu// generated for each counter that overflows) 13268013Sbinkertn@umich.edu// 13278013Sbinkertn@umich.edu// 13288013Sbinkertn@umich.edu// 13298013Sbinkertn@umich.edu ALIGN_BLOCK 13308013Sbinkertn@umich.edusys_int_perf_cnt: // Performance counter interrupt 13318013Sbinkertn@umich.edu lda r17, scb_v_perfmon(r31) // a1 to interrupt vector 13328013Sbinkertn@umich.edu mfpr r25, pt_entint 13338013Sbinkertn@umich.edu 13348013Sbinkertn@umich.edu lda r16, osfint_c_perf(r31) // a0 to perf counter code 13358013Sbinkertn@umich.edu mtpr r25, exc_addr 13368013Sbinkertn@umich.edu 13378013Sbinkertn@umich.edu //isolate which perf ctr fired, load code in a2, and ack 13388013Sbinkertn@umich.edu mfpr r25, isr 13398013Sbinkertn@umich.edu or r31, r31, r18 // assume interrupt was pc0 13408013Sbinkertn@umich.edu 13418013Sbinkertn@umich.edu srl r25, isr_v_pc1, r25 // isolate 13428013Sbinkertn@umich.edu cmovlbs r25, 1, r18 // if pc1 set, load 1 into r14 13438013Sbinkertn@umich.edu 13448013Sbinkertn@umich.edu srl r25, 1, r25 // get pc2 13458013Sbinkertn@umich.edu cmovlbs r25, 2, r18 // if pc2 set, load 2 into r14 13468013Sbinkertn@umich.edu 13478013Sbinkertn@umich.edu lda r25, 1(r31) // get a one 13488013Sbinkertn@umich.edu sll r25, r18, r25 13498013Sbinkertn@umich.edu 13508013Sbinkertn@umich.edu sll r25, hwint_clr_v_pc0c, r25 // ack only the perf counter that generated the interrupt 13518013Sbinkertn@umich.edu mtpr r25, hwint_clr 13528013Sbinkertn@umich.edu 13538013Sbinkertn@umich.edu hw_rei_spe 13548013Sbinkertn@umich.edu 13558013Sbinkertn@umich.edu 13568013Sbinkertn@umich.edu 13578013Sbinkertn@umich.edu// 13588013Sbinkertn@umich.edu// sys_reset - System specific RESET code 13598013Sbinkertn@umich.edu// On entry: 13608013Sbinkertn@umich.edu// r1 = pal_base +8 13618013Sbinkertn@umich.edu// 13628013Sbinkertn@umich.edu// Entry state on trap: 13638013Sbinkertn@umich.edu// r0 = whami 13648013Sbinkertn@umich.edu// r2 = base of scratch area 13658013Sbinkertn@umich.edu// r3 = halt code 13668013Sbinkertn@umich.edu// and the following 3 if init_cbox is enabled: 13678013Sbinkertn@umich.edu// r5 = sc_ctl 13688013Sbinkertn@umich.edu// r6 = bc_ctl 13698013Sbinkertn@umich.edu// r7 = bc_cnfg 13708013Sbinkertn@umich.edu// 13718013Sbinkertn@umich.edu// Entry state on switch: 13728013Sbinkertn@umich.edu// r17 - new PC 13738013Sbinkertn@umich.edu// r18 - new PCBB 13748013Sbinkertn@umich.edu// r19 - new VPTB 13758013Sbinkertn@umich.edu// 13768013Sbinkertn@umich.edu 13778013Sbinkertn@umich.edu ALIGN_BLOCK 13788013Sbinkertn@umich.edu .globl sys_reset 13798013Sbinkertn@umich.edusys_reset: 13808013Sbinkertn@umich.edu// mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load 13818013Sbinkertn@umich.edu mtpr r31, itb_ia // clear the ITB 13828013Sbinkertn@umich.edu mtpr r31, dtb_ia // clear the DTB 13838013Sbinkertn@umich.edu 13848013Sbinkertn@umich.edu lda r1, -8(r1) // point to start of code 13858013Sbinkertn@umich.edu mtpr r1, pal_base // initialize PAL_BASE 13868013Sbinkertn@umich.edu 13878013Sbinkertn@umich.edu // Interrupts 13888013Sbinkertn@umich.edu mtpr r31, astrr // stop ASTs 13898013Sbinkertn@umich.edu mtpr r31, aster // stop ASTs 13908013Sbinkertn@umich.edu mtpr r31, sirr // clear software interrupts 13918013Sbinkertn@umich.edu 13928013Sbinkertn@umich.edu mtpr r0, pt1 // r0 is whami (unless we entered via swp) 13938013Sbinkertn@umich.edu 13948013Sbinkertn@umich.edu ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero) 13958013Sbinkertn@umich.edu 13968013Sbinkertn@umich.edu bis r31, 1, r0 13978013Sbinkertn@umich.edu sll r0, icsr_v_crde, r0 // A 1 in iscr<corr_read_enable> 13988013Sbinkertn@umich.edu or r0, r1, r1 // Set the bit 13998013Sbinkertn@umich.edu 14008013Sbinkertn@umich.edu mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable, 14018013Sbinkertn@umich.edu // super page enabled, correct read per assembly option 14028013Sbinkertn@umich.edu 14038013Sbinkertn@umich.edu // Mbox/Dcache init 14048013Sbinkertn@umich.edu lda r1,BIT(mcsr_v_sp1)(zero) 14058013Sbinkertn@umich.edu 14068013Sbinkertn@umich.edu mtpr r1, mcsr // MCSR - Super page enabled 14078013Sbinkertn@umich.edu lda r1, BIT(dc_mode_v_dc_ena)(r31) 14088013Sbinkertn@umich.edu ALIGN_BRANCH 14098013Sbinkertn@umich.edu// mtpr r1, dc_mode // turn Dcache on 14108013Sbinkertn@umich.edu nop 14118013Sbinkertn@umich.edu 14128013Sbinkertn@umich.edu mfpr r31, pt0 // No Mbox instr in 1,2,3,4 14138013Sbinkertn@umich.edu mfpr r31, pt0 14148013Sbinkertn@umich.edu mfpr r31, pt0 14158013Sbinkertn@umich.edu mfpr r31, pt0 14168013Sbinkertn@umich.edu mtpr r31, dc_flush // flush Dcache 14178013Sbinkertn@umich.edu 14188013Sbinkertn@umich.edu // build PS (IPL=7,CM=K,VMM=0,SW=0) 14198013Sbinkertn@umich.edu lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7 14208013Sbinkertn@umich.edu lda r1, 0x1F(r31) 14218013Sbinkertn@umich.edu mtpr r1, ipl // set internal <ipl>=1F 14228013Sbinkertn@umich.edu mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy 14238013Sbinkertn@umich.edu mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy 14248013Sbinkertn@umich.edu 14258013Sbinkertn@umich.edu // Create the PALtemp pt_intmask 14268013Sbinkertn@umich.edu // MAP: 14278013Sbinkertn@umich.edu // OSF IPL EV5 internal IPL(hex) note 14288013Sbinkertn@umich.edu // 0 0 14298013Sbinkertn@umich.edu // 1 1 14308013Sbinkertn@umich.edu // 2 2 14318013Sbinkertn@umich.edu // 3 14 device 14328013Sbinkertn@umich.edu // 4 15 device 14338013Sbinkertn@umich.edu // 5 16 device 14348013Sbinkertn@umich.edu // 6 1E device,performance counter, powerfail 14358013Sbinkertn@umich.edu // 7 1F 14368013Sbinkertn@umich.edu // 14378013Sbinkertn@umich.edu 14388013Sbinkertn@umich.edu ldah r1, 0x1f1E(r31) // Create upper lw of int_mask 14398013Sbinkertn@umich.edu lda r1, 0x1615(r1) 14408013Sbinkertn@umich.edu 14418013Sbinkertn@umich.edu sll r1, 32, r1 14428013Sbinkertn@umich.edu ldah r1, 0x1402(r1) // Create lower lw of int_mask 14438013Sbinkertn@umich.edu 14448013Sbinkertn@umich.edu lda r1, 0x0100(r1) 14458013Sbinkertn@umich.edu mtpr r1, pt_intmask // Stash in PALtemp 14468013Sbinkertn@umich.edu 14478013Sbinkertn@umich.edu // Unlock a bunch of chip internal IPRs 14488013Sbinkertn@umich.edu mtpr r31, exc_sum // clear out exeception summary and exc_mask 14498013Sbinkertn@umich.edu mfpr r31, va // unlock va, mmstat 14508013Sbinkertn@umich.edu lda r8,(BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(zero) 14518013Sbinkertn@umich.edu 14528013Sbinkertn@umich.edu mtpr r8, icperr_stat // Clear Icache parity error & timeout status 14538013Sbinkertn@umich.edu lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31) 14548013Sbinkertn@umich.edu 14558013Sbinkertn@umich.edu mtpr r8, dcperr_stat // Clear Dcache parity error status 14568013Sbinkertn@umich.edu 14578013Sbinkertn@umich.edu rc r0 // clear intr_flag 14588013Sbinkertn@umich.edu mtpr r31, pt_trap 14598013Sbinkertn@umich.edu 14608013Sbinkertn@umich.edu mfpr r0, pt_misc 14618013Sbinkertn@umich.edu srl r0, pt_misc_v_switch, r1 14628013Sbinkertn@umich.edu blbs r1, sys_reset_switch // see if we got here from swppal 14638013Sbinkertn@umich.edu 14648013Sbinkertn@umich.edu // Rest of the "real" reset flow 14658013Sbinkertn@umich.edu // ASN 14668013Sbinkertn@umich.edu mtpr r31, dtb_asn 14678013Sbinkertn@umich.edu mtpr r31, itb_asn 14688013Sbinkertn@umich.edu 14698013Sbinkertn@umich.edu lda r1, 0x67(r31) 14708013Sbinkertn@umich.edu sll r1, hwint_clr_v_pc0c, r1 14718013Sbinkertn@umich.edu mtpr r1, hwint_clr // Clear hardware interrupt requests 14728013Sbinkertn@umich.edu 14738013Sbinkertn@umich.edu lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error 14748013Sbinkertn@umich.edu mfpr r0, pt1 // get whami 14758013Sbinkertn@umich.edu insbl r0, 1, r0 // isolate whami in correct pt_misc position 14768013Sbinkertn@umich.edu or r0, r1, r1 // combine whami and mces 14778013Sbinkertn@umich.edu mtpr r1, pt_misc // store whami and mces, swap bit clear 14788013Sbinkertn@umich.edu 14798013Sbinkertn@umich.edu zapnot r3, 1, r0 // isolate halt code 14808013Sbinkertn@umich.edu mtpr r0, pt0 // save entry type 14818013Sbinkertn@umich.edu 14828013Sbinkertn@umich.edu // Cycle counter 14838013Sbinkertn@umich.edu or r31, 1, r9 // get a one 14848013Sbinkertn@umich.edu sll r9, 32, r9 // shift to <32> 14858013Sbinkertn@umich.edu mtpr r31, cc // clear Cycle Counter 14868013Sbinkertn@umich.edu mtpr r9, cc_ctl // clear and enable the Cycle Counter 14878013Sbinkertn@umich.edu mtpr r31, pt_scc // clear System Cycle Counter 14888013Sbinkertn@umich.edu 14898013Sbinkertn@umich.edu 14908013Sbinkertn@umich.edu // Misc PALtemps 14918013Sbinkertn@umich.edu mtpr r31, maf_mode // no mbox instructions for 3 cycles 14928013Sbinkertn@umich.edu or r31, 1, r1 // get bogus scbb value 14938013Sbinkertn@umich.edu mtpr r1, pt_scbb // load scbb 14948013Sbinkertn@umich.edu mtpr r31, pt_prbr // clear out prbr 14958013Sbinkertn@umich.edu#if defined(TSUNAMI) || defined(BIG_TSUNAMI) 14968013Sbinkertn@umich.edu // yes, this is ugly, but you figure out a better 14978013Sbinkertn@umich.edu // way to get the address of the kludge_initial_pcbb 14988013Sbinkertn@umich.edu // in r1 with an uncooperative assembler --ali 14998013Sbinkertn@umich.edu br r1, kludge_getpcb_addr 15008013Sbinkertn@umich.edu br r31, kludge_initial_pcbb 15018013Sbinkertn@umich.edukludge_getpcb_addr: 15028013Sbinkertn@umich.edu ldq_p r19, 0(r1) 15038013Sbinkertn@umich.edu sll r19, 44, r19 15048013Sbinkertn@umich.edu srl r19, 44, r19 15058013Sbinkertn@umich.edu mulq r19,4,r19 15068013Sbinkertn@umich.edu addq r19, r1, r1 15078013Sbinkertn@umich.edu addq r1,4,r1 15088013Sbinkertn@umich.edu#elif defined(TLASER) 15098013Sbinkertn@umich.edu // or zero,kludge_initial_pcbb,r1 15108013Sbinkertn@umich.edu GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1) 15118013Sbinkertn@umich.edu#endif 15128013Sbinkertn@umich.edu mtpr r1, pt_pcbb // load pcbb 15138013Sbinkertn@umich.edu lda r1, 2(r31) // get a two 15148013Sbinkertn@umich.edu sll r1, 32, r1 // gen up upper bits 15158013Sbinkertn@umich.edu mtpr r1, mvptbr 15168013Sbinkertn@umich.edu mtpr r1, ivptbr 15178013Sbinkertn@umich.edu mtpr r31, pt_ptbr 15188013Sbinkertn@umich.edu // Performance counters 15198013Sbinkertn@umich.edu mtpr r31, pmctr 15208013Sbinkertn@umich.edu 15218013Sbinkertn@umich.edu // Clear pmctr_ctl in impure area 15228013Sbinkertn@umich.edu 15238013Sbinkertn@umich.edu 15248013Sbinkertn@umich.edu ldah r14, 0xfff0(r31) 15258013Sbinkertn@umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 15268013Sbinkertn@umich.edu GET_IMPURE(r13) 15278013Sbinkertn@umich.edu stq_p r31, 0(r13) // Clear lock_flag 15288013Sbinkertn@umich.edu 15298013Sbinkertn@umich.edu mfpr r0, pt0 // get entry type 15308013Sbinkertn@umich.edu br r31, sys_enter_console // enter the cosole 15318013Sbinkertn@umich.edu 15328013Sbinkertn@umich.edu 15338013Sbinkertn@umich.edu // swppal entry 15348013Sbinkertn@umich.edu // r0 - pt_misc 15358013Sbinkertn@umich.edu // r17 - new PC 15368013Sbinkertn@umich.edu // r18 - new PCBB 15378013Sbinkertn@umich.edu // r19 - new VPTB 15388013Sbinkertn@umich.edusys_reset_switch: 15398013Sbinkertn@umich.edu or r31, 1, r9 15408013Sbinkertn@umich.edu sll r9, pt_misc_v_switch, r9 15418013Sbinkertn@umich.edu bic r0, r9, r0 // clear switch bit 15428013Sbinkertn@umich.edu mtpr r0, pt_misc 15438013Sbinkertn@umich.edu 15448013Sbinkertn@umich.edu rpcc r1 // get cyccounter 15458013Sbinkertn@umich.edu 15468013Sbinkertn@umich.edu ldq_p r22, osfpcb_q_fen(r18) // get new fen/pme 15478013Sbinkertn@umich.edu ldl_p r23, osfpcb_l_cc(r18) // get cycle counter 15488013Sbinkertn@umich.edu ldl_p r24, osfpcb_l_asn(r18) // get new asn 15498013Sbinkertn@umich.edu 15508013Sbinkertn@umich.edu 15518013Sbinkertn@umich.edu ldq_p r25, osfpcb_q_Mmptr(r18)// get new mmptr 15528013Sbinkertn@umich.edu sll r25, page_offset_size_bits, r25 // convert pfn to pa 15538013Sbinkertn@umich.edu mtpr r25, pt_ptbr // load the new mmptr 15548013Sbinkertn@umich.edu mtpr r18, pt_pcbb // set new pcbb 15558013Sbinkertn@umich.edu 15568013Sbinkertn@umich.edu bic r17, 3, r17 // clean use pc 15578013Sbinkertn@umich.edu mtpr r17, exc_addr // set new pc 15588013Sbinkertn@umich.edu mtpr r19, mvptbr 15598013Sbinkertn@umich.edu mtpr r19, ivptbr 15608013Sbinkertn@umich.edu 15618013Sbinkertn@umich.edu ldq_p r30, osfpcb_q_Usp(r18) // get new usp 15628013Sbinkertn@umich.edu mtpr r30, pt_usp // save usp 15638013Sbinkertn@umich.edu 15648013Sbinkertn@umich.edu sll r24, dtb_asn_v_asn, r8 15658013Sbinkertn@umich.edu mtpr r8, dtb_asn 15668013Sbinkertn@umich.edu sll r24, itb_asn_v_asn, r24 15678013Sbinkertn@umich.edu mtpr r24, itb_asn 15688013Sbinkertn@umich.edu 15698013Sbinkertn@umich.edu mfpr r25, icsr // get current icsr 15708013Sbinkertn@umich.edu lda r24, 1(r31) 15718013Sbinkertn@umich.edu sll r24, icsr_v_fpe, r24 // 1 in icsr<fpe> position 15728013Sbinkertn@umich.edu bic r25, r24, r25 // clean out old fpe 15738013Sbinkertn@umich.edu and r22, 1, r22 // isolate new fen bit 15748013Sbinkertn@umich.edu sll r22, icsr_v_fpe, r22 15758013Sbinkertn@umich.edu or r22, r25, r25 // or in new fpe 15768013Sbinkertn@umich.edu mtpr r25, icsr // update ibox ipr 15778013Sbinkertn@umich.edu 15788013Sbinkertn@umich.edu subl r23, r1, r1 // gen new cc offset 15798013Sbinkertn@umich.edu insll r1, 4, r1 // << 32 15808013Sbinkertn@umich.edu mtpr r1, cc // set new offset 15818013Sbinkertn@umich.edu 15828013Sbinkertn@umich.edu or r31, r31, r0 // set success 15838013Sbinkertn@umich.edu ldq_p r30, osfpcb_q_Ksp(r18) // get new ksp 15848013Sbinkertn@umich.edu mfpr r31, pt0 // stall 15858013Sbinkertn@umich.edu hw_rei_stall 15868013Sbinkertn@umich.edu 15878013Sbinkertn@umich.edu// 15888013Sbinkertn@umich.edu//sys_machine_check - Machine check PAL 15898013Sbinkertn@umich.edu// A machine_check trap has occurred. The Icache has been flushed. 15908013Sbinkertn@umich.edu// 15918013Sbinkertn@umich.edu// 15928013Sbinkertn@umich.edu 15938013Sbinkertn@umich.edu ALIGN_BLOCK 15948013Sbinkertn@umich.eduEXPORT(sys_machine_check) 15958013Sbinkertn@umich.edu // Need to fill up the refill buffer (32 instructions) and 15968013Sbinkertn@umich.edu // then flush the Icache again. 15978013Sbinkertn@umich.edu // Also, due to possible 2nd Cbox register file write for 15988013Sbinkertn@umich.edu // uncorrectable errors, no register file read or write for 7 cycles. 15998013Sbinkertn@umich.edu 16008025Ssaidi@eecs.umich.edu //nop 16018025Ssaidi@eecs.umich.edu .long 0x4000054 // call M5 Panic 16028013Sbinkertn@umich.edu mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites 16038013Sbinkertn@umich.edu // r0 later 16048013Sbinkertn@umich.edu nop 16058013Sbinkertn@umich.edu nop 16068013Sbinkertn@umich.edu 16078013Sbinkertn@umich.edu nop 16088013Sbinkertn@umich.edu nop 16098013Sbinkertn@umich.edu 16108013Sbinkertn@umich.edu nop 16118013Sbinkertn@umich.edu nop 16128013Sbinkertn@umich.edu 16138013Sbinkertn@umich.edu nop 16148013Sbinkertn@umich.edu nop 16158013Sbinkertn@umich.edu // 10 instructions// 5 cycles 16168013Sbinkertn@umich.edu 16178013Sbinkertn@umich.edu nop 16188013Sbinkertn@umich.edu nop 16198013Sbinkertn@umich.edu 16208013Sbinkertn@umich.edu nop 16218013Sbinkertn@umich.edu nop 16228013Sbinkertn@umich.edu 16238013Sbinkertn@umich.edu // Register file can now be written 16248013Sbinkertn@umich.edu lda r0, scb_v_procmchk(r31) // SCB vector 16258013Sbinkertn@umich.edu mfpr r13, pt_mces // Get MCES 16268013Sbinkertn@umich.edu sll r0, 16, r0 // Move SCBv to correct position 16278013Sbinkertn@umich.edu bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit 16288013Sbinkertn@umich.edu 16298013Sbinkertn@umich.edu 16308013Sbinkertn@umich.edu zap r14, 0x3C, r14 // Clear mchk_code word and SCBv word 16318013Sbinkertn@umich.edu mtpr r14, pt_mces 16328013Sbinkertn@umich.edu // 20 instructions 16338013Sbinkertn@umich.edu 16348013Sbinkertn@umich.edu nop 16358013Sbinkertn@umich.edu or r14, r0, r14 // Insert new SCB vector 16368013Sbinkertn@umich.edu lda r0, mchk_c_proc_hrd_error(r31) // MCHK code 16378013Sbinkertn@umich.edu mfpr r12, exc_addr 16388013Sbinkertn@umich.edu 16398013Sbinkertn@umich.edu sll r0, 32, r0 // Move MCHK code to correct position 16408013Sbinkertn@umich.edu mtpr r4, pt4 16418013Sbinkertn@umich.edu or r14, r0, r14 // Insert new MCHK code 16428013Sbinkertn@umich.edu mtpr r14, pt_misc // Store updated MCES, MCHK code, and SCBv 16438013Sbinkertn@umich.edu 16448013Sbinkertn@umich.edu ldah r14, 0xfff0(r31) 16458013Sbinkertn@umich.edu mtpr r1, pt1 // Stash for scratch - 30 instructions 16468013Sbinkertn@umich.edu 16478013Sbinkertn@umich.edu zap r14, 0xE0, r14 // Get Cbox IPR base 16488013Sbinkertn@umich.edu mtpr r12, pt10 // Stash exc_addr 16498013Sbinkertn@umich.edu 16508013Sbinkertn@umich.edu 16518013Sbinkertn@umich.edu 16528013Sbinkertn@umich.edu mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed. 16538013Sbinkertn@umich.edu blbs r13, sys_double_machine_check // MCHK halt if double machine check 16548013Sbinkertn@umich.edu 16558013Sbinkertn@umich.edu mtpr r6, pt6 16568013Sbinkertn@umich.edu mtpr r5, pt5 16578013Sbinkertn@umich.edu 16588013Sbinkertn@umich.edu // Look for the powerfail cases here.... 16598013Sbinkertn@umich.edu mfpr r4, isr 16608013Sbinkertn@umich.edu srl r4, isr_v_pfl, r4 16618013Sbinkertn@umich.edu blbc r4, sys_mchk_collect_iprs // skip if no powerfail interrupt pending 16628013Sbinkertn@umich.edu lda r4, 0xffc4(r31) // get GBUS$MISCR address bits 16638013Sbinkertn@umich.edu sll r4, 24, r4 // shift to proper position 16648013Sbinkertn@umich.edu ldq_p r4, 0(r4) // read GBUS$MISCR 16658013Sbinkertn@umich.edu srl r4, 5, r4 // isolate bit <5> 16668013Sbinkertn@umich.edu blbc r4, sys_mchk_collect_iprs // skip if already cleared 16678013Sbinkertn@umich.edu // No missed CFAIL mchk 16688013Sbinkertn@umich.edu lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits 16698013Sbinkertn@umich.edu sll r5, 24, r5 // shift to proper position 16708013Sbinkertn@umich.edu lda r6, 0x40(r31) // get bit <6> mask 16718013Sbinkertn@umich.edu ldq_p r4, 0(r5) // read GBUS$SERNUM 16728013Sbinkertn@umich.edu or r4, r6, r6 // set bit <6> 16738013Sbinkertn@umich.edu stq_p r6, 0(r5) // clear GBUS$SERNUM<6> 16748013Sbinkertn@umich.edu mb 16758013Sbinkertn@umich.edu mb 16768013Sbinkertn@umich.edu 16778013Sbinkertn@umich.edu 16788013Sbinkertn@umich.edu // 16798013Sbinkertn@umich.edu // Start to collect the IPRs. Common entry point for mchk flows. 16808013Sbinkertn@umich.edu // 16818013Sbinkertn@umich.edu // Current state: 16828013Sbinkertn@umich.edu // pt0 - saved r0 16838013Sbinkertn@umich.edu // pt1 - saved r1 16848013Sbinkertn@umich.edu // pt4 - saved r4 16858013Sbinkertn@umich.edu // pt5 - saved r5 16868013Sbinkertn@umich.edu // pt6 - saved r6 16878013Sbinkertn@umich.edu // pt10 - saved exc_addr 16888013Sbinkertn@umich.edu // pt_misc<47:32> - mchk code 16898013Sbinkertn@umich.edu // pt_misc<31:16> - scb vector 16908013Sbinkertn@umich.edu // r14 - base of Cbox IPRs in IO space 16918013Sbinkertn@umich.edu // r0, r1, r4, r5, r6, r12, r13, r25 - available 16928013Sbinkertn@umich.edu // r8, r9, r10 - available as all loads are physical 16938013Sbinkertn@umich.edu // MCES<mchk> is set 16948013Sbinkertn@umich.edu // 16958013Sbinkertn@umich.edu // 16968013Sbinkertn@umich.edu 16978013Sbinkertn@umich.eduEXPORT(sys_mchk_collect_iprs) 16988025Ssaidi@eecs.umich.edu .long 0x4000054 // call M5 Panic 16998025Ssaidi@eecs.umich.edu //mb // MB before reading Scache IPRs 17008013Sbinkertn@umich.edu mfpr r1, icperr_stat 17018013Sbinkertn@umich.edu 17028013Sbinkertn@umich.edu mfpr r8, dcperr_stat 17038013Sbinkertn@umich.edu mtpr r31, dc_flush // Flush the Dcache 17048013Sbinkertn@umich.edu 17058013Sbinkertn@umich.edu mfpr r31, pt0 // Pad Mbox instructions from dc_flush 17068013Sbinkertn@umich.edu mfpr r31, pt0 17078013Sbinkertn@umich.edu nop 17088013Sbinkertn@umich.edu nop 17098013Sbinkertn@umich.edu 17108013Sbinkertn@umich.edu ldq_p r9, sc_addr(r14) // SC_ADDR IPR 17118013Sbinkertn@umich.edu bis r9, r31, r31 // Touch ld to make sure it completes before 17128013Sbinkertn@umich.edu // read of SC_STAT 17138013Sbinkertn@umich.edu ldq_p r10, sc_stat(r14) // SC_STAT, also unlocks SC_ADDR 17148013Sbinkertn@umich.edu 17158013Sbinkertn@umich.edu ldq_p r12, ei_addr(r14) // EI_ADDR IPR 17168013Sbinkertn@umich.edu ldq_p r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR 17178013Sbinkertn@umich.edu ldq_p r0, fill_syn(r14) // FILL_SYN IPR 17188013Sbinkertn@umich.edu bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT 17198013Sbinkertn@umich.edu bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT 17208013Sbinkertn@umich.edu ldq_p r25, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN 17218013Sbinkertn@umich.edu ldq_p r31, ei_stat(r14) // Read again to insure it is unlocked 17228013Sbinkertn@umich.edu 17238013Sbinkertn@umich.edu 17248013Sbinkertn@umich.edu 17258013Sbinkertn@umich.edu 17268013Sbinkertn@umich.edu // 17278013Sbinkertn@umich.edu // Look for nonretryable cases 17288013Sbinkertn@umich.edu // In this segment: 17298013Sbinkertn@umich.edu // r5<0> = 1 means retryable 17308013Sbinkertn@umich.edu // r4, r6, and r14 are available for scratch 17318013Sbinkertn@umich.edu // 17328013Sbinkertn@umich.edu // 17338013Sbinkertn@umich.edu 17348013Sbinkertn@umich.edu 17358013Sbinkertn@umich.edu bis r31, r31, r5 // Clear local retryable flag 17368013Sbinkertn@umich.edu srl r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits to low bits 17378013Sbinkertn@umich.edu 17388013Sbinkertn@umich.edu lda r4, 1(r31) 17398013Sbinkertn@umich.edu sll r4, icperr_stat_v_tmr, r4 17408013Sbinkertn@umich.edu and r1, r4, r4 // Timeout reset 17418013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17428013Sbinkertn@umich.edu 17438013Sbinkertn@umich.edu and r8, BIT(dcperr_stat_v_lock), r4 // DCache parity error locked 17448013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17458013Sbinkertn@umich.edu 17468013Sbinkertn@umich.edu lda r4, 1(r31) 17478013Sbinkertn@umich.edu sll r4, sc_stat_v_sc_scnd_err, r4 17488013Sbinkertn@umich.edu and r10, r4, r4 // 2nd Scache error occurred 17498013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17508013Sbinkertn@umich.edu 17518013Sbinkertn@umich.edu 17528013Sbinkertn@umich.edu bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control 17538013Sbinkertn@umich.edu // Parity Error, Interface Parity Error, 2nd Error 17548013Sbinkertn@umich.edu 17558013Sbinkertn@umich.edu and r25, r4, r4 17568013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17578013Sbinkertn@umich.edu 17588013Sbinkertn@umich.edu// bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4 17598013Sbinkertn@umich.edu bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4 17608013Sbinkertn@umich.edu and r25, r4, r4 // Isolate the Uncorrectable Error Bit 17618013Sbinkertn@umich.edu// bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6 17628013Sbinkertn@umich.edu bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit 17638013Sbinkertn@umich.edu cmovne r6, 0, r4 // r4 = 0 if IRD or if No Uncorrectable Error 17648013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17658013Sbinkertn@umich.edu 17668013Sbinkertn@umich.edu lda r4, 7(r31) 17678013Sbinkertn@umich.edu and r10, r4, r4 // Isolate the Scache Tag Parity Error bits 17688013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable // All Scache Tag PEs are not retryable 17698013Sbinkertn@umich.edu 17708013Sbinkertn@umich.edu 17718013Sbinkertn@umich.edu lda r4, 0x7f8(r31) 17728013Sbinkertn@umich.edu and r10, r4, r4 // Isolate the Scache Data Parity Error bits 17738013Sbinkertn@umich.edu srl r10, sc_stat_v_cbox_cmd, r6 17748013Sbinkertn@umich.edu and r6, 0x1f, r6 // Isolate Scache Command field 17758013Sbinkertn@umich.edu subq r6, 1, r6 // Scache Iread command = 1 17768013Sbinkertn@umich.edu cmoveq r6, 0, r4 // r4 = 0 if IRD or if No Parity Error 17778013Sbinkertn@umich.edu bne r4, sys_cpu_mchk_not_retryable 17788013Sbinkertn@umich.edu 17798013Sbinkertn@umich.edu // Look for the system unretryable cases here.... 17808013Sbinkertn@umich.edu 17818013Sbinkertn@umich.edu mfpr r4, isr // mchk_interrupt pin asserted 17828013Sbinkertn@umich.edu srl r4, isr_v_mck, r4 17838013Sbinkertn@umich.edu blbs r4, sys_cpu_mchk_not_retryable 17848013Sbinkertn@umich.edu 17858013Sbinkertn@umich.edu 17868013Sbinkertn@umich.edu 17878013Sbinkertn@umich.edu // 17888013Sbinkertn@umich.edu // Look for retryable cases 17898013Sbinkertn@umich.edu // In this segment: 17908013Sbinkertn@umich.edu // r5<0> = 1 means retryable 17918013Sbinkertn@umich.edu // r6 - holds the mchk code 17928013Sbinkertn@umich.edu // r4 and r14 are available for scratch 17938013Sbinkertn@umich.edu // 17948013Sbinkertn@umich.edu // 17958013Sbinkertn@umich.edu 17968013Sbinkertn@umich.edu 17978013Sbinkertn@umich.edu // Within the chip, the retryable cases are Istream errors 17988013Sbinkertn@umich.edu lda r4, 3(r31) 17998013Sbinkertn@umich.edu sll r4, icperr_stat_v_dpe, r4 18008013Sbinkertn@umich.edu and r1, r4, r4 18018013Sbinkertn@umich.edu cmovne r4, 1, r5 // Retryable if just Icache parity error 18028013Sbinkertn@umich.edu 18038013Sbinkertn@umich.edu 18048013Sbinkertn@umich.edu lda r4, 0x7f8(r31) 18058013Sbinkertn@umich.edu and r10, r4, r4 // Isolate the Scache Data Parity Error bits 18068013Sbinkertn@umich.edu srl r10, sc_stat_v_cbox_cmd, r14 18078013Sbinkertn@umich.edu and r14, 0x1f, r14 // Isolate Scache Command field 18088013Sbinkertn@umich.edu subq r14, 1, r14 // Scache Iread command = 1 18098013Sbinkertn@umich.edu cmovne r4, 1, r4 // r4 = 1 if Scache data parity error bit set 18108013Sbinkertn@umich.edu cmovne r14, 0, r4 // r4 = 1 if Scache PE and Iread 18118013Sbinkertn@umich.edu bis r4, r5, r5 // Accumulate 18128013Sbinkertn@umich.edu 18138013Sbinkertn@umich.edu 18148013Sbinkertn@umich.edu bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4 18158013Sbinkertn@umich.edu and r25, r4, r4 // Isolate the Uncorrectable Error Bit 18168013Sbinkertn@umich.edu and r25, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r14 // Isolate the Iread bit 18178013Sbinkertn@umich.edu cmovne r4, 1, r4 // r4 = 1 if uncorr error 18188013Sbinkertn@umich.edu cmoveq r14, 0, r4 // r4 = 1 if uncorr and Iread 18198013Sbinkertn@umich.edu bis r4, r5, r5 // Accumulate 18208013Sbinkertn@umich.edu 18218013Sbinkertn@umich.edu mfpr r6, pt_misc 18228013Sbinkertn@umich.edu extwl r6, 4, r6 // Fetch mchk code 18238013Sbinkertn@umich.edu bic r6, 1, r6 // Clear flag from interrupt flow 18248013Sbinkertn@umich.edu cmovne r5, mchk_c_retryable_ird, r6 // Set mchk code 18258013Sbinkertn@umich.edu 18268013Sbinkertn@umich.edu 18278013Sbinkertn@umich.edu // 18288013Sbinkertn@umich.edu // Write the logout frame 18298013Sbinkertn@umich.edu // 18308013Sbinkertn@umich.edu // Current state: 18318013Sbinkertn@umich.edu // r0 - fill_syn 18328013Sbinkertn@umich.edu // r1 - icperr_stat 18338013Sbinkertn@umich.edu // r4 - available 18348013Sbinkertn@umich.edu // r5<0> - retry flag 18358013Sbinkertn@umich.edu // r6 - mchk code 18368013Sbinkertn@umich.edu // r8 - dcperr_stat 18378013Sbinkertn@umich.edu // r9 - sc_addr 18388013Sbinkertn@umich.edu // r10 - sc_stat 18398013Sbinkertn@umich.edu // r12 - ei_addr 18408013Sbinkertn@umich.edu // r13 - bc_tag_addr 18418013Sbinkertn@umich.edu // r14 - available 18428013Sbinkertn@umich.edu // r25 - ei_stat (shifted) 18438013Sbinkertn@umich.edu // pt0 - saved r0 18448013Sbinkertn@umich.edu // pt1 - saved r1 18458013Sbinkertn@umich.edu // pt4 - saved r4 18468013Sbinkertn@umich.edu // pt5 - saved r5 18478013Sbinkertn@umich.edu // pt6 - saved r6 18488013Sbinkertn@umich.edu // pt10 - saved exc_addr 18498013Sbinkertn@umich.edu // 18508013Sbinkertn@umich.edu // 18518013Sbinkertn@umich.edu 18528013Sbinkertn@umich.edusys_mchk_write_logout_frame: 18538013Sbinkertn@umich.edu // Get base of the logout area. 18548013Sbinkertn@umich.edu GET_IMPURE(r14) // addr of per-cpu impure area 18558013Sbinkertn@umich.edu GET_ADDR(r14,pal_logout_area+mchk_mchk_base,r14) 18568013Sbinkertn@umich.edu 18578013Sbinkertn@umich.edu // Write the first 2 quadwords of the logout area: 18588013Sbinkertn@umich.edu 18598013Sbinkertn@umich.edu sll r5, 63, r5 // Move retry flag to bit 63 18608013Sbinkertn@umich.edu lda r4, mchk_size(r5) // Combine retry flag and frame size 18618013Sbinkertn@umich.edu stq_p r4, mchk_flag(r14) // store flag/frame size 18628013Sbinkertn@umich.edu lda r4, mchk_sys_base(r31) // sys offset 18638013Sbinkertn@umich.edu sll r4, 32, r4 18648013Sbinkertn@umich.edu lda r4, mchk_cpu_base(r4) // cpu offset 18658013Sbinkertn@umich.edu stq_p r4, mchk_offsets(r14) // store sys offset/cpu offset into logout frame 18668013Sbinkertn@umich.edu 18678013Sbinkertn@umich.edu // 18688013Sbinkertn@umich.edu // Write the mchk code to the logout area 18698013Sbinkertn@umich.edu // Write error IPRs already fetched to the logout area 18708013Sbinkertn@umich.edu // Restore some GPRs from PALtemps 18718013Sbinkertn@umich.edu // 18728013Sbinkertn@umich.edu 18738013Sbinkertn@umich.edu mfpr r5, pt5 18748013Sbinkertn@umich.edu stq_p r6, mchk_mchk_code(r14) 18758013Sbinkertn@umich.edu mfpr r4, pt4 18768013Sbinkertn@umich.edu stq_p r1, mchk_ic_perr_stat(r14) 18778013Sbinkertn@umich.edu mfpr r6, pt6 18788013Sbinkertn@umich.edu stq_p r8, mchk_dc_perr_stat(r14) 18798013Sbinkertn@umich.edu mfpr r1, pt1 18808013Sbinkertn@umich.edu stq_p r9, mchk_sc_addr(r14) 18818013Sbinkertn@umich.edu stq_p r10, mchk_sc_stat(r14) 18828013Sbinkertn@umich.edu stq_p r12, mchk_ei_addr(r14) 18838013Sbinkertn@umich.edu stq_p r13, mchk_bc_tag_addr(r14) 18848013Sbinkertn@umich.edu stq_p r0, mchk_fill_syn(r14) 18858013Sbinkertn@umich.edu mfpr r0, pt0 18868013Sbinkertn@umich.edu sll r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits back to expected position 18878013Sbinkertn@umich.edu // retrieve lower 28 bits again from ei_stat and restore before storing to logout frame 18888013Sbinkertn@umich.edu ldah r13, 0xfff0(r31) 18898013Sbinkertn@umich.edu zapnot r13, 0x1f, r13 18908013Sbinkertn@umich.edu ldq_p r13, ei_stat(r13) 18918013Sbinkertn@umich.edu sll r13, 64-ei_stat_v_bc_tperr, r13 18928013Sbinkertn@umich.edu srl r13, 64-ei_stat_v_bc_tperr, r13 18938013Sbinkertn@umich.edu or r25, r13, r25 18948013Sbinkertn@umich.edu stq_p r25, mchk_ei_stat(r14) 18958013Sbinkertn@umich.edu 18968013Sbinkertn@umich.edu 18978013Sbinkertn@umich.edu 18988013Sbinkertn@umich.edu 18998013Sbinkertn@umich.edu // 19008013Sbinkertn@umich.edu // complete the CPU-specific part of the logout frame 19018013Sbinkertn@umich.edu // 19028013Sbinkertn@umich.edu 19038013Sbinkertn@umich.edu ldah r13, 0xfff0(r31) 19048013Sbinkertn@umich.edu zap r13, 0xE0, r13 // Get Cbox IPR base 19058013Sbinkertn@umich.edu ldq_p r13, ld_lock(r13) // Get ld_lock IPR 19068013Sbinkertn@umich.edu stq_p r13, mchk_ld_lock(r14) // and stash it in the frame 19078013Sbinkertn@umich.edu 19088013Sbinkertn@umich.edu // Unlock IPRs 19098013Sbinkertn@umich.edu lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31) 19108013Sbinkertn@umich.edu mtpr r8, dcperr_stat // Clear Dcache parity error status 19118013Sbinkertn@umich.edu 19128013Sbinkertn@umich.edu lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31) 19138013Sbinkertn@umich.edu mtpr r8, icperr_stat // Clear Icache parity error & timeout status 19148013Sbinkertn@umich.edu 19158013Sbinkertn@umich.edu1: ldq_p r8, mchk_ic_perr_stat(r14) // get ICPERR_STAT value 19168013Sbinkertn@umich.edu GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value 19178013Sbinkertn@umich.edu and r0, r8, r0 // compare 19188013Sbinkertn@umich.edu beq r0, 2f // check next case if nothing set 19198013Sbinkertn@umich.edu lda r0, mchk_c_retryable_ird(r31) // set new MCHK code 19208013Sbinkertn@umich.edu br r31, do_670 // setup new vector 19218013Sbinkertn@umich.edu 19228013Sbinkertn@umich.edu2: ldq_p r8, mchk_dc_perr_stat(r14) // get DCPERR_STAT value 19238013Sbinkertn@umich.edu GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value 19248013Sbinkertn@umich.edu and r0, r8, r0 // compare 19258013Sbinkertn@umich.edu beq r0, 3f // check next case if nothing set 19268013Sbinkertn@umich.edu lda r0, mchk_c_dcperr(r31) // set new MCHK code 19278013Sbinkertn@umich.edu br r31, do_670 // setup new vector 19288013Sbinkertn@umich.edu 19298013Sbinkertn@umich.edu3: ldq_p r8, mchk_sc_stat(r14) // get SC_STAT value 19308013Sbinkertn@umich.edu GET_ADDR(r0,0x107ff,r31) // get SC_STAT value 19318013Sbinkertn@umich.edu and r0, r8, r0 // compare 19328013Sbinkertn@umich.edu beq r0, 4f // check next case if nothing set 19338013Sbinkertn@umich.edu lda r0, mchk_c_scperr(r31) // set new MCHK code 19348013Sbinkertn@umich.edu br r31, do_670 // setup new vector 19358013Sbinkertn@umich.edu 19368013Sbinkertn@umich.edu4: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value 19378013Sbinkertn@umich.edu GET_ADDR(r0,0x30000000,r31) // get EI_STAT value 19388013Sbinkertn@umich.edu and r0, r8, r0 // compare 19398013Sbinkertn@umich.edu beq r0, 5f // check next case if nothing set 19408013Sbinkertn@umich.edu lda r0, mchk_c_bcperr(r31) // set new MCHK code 19418013Sbinkertn@umich.edu br r31, do_670 // setup new vector 19428013Sbinkertn@umich.edu 19438013Sbinkertn@umich.edu5: ldl_p r8, mchk_tlber(r14) // get TLBER value 19448013Sbinkertn@umich.edu GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value 19458013Sbinkertn@umich.edu sll r0, 16, r0 // shift into proper position 19468013Sbinkertn@umich.edu GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value 19478013Sbinkertn@umich.edu or r0, r1, r0 // merge mask values 19488013Sbinkertn@umich.edu and r0, r8, r0 // compare 19498013Sbinkertn@umich.edu beq r0, 6f // check next case if nothing set 19508013Sbinkertn@umich.edu GET_ADDR(r0, 0xfff0, r31) // set new MCHK code 19518013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19528013Sbinkertn@umich.edu 19538013Sbinkertn@umich.edu6: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value 19548013Sbinkertn@umich.edu GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value 19558013Sbinkertn@umich.edu and r0, r8, r0 // compare 19568013Sbinkertn@umich.edu beq r0, 7f // check next case if nothing set 19578013Sbinkertn@umich.edu GET_ADDR(r0, 0xfffa, r31) // set new MCHK code 19588013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19598013Sbinkertn@umich.edu 19608013Sbinkertn@umich.edu7: ldl_p r8, mchk_tlepderr(r14) // get TLEPDERR value 19618013Sbinkertn@umich.edu GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value 19628013Sbinkertn@umich.edu and r0, r8, r0 // compare 19638013Sbinkertn@umich.edu beq r0, 8f // check next case if nothing set 19648013Sbinkertn@umich.edu GET_ADDR(r0, 0xfffb, r31) // set new MCHK code 19658013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19668013Sbinkertn@umich.edu 19678013Sbinkertn@umich.edu8: ldl_p r8, mchk_tlepmerr(r14) // get TLEPMERR value 19688013Sbinkertn@umich.edu GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value 19698013Sbinkertn@umich.edu and r0, r8, r0 // compare 19708013Sbinkertn@umich.edu beq r0, 9f // check next case if nothing set 19718013Sbinkertn@umich.edu GET_ADDR(r0, 0xfffc, r31) // set new MCHK code 19728013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19738013Sbinkertn@umich.edu 19748013Sbinkertn@umich.edu9: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value 19758013Sbinkertn@umich.edu GET_ADDR(r0,0xb,r31) // get EI_STAT mask value 19768013Sbinkertn@umich.edu sll r0, 32, r0 // shift to upper lw 19778013Sbinkertn@umich.edu and r0, r8, r0 // compare 19788013Sbinkertn@umich.edu beq r0, 1f // check next case if nothing set 19798013Sbinkertn@umich.edu GET_ADDR(r0,0xfffd,r31) // set new MCHK code 19808013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19818013Sbinkertn@umich.edu 19828013Sbinkertn@umich.edu1: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value 19838013Sbinkertn@umich.edu GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value 19848013Sbinkertn@umich.edu and r0, r8, r0 // compare 19858013Sbinkertn@umich.edu beq r0, cont_logout_frame // check next case if nothing set 19868013Sbinkertn@umich.edu GET_ADDR(r0, 0xfffe, r31) // set new MCHK code 19878013Sbinkertn@umich.edu br r31, do_660 // setup new vector 19888013Sbinkertn@umich.edu 19898013Sbinkertn@umich.edudo_670: lda r8, scb_v_procmchk(r31) // SCB vector 19908013Sbinkertn@umich.edu br r31, do_6x0_cont 19918013Sbinkertn@umich.edudo_660: lda r8, scb_v_sysmchk(r31) // SCB vector 19928013Sbinkertn@umich.edudo_6x0_cont: 19938013Sbinkertn@umich.edu sll r8, 16, r8 // shift to proper position 19948013Sbinkertn@umich.edu mfpr r1, pt_misc // fetch current pt_misc 19958013Sbinkertn@umich.edu GET_ADDR(r4,0xffff, r31) // mask for vector field 19968013Sbinkertn@umich.edu sll r4, 16, r4 // shift to proper position 19978013Sbinkertn@umich.edu bic r1, r4, r1 // clear out old vector field 19988013Sbinkertn@umich.edu or r1, r8, r1 // merge in new vector 19998013Sbinkertn@umich.edu mtpr r1, pt_misc // save new vector field 20008013Sbinkertn@umich.edu stl_p r0, mchk_mchk_code(r14) // save new mchk code 20018013Sbinkertn@umich.edu 20028013Sbinkertn@umich.educont_logout_frame: 20038013Sbinkertn@umich.edu // Restore some GPRs from PALtemps 20048013Sbinkertn@umich.edu mfpr r0, pt0 20058013Sbinkertn@umich.edu mfpr r1, pt1 20068013Sbinkertn@umich.edu mfpr r4, pt4 20078013Sbinkertn@umich.edu 20088013Sbinkertn@umich.edu mfpr r12, pt10 // fetch original PC 20098013Sbinkertn@umich.edu blbs r12, sys_machine_check_while_in_pal // MCHK halt if machine check in pal 20108013Sbinkertn@umich.edu 20118013Sbinkertn@umich.edu//XXXbugnion pvc_jsr armc, bsr=1 20128013Sbinkertn@umich.edu bsr r12, sys_arith_and_mchk // go check for and deal with arith trap 20138013Sbinkertn@umich.edu 20148013Sbinkertn@umich.edu mtpr r31, exc_sum // Clear Exception Summary 20158013Sbinkertn@umich.edu 20168013Sbinkertn@umich.edu mfpr r25, pt10 // write exc_addr after arith_and_mchk to pickup new pc 20178013Sbinkertn@umich.edu stq_p r25, mchk_exc_addr(r14) 20188013Sbinkertn@umich.edu 20198013Sbinkertn@umich.edu // 20208013Sbinkertn@umich.edu // Set up the km trap 20218013Sbinkertn@umich.edu // 20228013Sbinkertn@umich.edu 20238013Sbinkertn@umich.edu 20248013Sbinkertn@umich.edusys_post_mchk_trap: 20258013Sbinkertn@umich.edu mfpr r25, pt_misc // Check for flag from mchk interrupt 20268013Sbinkertn@umich.edu extwl r25, 4, r25 20278013Sbinkertn@umich.edu blbs r25, sys_mchk_stack_done // Stack from already pushed if from interrupt flow 20288013Sbinkertn@umich.edu 20298013Sbinkertn@umich.edu bis r14, r31, r12 // stash pointer to logout area 20308013Sbinkertn@umich.edu mfpr r14, pt10 // get exc_addr 20318013Sbinkertn@umich.edu 20328013Sbinkertn@umich.edu sll r11, 63-3, r25 // get mode to msb 20338013Sbinkertn@umich.edu bge r25, 3f 20348013Sbinkertn@umich.edu 20358013Sbinkertn@umich.edu mtpr r31, dtb_cm 20368013Sbinkertn@umich.edu mtpr r31, ev5__ps 20378013Sbinkertn@umich.edu 20388013Sbinkertn@umich.edu mtpr r30, pt_usp // save user stack 20398013Sbinkertn@umich.edu mfpr r30, pt_ksp 20408013Sbinkertn@umich.edu 20418013Sbinkertn@umich.edu3: 20428013Sbinkertn@umich.edu lda sp, 0-osfsf_c_size(sp) // allocate stack space 20438013Sbinkertn@umich.edu nop 20448013Sbinkertn@umich.edu 20458013Sbinkertn@umich.edu stq r18, osfsf_a2(sp) // a2 20468013Sbinkertn@umich.edu stq r11, osfsf_ps(sp) // save ps 20478013Sbinkertn@umich.edu 20488013Sbinkertn@umich.edu stq r14, osfsf_pc(sp) // save pc 20498013Sbinkertn@umich.edu mfpr r25, pt_entint // get the VA of the interrupt routine 20508013Sbinkertn@umich.edu 20518013Sbinkertn@umich.edu stq r16, osfsf_a0(sp) // a0 20528013Sbinkertn@umich.edu lda r16, osfint_c_mchk(r31) // flag as mchk in a0 20538013Sbinkertn@umich.edu 20548013Sbinkertn@umich.edu stq r17, osfsf_a1(sp) // a1 20558013Sbinkertn@umich.edu mfpr r17, pt_misc // get vector 20568013Sbinkertn@umich.edu 20578013Sbinkertn@umich.edu stq r29, osfsf_gp(sp) // old gp 20588013Sbinkertn@umich.edu mtpr r25, exc_addr // 20598013Sbinkertn@umich.edu 20608013Sbinkertn@umich.edu or r31, 7, r11 // get new ps (km, high ipl) 20618013Sbinkertn@umich.edu subq r31, 1, r18 // get a -1 20628013Sbinkertn@umich.edu 20638013Sbinkertn@umich.edu extwl r17, 2, r17 // a1 <- interrupt vector 20648013Sbinkertn@umich.edu bis r31, ipl_machine_check, r25 20658013Sbinkertn@umich.edu 20668013Sbinkertn@umich.edu mtpr r25, ipl // Set internal ipl 20678013Sbinkertn@umich.edu srl r18, 42, r18 // shift off low bits of kseg addr 20688013Sbinkertn@umich.edu 20698013Sbinkertn@umich.edu sll r18, 42, r18 // shift back into position 20708013Sbinkertn@umich.edu mfpr r29, pt_kgp // get the kern r29 20718013Sbinkertn@umich.edu 20728013Sbinkertn@umich.edu or r12, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address 20738013Sbinkertn@umich.edu hw_rei_spe // out to interrupt dispatch routine 20748013Sbinkertn@umich.edu 20758013Sbinkertn@umich.edu 20768013Sbinkertn@umich.edu // 20778013Sbinkertn@umich.edu // The stack is pushed. Load up a0,a1,a2 and vector via entInt 20788013Sbinkertn@umich.edu // 20798013Sbinkertn@umich.edu // 20808013Sbinkertn@umich.edu ALIGN_BRANCH 20818013Sbinkertn@umich.edusys_mchk_stack_done: 20828013Sbinkertn@umich.edu lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0 20838013Sbinkertn@umich.edu lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector 20848013Sbinkertn@umich.edu 20858013Sbinkertn@umich.edu subq r31, 1, r18 // get a -1 20868013Sbinkertn@umich.edu mfpr r25, pt_entInt 20878013Sbinkertn@umich.edu 20888013Sbinkertn@umich.edu srl r18, 42, r18 // shift off low bits of kseg addr 20898013Sbinkertn@umich.edu mtpr r25, exc_addr // load interrupt vector 20908013Sbinkertn@umich.edu 20918013Sbinkertn@umich.edu sll r18, 42, r18 // shift back into position 20928013Sbinkertn@umich.edu or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address 20938013Sbinkertn@umich.edu 20948013Sbinkertn@umich.edu hw_rei_spe // done 20958013Sbinkertn@umich.edu 20968013Sbinkertn@umich.edu 20978013Sbinkertn@umich.edu ALIGN_BRANCH 20988013Sbinkertn@umich.edusys_cpu_mchk_not_retryable: 20998013Sbinkertn@umich.edu mfpr r6, pt_misc 21008013Sbinkertn@umich.edu extwl r6, 4, r6 // Fetch mchk code 21018013Sbinkertn@umich.edu br r31, sys_mchk_write_logout_frame // 21028013Sbinkertn@umich.edu 21038013Sbinkertn@umich.edu 21048013Sbinkertn@umich.edu 21058013Sbinkertn@umich.edu// 21068013Sbinkertn@umich.edu//sys_double_machine_check - a machine check was started, but MCES<MCHK> was 21078013Sbinkertn@umich.edu// already set. We will now double machine check halt. 21088013Sbinkertn@umich.edu// 21098013Sbinkertn@umich.edu// pt0 - old R0 21108013Sbinkertn@umich.edu// 21118013Sbinkertn@umich.edu// 21128013Sbinkertn@umich.edu 21138013Sbinkertn@umich.eduEXPORT(sys_double_machine_check) 21148013Sbinkertn@umich.edu lda r0, hlt_c_dbl_mchk(r31) 21158013Sbinkertn@umich.edu br r31, sys_enter_console 21168013Sbinkertn@umich.edu 21178013Sbinkertn@umich.edu// 21188013Sbinkertn@umich.edu// sys_machine_check_while_in_pal - a machine check was started, 21198013Sbinkertn@umich.edu// exc_addr points to a PAL PC. We will now machine check halt. 21208013Sbinkertn@umich.edu// 21218013Sbinkertn@umich.edu// pt0 - old R0 21228013Sbinkertn@umich.edu// 21238013Sbinkertn@umich.edu// 21248013Sbinkertn@umich.edusys_machine_check_while_in_pal: 21258013Sbinkertn@umich.edu stq_p r12, mchk_exc_addr(r14) // exc_addr has not yet been written 21268013Sbinkertn@umich.edu lda r0, hlt_c_mchk_from_pal(r31) 21278013Sbinkertn@umich.edu br r31, sys_enter_console 21288013Sbinkertn@umich.edu 21298013Sbinkertn@umich.edu 21308013Sbinkertn@umich.edu//ARITH and MCHK 21318013Sbinkertn@umich.edu// Check for arithmetic errors and build trap frame, 21328013Sbinkertn@umich.edu// but don't post the trap. 21338013Sbinkertn@umich.edu// on entry: 21348013Sbinkertn@umich.edu// pt10 - exc_addr 21358013Sbinkertn@umich.edu// r12 - return address 21368013Sbinkertn@umich.edu// r14 - logout frame pointer 21378013Sbinkertn@umich.edu// r13 - available 21388013Sbinkertn@umich.edu// r8,r9,r10 - available except across stq's 21398013Sbinkertn@umich.edu// pt0,1,6 - available 21408013Sbinkertn@umich.edu// 21418013Sbinkertn@umich.edu// on exit: 21428013Sbinkertn@umich.edu// pt10 - new exc_addr 21438013Sbinkertn@umich.edu// r17 = exc_mask 21448013Sbinkertn@umich.edu// r16 = exc_sum 21458013Sbinkertn@umich.edu// r14 - logout frame pointer 21468013Sbinkertn@umich.edu// 21478013Sbinkertn@umich.edu ALIGN_BRANCH 21488013Sbinkertn@umich.edusys_arith_and_mchk: 21498013Sbinkertn@umich.edu mfpr r13, ev5__exc_sum 21508013Sbinkertn@umich.edu srl r13, exc_sum_v_swc, r13 21518013Sbinkertn@umich.edu bne r13, handle_arith_and_mchk 21528013Sbinkertn@umich.edu 21538013Sbinkertn@umich.edu// XXX bugnion pvc$jsr armc, bsr=1, dest=1 21548013Sbinkertn@umich.edu ret r31, (r12) // return if no outstanding arithmetic error 21558013Sbinkertn@umich.edu 21568013Sbinkertn@umich.eduhandle_arith_and_mchk: 21578013Sbinkertn@umich.edu mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel 21588013Sbinkertn@umich.edu // no virt ref for next 2 cycles 21598013Sbinkertn@umich.edu mtpr r14, pt0 21608013Sbinkertn@umich.edu 21618013Sbinkertn@umich.edu mtpr r1, pt1 // get a scratch reg 21628013Sbinkertn@umich.edu and r11, osfps_m_mode, r1 // get mode bit 21638013Sbinkertn@umich.edu 21648013Sbinkertn@umich.edu bis r11, r31, r25 // save ps 21658013Sbinkertn@umich.edu beq r1, 1f // if zero we are in kern now 21668013Sbinkertn@umich.edu 21678013Sbinkertn@umich.edu bis r31, r31, r25 // set the new ps 21688013Sbinkertn@umich.edu mtpr r30, pt_usp // save user stack 21698013Sbinkertn@umich.edu 21708013Sbinkertn@umich.edu mfpr r30, pt_ksp // get kern stack 21718013Sbinkertn@umich.edu1: 21728013Sbinkertn@umich.edu mfpr r14, exc_addr // get pc into r14 in case stack writes fault 21738013Sbinkertn@umich.edu 21748013Sbinkertn@umich.edu lda sp, 0-osfsf_c_size(sp) // allocate stack space 21758013Sbinkertn@umich.edu mtpr r31, ev5__ps // Set Ibox current mode to kernel 21768013Sbinkertn@umich.edu 21778013Sbinkertn@umich.edu mfpr r1, pt_entArith 21788013Sbinkertn@umich.edu stq r14, osfsf_pc(sp) // save pc 21798013Sbinkertn@umich.edu 21808013Sbinkertn@umich.edu stq r17, osfsf_a1(sp) 21818013Sbinkertn@umich.edu mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle 21828013Sbinkertn@umich.edu 21838013Sbinkertn@umich.edu stq r29, osfsf_gp(sp) 21848013Sbinkertn@umich.edu stq r16, osfsf_a0(sp) // save regs 21858013Sbinkertn@umich.edu 21868013Sbinkertn@umich.edu bis r13, r31, r16 // move exc_sum to r16 21878013Sbinkertn@umich.edu stq r18, osfsf_a2(sp) 21888013Sbinkertn@umich.edu 21898013Sbinkertn@umich.edu stq r11, osfsf_ps(sp) // save ps 21908013Sbinkertn@umich.edu mfpr r29, pt_kgp // get the kern gp 21918013Sbinkertn@umich.edu 21928013Sbinkertn@umich.edu mfpr r14, pt0 // restore logout frame pointer from pt0 21938013Sbinkertn@umich.edu bis r25, r31, r11 // set new ps 21948013Sbinkertn@umich.edu 21958013Sbinkertn@umich.edu mtpr r1, pt10 // Set new PC 21968013Sbinkertn@umich.edu mfpr r1, pt1 21978013Sbinkertn@umich.edu 21988013Sbinkertn@umich.edu// XXX bugnion pvc$jsr armc, bsr=1, dest=1 21998013Sbinkertn@umich.edu ret r31, (r12) // return if no outstanding arithmetic error 22008013Sbinkertn@umich.edu 22018013Sbinkertn@umich.edu 22028013Sbinkertn@umich.edu 22038013Sbinkertn@umich.edu// sys_enter_console - Common PALcode for ENTERING console 22048013Sbinkertn@umich.edu// 22058013Sbinkertn@umich.edu// Entry: 22068013Sbinkertn@umich.edu// Entered when PAL wants to enter the console. 22078013Sbinkertn@umich.edu// usually as the result of a HALT instruction or button, 22088013Sbinkertn@umich.edu// or catastrophic error. 22098013Sbinkertn@umich.edu// 22108013Sbinkertn@umich.edu// Regs on entry... 22118013Sbinkertn@umich.edu// 22128013Sbinkertn@umich.edu// R0 = halt code 22138013Sbinkertn@umich.edu// pt0 <- r0 22148013Sbinkertn@umich.edu// 22158013Sbinkertn@umich.edu// Function: 22168013Sbinkertn@umich.edu// 22178013Sbinkertn@umich.edu// Save all readable machine state, and "call" the console 22188013Sbinkertn@umich.edu// 22198013Sbinkertn@umich.edu// Returns: 22208013Sbinkertn@umich.edu// 22218013Sbinkertn@umich.edu// 22228013Sbinkertn@umich.edu// Notes: 22238013Sbinkertn@umich.edu// 22248013Sbinkertn@umich.edu// In these routines, once the save state routine has been executed, 22258013Sbinkertn@umich.edu// the remainder of the registers become scratchable, as the only 22268013Sbinkertn@umich.edu// "valid" copy of them is the "saved" copy. 22278013Sbinkertn@umich.edu// 22288013Sbinkertn@umich.edu// Any registers or PTs that are modified before calling the save 22298013Sbinkertn@umich.edu// routine will have there data lost. The code below will save all 22308013Sbinkertn@umich.edu// state, but will loose pt 0,4,5. 22318013Sbinkertn@umich.edu// 22328013Sbinkertn@umich.edu// 22338013Sbinkertn@umich.edu 22348013Sbinkertn@umich.edu ALIGN_BLOCK 22358013Sbinkertn@umich.eduEXPORT(sys_enter_console) 22368013Sbinkertn@umich.edu mtpr r1, pt4 22378013Sbinkertn@umich.edu mtpr r3, pt5 22388013Sbinkertn@umich.edu subq r31, 1, r1 22398013Sbinkertn@umich.edu sll r1, 42, r1 22408013Sbinkertn@umich.edu ldah r1, 1(r1) 22418013Sbinkertn@umich.edu 22428013Sbinkertn@umich.edu /* taken from scrmax, seems like the obvious thing to do */ 22438013Sbinkertn@umich.edu mtpr r1, exc_addr 22448013Sbinkertn@umich.edu mfpr r1, pt4 22458013Sbinkertn@umich.edu mfpr r3, pt5 22468013Sbinkertn@umich.edu STALL 22478013Sbinkertn@umich.edu STALL 22488013Sbinkertn@umich.edu hw_rei_stall 22498013Sbinkertn@umich.edu 22508013Sbinkertn@umich.edu 22518013Sbinkertn@umich.edu// 22528013Sbinkertn@umich.edu// sys_exit_console - Common PALcode for ENTERING console 22538013Sbinkertn@umich.edu// 22548013Sbinkertn@umich.edu// Entry: 22558013Sbinkertn@umich.edu// Entered when console wants to reenter PAL. 22568013Sbinkertn@umich.edu// usually as the result of a CONTINUE. 22578013Sbinkertn@umich.edu// 22588013Sbinkertn@umich.edu// 22598013Sbinkertn@umich.edu// Regs' on entry... 22608013Sbinkertn@umich.edu// 22618013Sbinkertn@umich.edu// 22628013Sbinkertn@umich.edu// Function: 22638013Sbinkertn@umich.edu// 22648013Sbinkertn@umich.edu// Restore all readable machine state, and return to user code. 22658013Sbinkertn@umich.edu// 22668013Sbinkertn@umich.edu// 22678013Sbinkertn@umich.edu// 22688013Sbinkertn@umich.edu// 22698013Sbinkertn@umich.edu ALIGN_BLOCK 22708013Sbinkertn@umich.edusys_exit_console: 22718013Sbinkertn@umich.edu 22728013Sbinkertn@umich.edu GET_IMPURE(r1) 22738013Sbinkertn@umich.edu 22748013Sbinkertn@umich.edu // clear lock and intr_flags prior to leaving console 22758013Sbinkertn@umich.edu rc r31 // clear intr_flag 22768013Sbinkertn@umich.edu // lock flag cleared by restore_state 22778013Sbinkertn@umich.edu // TB's have been flushed 22788013Sbinkertn@umich.edu 22798013Sbinkertn@umich.edu ldq_p r3, (cns_gpr+(8*3))(r1) // restore r3 22808013Sbinkertn@umich.edu ldq_p r1, (cns_gpr+8)(r1) // restore r1 22818013Sbinkertn@umich.edu hw_rei_stall // back to user 22828013Sbinkertn@umich.edu 22838013Sbinkertn@umich.edu 22848013Sbinkertn@umich.edu// kludge_initial_pcbb - PCB for Boot use only 22858013Sbinkertn@umich.edu 22868013Sbinkertn@umich.edu ALIGN_128 22878013Sbinkertn@umich.edu.globl kludge_initial_pcbb 22888013Sbinkertn@umich.edukludge_initial_pcbb: // PCB is 128 bytes long 22898013Sbinkertn@umich.edu nop 22908013Sbinkertn@umich.edu nop 22918013Sbinkertn@umich.edu nop 22928013Sbinkertn@umich.edu nop 22938013Sbinkertn@umich.edu 22948013Sbinkertn@umich.edu nop 22958013Sbinkertn@umich.edu nop 22968013Sbinkertn@umich.edu nop 22978013Sbinkertn@umich.edu nop 22988013Sbinkertn@umich.edu 22998013Sbinkertn@umich.edu nop 23008013Sbinkertn@umich.edu nop 23018013Sbinkertn@umich.edu nop 23028013Sbinkertn@umich.edu nop 23038013Sbinkertn@umich.edu 23048013Sbinkertn@umich.edu nop 23058013Sbinkertn@umich.edu nop 23068013Sbinkertn@umich.edu nop 23078013Sbinkertn@umich.edu nop 23088013Sbinkertn@umich.edu 23098013Sbinkertn@umich.edu 23108013Sbinkertn@umich.edu// SET_SC_BC_CTL subroutine 23118013Sbinkertn@umich.edu// 23128013Sbinkertn@umich.edu// Subroutine to set the SC_CTL, BC_CONFIG, and BC_CTL registers and 23138013Sbinkertn@umich.edu// flush the Scache 23148013Sbinkertn@umich.edu// There must be no outstanding memory references -- istream or 23158013Sbinkertn@umich.edu// dstream -- when these registers are written. EV5 prefetcher is 23168013Sbinkertn@umich.edu// difficult to turn off. So, this routine needs to be exactly 32 23178013Sbinkertn@umich.edu// instructions long// the final jmp must be in the last octaword of a 23188013Sbinkertn@umich.edu// page (prefetcher doesn't go across page) 23198013Sbinkertn@umich.edu// 23208013Sbinkertn@umich.edu// 23218013Sbinkertn@umich.edu// Register expecations: 23228013Sbinkertn@umich.edu// r0 base address of CBOX iprs 23238013Sbinkertn@umich.edu// r5 value to set sc_ctl to (flush bit is added in) 23248013Sbinkertn@umich.edu// r6 value to set bc_ctl to 23258013Sbinkertn@umich.edu// r7 value to set bc_config to 23268013Sbinkertn@umich.edu// r10 return address 23278013Sbinkertn@umich.edu// r19 old sc_ctl value 23288013Sbinkertn@umich.edu// r20 old value of bc_ctl 23298013Sbinkertn@umich.edu// r21 old value of bc_config 23308013Sbinkertn@umich.edu// r23 flush scache flag 23318013Sbinkertn@umich.edu// Register usage: 23328013Sbinkertn@umich.edu// r17 sc_ctl with flush bit cleared 23338013Sbinkertn@umich.edu// r22 loop address 23348013Sbinkertn@umich.edu// 23358013Sbinkertn@umich.edu// 23368013Sbinkertn@umich.eduset_sc_bc_ctl: 23378013Sbinkertn@umich.edu ret r31, (r10) // return to where we came from 2338