1/* 2 * Copyright (c) 1993 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef DC21164FROMGASSOURCES_INCLUDED 30#define DC21164FROMGASSOURCES_INCLUDED 1 31 32/* 33** 34** INTERNAL PROCESSOR REGISTER DEFINITIONS 35** 36** The internal processor register definitions below are annotated 37** with one of the following symbols: 38** 39** RW - The register may be read and written 40** RO - The register may only be read 41** WO - The register may only be written 42** 43** For RO and WO registers, all bits and fields within the register are 44** also read-only or write-only. For RW registers, each bit or field 45** within the register is annotated with one of the following: 46** 47** RW - The bit/field may be read and written 48** RO - The bit/field may be read; writes are ignored 49** WO - The bit/field may be written; reads return UNPREDICTABLE 50** WZ - The bit/field may be written; reads return a zero value 51** W0C - The bit/field may be read; write-zero-to-clear 52** W1C - The bit/field may be read; write-one-to-clear 53** WA - The bit/field may be read; write-anything-to-clear 54** RC - The bit/field may be read, causing state to clear; 55** writes are ignored 56** 57*/ 58 59 60/* 61** 62** Ibox IPR Definitions: 63** 64*/ 65 66// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ 67#define itbTag 0x101 /* WO - ITB Tag */ 68#define itbPte 0x102 /* RW - ITB Page Table Entry */ 69#define itbAsn 0x103 /* RW - ITB Address Space Number */ 70#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ 71#define itbIa 0x105 /* WO - ITB Invalidate All */ 72#define itbIap 0x106 /* WO - ITB Invalidate All Process */ 73#define itbIs 0x107 /* WO - ITB Invalidate Single */ 74// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ 75// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ 76// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ 77#define excAddr 0x10B /* RW - Exception Address */ 78#define excSum 0x10C /* RW - Exception Summary */ 79#define excMask 0x10D /* RO - Exception Mask */ 80#define palBase 0x10E /* RW - PAL Base */ 81#define ips 0x10F /* RW - Processor Status */ 82// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ 83#define intId 0x111 /* RO - Interrupt ID */ 84#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ 85#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ 86#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ 87#define slXmit 0x116 /* WO - Serial Line Transmit */ 88#define slRcv 0x117 /* RO - Serial Line Receive */ 89// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ 90#define icFlush 0x119 /* WO - I-Cache Flush Control */ 91#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ 92#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ 93#define PmCtr 0x11C /* RW - Performance Counter */ 94 95/* 96** 97** Ibox Control/Status Register (ICSR) Bit Summary 98** 99** Extent Size Name Type Function 100** ------ ---- ---- ---- ------------------------------------ 101** <39> 1 TST RW,0 Assert Test Status 102** <38> 1 ISTA RO I-Cache BIST Status 103** <37> 1 DBS RW,1 Debug Port Select 104** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity 105** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity 106** <34> 1 FMS RW,0 Force I-Cache Miss 107** <33> 1 SLE RW,0 Enable Serial Line Interrupts 108** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts 109** <30> 1 SDE RW,0 Enable PAL Shadow Registers 110** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode 111** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode 112** <26> 1 FPE RW,0 Enable Floating Point Instructions 113** <25> 1 TMD RW,0 Disable Ibox Timeout Counter 114** <24> 1 TMM RW,0 Timeout Counter Mode 115** 116*/ 117 118#define ICSR_V_TST 39 119#define ICSR_M_TST (1<<ICSR_V_TST) 120#define ICSR_V_ISTA 38 121#define ICSR_M_ISTA (1<<ICSR_V_ISTA) 122#define ICSR_V_DBS 37 123#define ICSR_M_DBS (1<<ICSR_V_DBS) 124#define ICSR_V_FBD 36 125#define ICSR_M_FBD (1<<ICSR_V_FBD) 126#define ICSR_V_FBT 35 127#define ICSR_M_FBT (1<<ICSR_V_FBT) 128#define ICSR_V_FMS 34 129#define ICSR_M_FMS (1<<ICSR_V_FMS) 130#define ICSR_V_SLE 33 131#define ICSR_M_SLE (1<<ICSR_V_SLE) 132#define ICSR_V_CRDE 32 133#define ICSR_M_CRDE (1<<ICSR_V_CRDE) 134#define ICSR_V_SDE 30 135#define ICSR_M_SDE (1<<ICSR_V_SDE) 136#define ICSR_V_SPE 28 137#define ICSR_M_SPE (3<<ICSR_V_SPE) 138#define ICSR_V_HWE 27 139#define ICSR_M_HWE (1<<ICSR_V_HWE) 140#define ICSR_V_FPE 26 141#define ICSR_M_FPE (1<<ICSR_V_FPE) 142#define ICSR_V_TMD 25 143#define ICSR_M_TMD (1<<ICSR_V_TMD) 144#define ICSR_V_TMM 24 145#define ICSR_M_TMM (1<<ICSR_V_TMM) 146 147/* 148** 149** Serial Line Tranmit Register (SL_XMIT) 150** 151** Extent Size Name Type Function 152** ------ ---- ---- ---- ------------------------------------ 153** <7> 1 TMT WO,1 Serial line transmit data 154** 155*/ 156 157#define SLXMIT_V_TMT 7 158#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT) 159 160/* 161** 162** Serial Line Receive Register (SL_RCV) 163** 164** Extent Size Name Type Function 165** ------ ---- ---- ---- ------------------------------------ 166** <6> 1 RCV RO Serial line receive data 167** 168*/ 169 170#define SLRCV_V_RCV 6 171#define SLRCV_M_RCV (1<<SLRCV_V_RCV) 172 173/* 174** 175** Icache Parity Error Status Register (ICPERR) Bit Summary 176** 177** Extent Size Name Type Function 178** ------ ---- ---- ---- ------------------------------------ 179** <13> 1 TMR W1C Timeout reset error 180** <12> 1 TPE W1C Tag parity error 181** <11> 1 DPE W1C Data parity error 182** 183*/ 184 185#define ICPERR_V_TMR 13 186#define ICPERR_M_TMR (1<<ICPERR_V_TMR) 187#define ICPERR_V_TPE 12 188#define ICPERR_M_TPE (1<<ICPERR_V_TPE) 189#define ICPERR_V_DPE 11 190#define ICPERR_M_DPE (1<<ICPERR_V_DPE) 191 192#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE) 193 194/* 195** 196** Exception Summary Register (EXC_SUM) Bit Summary 197** 198** Extent Size Name Type Function 199** ------ ---- ---- ---- ------------------------------------ 200** <16> 1 IOV WA Integer overflow 201** <15> 1 INE WA Inexact result 202** <14> 1 UNF WA Underflow 203** <13> 1 FOV WA Overflow 204** <12> 1 DZE WA Division by zero 205** <11> 1 INV WA Invalid operation 206** <10> 1 SWC WA Software completion 207** 208*/ 209 210#define EXC_V_IOV 16 211#define EXC_M_IOV (1<<EXC_V_IOV) 212#define EXC_V_INE 15 213#define EXC_M_INE (1<<EXC_V_INE) 214#define EXC_V_UNF 14 215#define EXC_M_UNF (1<<EXC_V_UNF) 216#define EXC_V_FOV 13 217#define EXC_M_FOV (1<<EXC_V_FOV) 218#define EXC_V_DZE 12 219#define EXC_M_DZE (1<<EXC_V_DZE) 220#define EXC_V_INV 11 221#define EXC_M_INV (1<<EXC_V_INV) 222#define EXC_V_SWC 10 223#define EXC_M_SWC (1<<EXC_V_SWC) 224 225/* 226** 227** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary 228** 229** Extent Size Name Type Function 230** ------ ---- ---- ---- --------------------------------- 231** <33> 1 SLC W1C Clear Serial Line interrupt 232** <32> 1 CRDC W1C Clear Correctable Read Data interrupt 233** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt 234** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt 235** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt 236** 237*/ 238 239#define HWINT_V_SLC 33 240#define HWINT_M_SLC (1<<HWINT_V_SLC) 241#define HWINT_V_CRDC 32 242#define HWINT_M_CRDC (1<<HWINT_V_CRDC) 243#define HWINT_V_PC2C 29 244#define HWINT_M_PC2C (1<<HWINT_V_PC2C) 245#define HWINT_V_PC1C 28 246#define HWINT_M_PC1C (1<<HWINT_V_PC1C) 247#define HWINT_V_PC0C 27 248#define HWINT_M_PC0C (1<<HWINT_V_PC0C) 249 250/* 251** 252** Interrupt Summary Register (ISR) Bit Summary 253** 254** Extent Size Name Type Function 255** ------ ---- ---- ---- --------------------------------- 256** <34> 1 HLT RO External Halt interrupt 257** <33> 1 SLI RO Serial Line interrupt 258** <32> 1 CRD RO Correctable ECC errors 259** <31> 1 MCK RO System Machine Check 260** <30> 1 PFL RO Power Fail 261** <29> 1 PC2 RO Performance Counter 2 interrupt 262** <28> 1 PC1 RO Performance Counter 1 interrupt 263** <27> 1 PC0 RO Performance Counter 0 interrupt 264** <23> 1 I23 RO External Hardware interrupt 265** <22> 1 I22 RO External Hardware interrupt 266** <21> 1 I21 RO External Hardware interrupt 267** <20> 1 I20 RO External Hardware interrupt 268** <19> 1 ATR RO Async. System Trap request 269** <18:4> 15 SIRR RO,0 Software Interrupt request 270** <3:0> 4 ASTRR RO Async. System Trap request (USEK) 271** 272**/ 273 274#define ISR_V_HLT 34 275#define ISR_M_HLT (1<<ISR_V_HLT) 276#define ISR_V_SLI 33 277#define ISR_M_SLI (1<<ISR_V_SLI) 278#define ISR_V_CRD 32 279#define ISR_M_CRD (1<<ISR_V_CRD) 280#define ISR_V_MCK 31 281#define ISR_M_MCK (1<<ISR_V_MCK) 282#define ISR_V_PFL 30 283#define ISR_M_PFL (1<<ISR_V_PFL) 284#define ISR_V_PC2 29 285#define ISR_M_PC2 (1<<ISR_V_PC2) 286#define ISR_V_PC1 28 287#define ISR_M_PC1 (1<<ISR_V_PC1) 288#define ISR_V_PC0 27 289#define ISR_M_PC0 (1<<ISR_V_PC0) 290#define ISR_V_I23 23 291#define ISR_M_I23 (1<<ISR_V_I23) 292#define ISR_V_I22 22 293#define ISR_M_I22 (1<<ISR_V_I22) 294#define ISR_V_I21 21 295#define ISR_M_I21 (1<<ISR_V_I21) 296#define ISR_V_I20 20 297#define ISR_M_I20 (1<<ISR_V_I20) 298#define ISR_V_ATR 19 299#define ISR_M_ATR (1<<ISR_V_ATR) 300#define ISR_V_SIRR 4 301#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR) 302#define ISR_V_ASTRR 0 303#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR) 304 305/* 306** 307** Mbox and D-Cache IPR Definitions: 308** 309*/ 310 311#define dtbAsn 0x200 /* WO - DTB Address Space Number */ 312#define dtbCm 0x201 /* WO - DTB Current Mode */ 313#define dtbTag 0x202 /* WO - DTB Tag */ 314#define dtbPte 0x203 /* RW - DTB Page Table Entry */ 315#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */ 316#define mmStat 0x205 /* RO - D-Stream MM Fault Status */ 317// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */ 318#define vaForm 0x207 /* RO - Formatted Virtual Address */ 319#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */ 320#define dtbIap 0x209 /* WO - DTB Invalidate All Process */ 321#define dtbIa 0x20A /* WO - DTB Invalidate All */ 322#define dtbIs 0x20B /* WO - DTB Invalidate Single */ 323#define altMode 0x20C /* WO - Alternate Mode */ 324// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */ 325#define ccCtl 0x20E /* WO - Cycle Counter Control */ 326// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */ 327#define dcFlush 0x210 /* WO - Dcache Flush */ 328#define dcPerr 0x212 /* RW - Dcache Parity Error Status */ 329#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */ 330#define dcTestTag 0x214 /* RW - Dcache Test Tag */ 331#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */ 332#define dcMode 0x216 /* RW - Dcache Mode */ 333#define mafMode 0x217 /* RW - Miss Address File Mode */ 334 335/* 336** 337** D-Stream MM Fault Status Register (MM_STAT) Bit Summary 338** 339** Extent Size Name Type Function 340** ------ ---- ---- ---- --------------------------------- 341** <16:11> 6 OPCODE RO Opcode of faulting instruction 342** <10:06> 5 RA RO Ra field of faulting instruction 343** <5> 1 BAD_VA RO Bad virtual address 344** <4> 1 DTB_MISS RO Reference resulted in DTB miss 345** <3> 1 FOW RO Fault on write 346** <2> 1 FOR RO Fault on read 347** <1> 1 ACV RO Access violation 348** <0> 1 WR RO Reference type 349** 350*/ 351 352#define MMSTAT_V_OPC 11 353#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC) 354#define MMSTAT_V_RA 6 355#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA) 356#define MMSTAT_V_BAD_VA 5 357#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA) 358#define MMSTAT_V_DTB_MISS 4 359#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS) 360#define MMSTAT_V_FOW 3 361#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW) 362#define MMSTAT_V_FOR 2 363#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR) 364#define MMSTAT_V_ACV 1 365#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV) 366#define MMSTAT_V_WR 0 367#define MMSTAT_M_WR (1<<MMSTAT_V_WR) 368 369 370/* 371** 372** Mbox Control Register (MCSR) Bit Summary 373** 374** Extent Size Name Type Function 375** ------ ---- ---- ---- --------------------------------- 376** <5> 1 DBG1 RW,0 Mbox Debug Packet Select 377** <4> 1 E_BE RW,0 Ebox Big Endian mode enable 378** <3> 1 DBG0 RW,0 Debug Test Select 379** <2:1> 2 SP RW,0 Superpage mode enable 380** <0> 1 M_BE RW,0 Mbox Big Endian mode enable 381** 382*/ 383 384#define MCSR_V_DBG1 5 385#define MCSR_M_DBG1 (1<<MCSR_V_DBG1) 386#define MCSR_V_E_BE 4 387#define MCSR_M_E_BE (1<<MCSR_V_E_BE) 388#define MCSR_V_DBG0 3 389#define MCSR_M_DBG0 (1<<MCSR_V_DBG0) 390#define MCSR_V_SP 1 391#define MCSR_M_SP (3<<MCSR_V_SP) 392#define MCSR_V_M_BE 0 393#define MCSR_M_M_BE (1<<MCSR_V_M_BE) 394 395/* 396** 397** Dcache Parity Error Status Register (DCPERR) Bit Summary 398** 399** Extent Size Name Type Function 400** ------ ---- ---- ---- ------------------------------------ 401** <5> 1 TP1 RO Dcache bank 1 tag parity error 402** <4> 1 TP0 RO Dcache bank 0 tag parity error 403** <3> 1 DP1 RO Dcache bank 1 data parity error 404** <2> 1 DP0 RO Dcache bank 0 data parity error 405** <1> 1 LOCK W1C Locks/clears bits <5:2> 406** <0> 1 SEO W1C Second Dcache parity error occurred 407** 408*/ 409 410#define DCPERR_V_TP1 5 411#define DCPERR_M_TP1 (1<<DCPERR_V_TP1) 412#define DCPERR_V_TP0 4 413#define DCPERR_M_TP0 (1<<DCPERR_V_TP0) 414#define DCPERR_V_DP1 3 415#define DCPERR_M_DP1 (1<<DCPERR_V_DP1) 416#define DCPERR_V_DP0 2 417#define DCPERR_M_DP0 (1<<DCPERR_V_DP0) 418#define DCPERR_V_LOCK 1 419#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK) 420#define DCPERR_V_SEO 0 421#define DCPERR_M_SEO (1<<DCPERR_V_SEO) 422 423#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO) 424 425/* 426** 427** Dcache Mode Register (DC_MODE) Bit Summary 428** 429** Extent Size Name Type Function 430** ------ ---- ---- ---- --------------------------------- 431** <4> 1 DOA RO Hardware Dcache Disable 432** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting 433** <2> 1 BAD_DP RW,0 Force Dcache data bad parity 434** <1> 1 FHIT RW,0 Force Dcache hit 435** <0> 1 ENA RW,0 Software Dcache Enable 436** 437*/ 438 439#define DC_V_DOA 4 440#define DC_M_DOA (1<<DC_V_DOA) 441#define DC_V_PERR_DIS 3 442#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS) 443#define DC_V_BAD_DP 2 444#define DC_M_BAD_DP (1<<DC_V_BAD_DP) 445#define DC_V_FHIT 1 446#define DC_M_FHIT (1<<DC_V_FHIT) 447#define DC_V_ENA 0 448#define DC_M_ENA (1<<DC_V_ENA) 449 450/* 451** 452** Miss Address File Mode Register (MAF_MODE) Bit Summay 453** 454** Extent Size Name Type Function 455** ------ ---- ---- ---- --------------------------------- 456** <7> 1 WB RO,0 If set, pending WB request 457** <6> 1 DREAD RO,0 If set, pending D-read request 458** 459*/ 460 461#define MAF_V_WB_PENDING 7 462#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING) 463#define MAF_V_DREAD_PENDING 6 464#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING) 465 466/* 467** 468** Cbox IPR Definitions: 469** 470*/ 471 472#define scCtl 0x0A8 /* RW - Scache Control */ 473#define scStat 0x0E8 /* RO - Scache Error Status */ 474#define scAddr 0x188 /* RO - Scache Error Address */ 475#define bcCtl 0x128 /* WO - Bcache/System Interface Control */ 476#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */ 477#define bcTagAddr 0x108 /* RO - Bcache Tag */ 478#define eiStat 0x168 /* RO - Bcache/System Error Status */ 479#define eiAddr 0x148 /* RO - Bcache/System Error Address */ 480#define fillSyn 0x068 /* RO - Fill Syndrome */ 481#define ldLock 0x1E8 /* RO - LDx_L Address */ 482 483/* 484** 485** Scache Control Register (SC_CTL) Bit Summary 486** 487** Extent Size Name Type Function 488** ------ ---- ---- ---- --------------------------------- 489** <15:13> 3 SET_EN RW,1 Set enable 490** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select 491** <11:08> 4 FB_DP RW,0 Force bad data parity 492** <07:02> 6 TAG_STAT RW Tag status and parity 493** <1> 1 FLUSH RW,0 If set, clear all tag valid bits 494** <0> 1 FHIT RW,0 Force hits 495** 496*/ 497 498#define SC_V_SET_EN 13 499#define SC_M_SET_EN (7<<SC_V_SET_EN) 500#define SC_V_BLK_SIZE 12 501#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE) 502#define SC_V_FB_DP 8 503#define SC_M_FB_DP (0xF<<SC_V_FB_DP) 504#define SC_V_TAG_STAT 2 505#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT) 506#define SC_V_FLUSH 1 507#define SC_M_FLUSH (1<<SC_V_FLUSH) 508#define SC_V_FHIT 0 509#define SC_M_FHIT (1<<SC_V_FHIT) 510 511/* 512** 513** Bcache Control Register (BC_CTL) Bit Summary 514** 515** Extent Size Name Type Function 516** ------ ---- ---- ---- --------------------------------- 517** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer 518** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads 519** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select 520** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select 521** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining 522** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins 523** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error 524** <14:13> 2 BC_BAD_DAT WO,0 Force bad data 525** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity 526** <7> 1 BC_FHIT WO,0 Bcache force hit 527** <6> 1 EI_ECC WO,1 ECC or byte parity mode 528** <5> 1 VTM_FIRST WO,1 Drive out victim block address first 529** <4> 1 CORR_FILL_DAT WO,1 Correct fill data 530** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins 531** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins 532** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. 533** <0> 1 BC_ENA W0,0 Bcache enable 534** 535*/ 536#define BC_V_DIS_SC_VIC_BUF 27 537#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF) 538#define BC_V_DIS_BAF_BYP 26 539#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP) 540#define BC_V_DBG_MUX_SEL 25 541#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL) 542#define BC_V_PM_MUX_SEL 19 543#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL) 544#define BC_V_BC_WAVE 17 545#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE) 546#define BC_V_TL_PIPE_LATCH 16 547#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH) 548#define BC_V_EI_DIS_ERR 15 549#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR) 550#define BC_V_BC_BAD_DAT 13 551#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT) 552#define BC_V_BC_TAG_STAT 8 553#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT) 554#define BC_V_BC_FHIT 7 555#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT) 556#define BC_V_EI_ECC_OR_PARITY 6 557#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY) 558#define BC_V_VTM_FIRST 5 559#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST) 560#define BC_V_CORR_FILL_DAT 4 561#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT) 562#define BC_V_EI_CMD_GRP3 3 563#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3) 564#define BC_V_EI_CMD_GRP2 2 565#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2) 566#define BC_V_ALLOC_CYC 1 567#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC) 568#define BC_V_BC_ENA 0 569#define BC_M_BC_ENA (1<<BC_V_BC_ENA) 570 571#define BC_K_DFAULT \ 572 (((BC_M_EI_DIS_ERR) | \ 573 (BC_M_EI_ECC_OR_PARITY) | \ 574 (BC_M_VTM_FIRST) | \ 575 (BC_M_CORR_FILL_DAT))>>1) 576/* 577** 578** Bcache Configuration Register (BC_CONFIG) Bit Summary 579** 580** Extent Size Name Type Function 581** ------ ---- ---- ---- --------------------------------- 582** <35:29> 7 RSVD WO Reserved - Must Be Zero 583** <28:20> 9 WE_CTL WO,0 Bcache write enable control 584** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero 585** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset 586** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero 587** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing 588** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles 589** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles 590** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero 591** <02:00> 3 SIZE WO,1 Bcache size 592*/ 593#define BC_V_WE_CTL 20 594#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL) 595#define BC_V_WE_OFF 16 596#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF) 597#define BC_V_RD_WR_SPC 12 598#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC) 599#define BC_V_WR_SPD 8 600#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD) 601#define BC_V_RD_SPD 4 602#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD) 603#define BC_V_SIZE 0 604#define BC_M_SIZE (0x7<<BC_V_SIZE) 605 606#define BC_K_CONFIG \ 607 ((0x1<<BC_V_WE_OFF) | \ 608 (0x7<<BC_V_RD_WR_SPC) | \ 609 (0x4<<BC_V_WR_SPD) | \ 610 (0x4<<BC_V_RD_SPD) | \ 611 (0x1<<BC_V_SIZE)) 612 613/* 614** 615** DECchip 21164 Privileged Architecture Library Entry Offsets: 616** 617** Entry Name Offset (Hex) 618** 619** RESET 0000 620** IACCVIO 0080 621** INTERRUPT 0100 622** ITB_MISS 0180 623** DTB_MISS (Single) 0200 624** DTB_MISS (Double) 0280 625** UNALIGN 0300 626** D_FAULT 0380 627** MCHK 0400 628** OPCDEC 0480 629** ARITH 0500 630** FEN 0580 631** CALL_PAL (Privileged) 2000 632** CALL_PAL (Unprivileged) 3000 633** 634*/ 635 636#define PAL_RESET_ENTRY 0x0000 637#define PAL_IACCVIO_ENTRY 0x0080 638#define PAL_INTERRUPT_ENTRY 0x0100 639#define PAL_ITB_MISS_ENTRY 0x0180 640#define PAL_DTB_MISS_ENTRY 0x0200 641#define PAL_DOUBLE_MISS_ENTRY 0x0280 642#define PAL_UNALIGN_ENTRY 0x0300 643#define PAL_D_FAULT_ENTRY 0x0380 644#define PAL_MCHK_ENTRY 0x0400 645#define PAL_OPCDEC_ENTRY 0x0480 646#define PAL_ARITH_ENTRY 0x0500 647#define PAL_FEN_ENTRY 0x0580 648#define PAL_CALL_PAL_PRIV_ENTRY 0x2000 649#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000 650 651/* 652** 653** Architecturally Reserved Opcode (PALRES) Definitions: 654** 655*/ 656 657#define mtpr hw_mtpr 658#define mfpr hw_mfpr 659 660#define ldl_a hw_ldl/a 661#define ldq_a hw_ldq/a 662#define stq_a hw_stq/a 663#define stl_a hw_stl/a 664 665#define ldl_p hw_ldl/p 666#define ldq_p hw_ldq/p 667#define stl_p hw_stl/p 668#define stq_p hw_stq/p 669 670/* 671** Virtual PTE fetch variants of HW_LD. 672*/ 673#define ld_vpte hw_ldq/v 674 675/* 676** Physical mode load-lock and store-conditional variants of 677** HW_LD and HW_ST. 678*/ 679 680#define ldq_lp hw_ldq/pl 681#define stq_cp hw_stq/pc 682 683/* 684** 685** General Purpose Register Definitions: 686** 687*/ 688 689#define r0 $0 690#define r1 $1 691#define r2 $2 692#define r3 $3 693#define r4 $4 694#define r5 $5 695#define r6 $6 696#define r7 $7 697#define r8 $8 698#define r9 $9 699#define r10 $10 700#define r11 $11 701#define r12 $12 702#define r13 $13 703#define r14 $14 704#define r15 $15 705#define r16 $16 706#define r17 $17 707#define r18 $18 708#define r19 $19 709#define r20 $20 710#define r21 $21 711#define r22 $22 712#define r23 $23 713#define r24 $24 714#define r25 $25 715#define r26 $26 716#define r27 $27 717#define r28 $28 718#define r29 $29 719#define r30 $30 720#define r31 $31 721 722/* 723** 724** Floating Point Register Definitions: 725** 726*/ 727 728#define f0 $f0 729#define f1 $f1 730#define f2 $f2 731#define f3 $f3 732#define f4 $f4 733#define f5 $f5 734#define f6 $f6 735#define f7 $f7 736#define f8 $f8 737#define f9 $f9 738#define f10 $f10 739#define f11 $f11 740#define f12 $f12 741#define f13 $f13 742#define f14 $f14 743#define f15 $f15 744#define f16 $f16 745#define f17 $f17 746#define f18 $f18 747#define f19 $f19 748#define f20 $f20 749#define f21 $f21 750#define f22 $f22 751#define f23 $f23 752#define f24 $f24 753#define f25 $f25 754#define f26 $f26 755#define f27 $f27 756#define f28 $f28 757#define f29 $f29 758#define f30 $f30 759#define f31 $f31 760 761/* 762** 763** PAL Temporary Register Definitions: 764** 765*/ 766 767// covered by fetch distribution..pb Nov/95 768 769// #define pt0 0x140 770// #define pt1 0x141 771// #define pt2 0x142 772// #define pt3 0x143 773// #define pt4 0x144 774// #define pt5 0x145 775// #define pt6 0x146 776// #define pt7 0x147 777// #define pt8 0x148 778// #define pt9 0x149 779// #define pt10 0x14A 780// #define pt11 0x14B 781// #define pt12 0x14C 782// #define pt13 0x14D 783// #define pt14 0x14E 784// #define pt15 0x14F 785// #define pt16 0x150 786// #define pt17 0x151 787// #define pt18 0x152 788// #define pt19 0x153 789// #define pt20 0x154 790// #define pt21 0x155 791// #define pt22 0x156 792// #define pt23 0x157 793 794/* 795** PAL Shadow Registers: 796** 797** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and 798** ICSR<SDE> = 1. 799*/ 800 801#define p0 r8 /* ITB/DTB Miss Scratch */ 802#define p1 r9 /* ITB/DTB Miss Scratch */ 803#define p2 r10 /* ITB/DTB Miss Scratch */ 804#define p3 r11 805// #define ps r11 /* Processor Status */ 806#define p4 r12 /* Local Scratch */ 807#define p5 r13 /* Local Scratch */ 808#define p6 r14 /* Local Scratch */ 809#define p7 r25 /* Local Scratch */ 810 811/* 812** SRM Defined State Definitions: 813*/ 814 815/* 816** This table is an accounting of the DECchip 21164 storage used to 817** implement the SRM defined state for OSF/1. 818** 819** IPR Name Internal Storage 820** -------- ---------------- 821** Processor Status ps, dtbCm, ipl, r11 822** Program Counter Ibox 823** Interrupt Entry ptEntInt 824** Arith Trap Entry ptEntArith 825** MM Fault Entry ptEntMM 826** Unaligned Access Entry ptEntUna 827** Instruction Fault Entry ptEntIF 828** Call System Entry ptEntSys 829** User Stack Pointer ptUsp 830** Kernel Stack Pointer ptKsp 831** Kernel Global Pointer ptKgp 832** System Value ptSysVal 833** Page Table Base Register ptPtbr 834** Virtual Page Table Base iVptBr, mVptBr 835** Process Control Block Base ptPcbb 836** Address Space Number itbAsn, dtbAsn 837** Cycle Counter cc, ccCtl 838** Float Point Enable icsr 839** Lock Flag Cbox/System 840** Unique PCB 841** Who-Am-I ptWhami 842*/ 843 844#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ 845#define ptImpure pt3 /* Pointer To PAL Scratch Area */ 846#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ 847#define ptIntMask pt8 /* Interrupt Enable Mask */ 848#define ptEntSys pt9 /* Call System Dispatch Entry */ 849#define ptTrap pt11 850#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ 851#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ 852#if defined(KDEBUG) 853#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ 854#endif /* KDEBUG */ 855#define ptMisc pt16 /* Miscellaneous Flags */ 856#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ 857#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ 858#define ptSysVal pt17 /* Per-Processor System Value */ 859#define ptUsp pt18 /* User Stack Pointer */ 860#define ptKsp pt19 /* Kernel Stack Pointer */ 861#define ptPtbr pt20 /* Page Table Base Register */ 862#define ptEntMM pt21 /* MM Fault Dispatch Entry */ 863#define ptKgp pt22 /* Kernel Global Pointer */ 864#define ptPcbb pt23 /* Process Control Block Base */ 865 866/* 867** 868** Miscellaneous PAL State Flags (ptMisc) Bit Summary 869** 870** Extent Size Name Function 871** ------ ---- ---- --------------------------------- 872** <55:48> 8 SWAP Swap PALcode flag -- character 'S' 873** <47:32> 16 MCHK Machine Check Error code 874** <31:16> 16 SCB System Control Block vector 875** <15:08> 8 WHAMI Who-Am-I identifier 876** <04:00> 5 MCES Machine Check Error Summary bits 877** 878*/ 879 880#define PT16_V_MCES 0 881#define PT16_V_WHAMI 8 882#define PT16_V_SCB 16 883#define PT16_V_MCHK 32 884#define PT16_V_SWAP 48 885 886#endif /* DC21164FROMGASSOURCES_INCLUDED */ 887