Searched refs:ports (Results 1 - 23 of 23) sorted by relevance

/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.cc58 // create the ports
60 ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
70 for (int i = 0; i < ports.size(); i++)
71 delete ports[i];
77 assert(ports.size() > 0);
88 if (idx >= static_cast<int>(ports.size())) {
92 return *ports[idx];
111 assert(idx >= 0 && idx < ports.size());
113 return ports[idx];
H A DRubyDirectedTester.hh101 std::vector<MasterPort*> ports; member in class:RubyDirectedTester
/gem5/src/systemc/tests/systemc/1666-2011-compliance/sc_vector/
H A Dsc_vector.cpp90 sc_vector<sc_port<i_f> > ports; member in struct:Initiator
93 : ports("ports", 4)
100 for (unsigned int i = 0; i < ports.size(); i++) // Use method size() with vector
103 ports[i]->method(); // Use operator[] with vector
149 port_type ports; // Vector-of-ports member in struct:M
191 : ports("ports", N)
206 sc_assert( ports
[all...]
/gem5/src/systemc/core/
H A Dmodule.cc109 panic_if(proxies.size() > ports.size(),
110 "Trying to bind %d interfaces/ports to %d ports.\n",
111 proxies.size(), ports.size());
114 auto portIt = ports.begin();
H A Dsc_port.cc77 m->ports.push_back(this);
H A Dmodule.hh127 std::vector<::sc_core::sc_port_base *> ports; member in class:sc_gem5::Module
/gem5/tests/configs/
H A Dmemtest-ruby.py61 options.ports=32
102 # Tie the cpu port to the ruby cpu ports and
H A Drubytest-ruby.py62 options.ports=32
104 # Tie the ruby tester ports to the ruby cpu read and write ports
/gem5/configs/ruby/
H A DMESI_Two_Level.py86 # number of cpu ports connected to the tester object, which
104 transitions_per_cycle = options.ports,
148 transitions_per_cycle = options.ports,
199 transitions_per_cycle = options.ports,
H A DMOESI_CMP_directory.py100 # number of cpu ports connected to the tester object, which
114 transitions_per_cycle=options.ports,
168 transitions_per_cycle = options.ports,
227 transitions_per_cycle = options.ports,
H A DMOESI_CMP_token.py95 # number of cpu ports connected to the tester object, which
118 transitions_per_cycle=options.ports,
163 transitions_per_cycle = options.ports,
232 transitions_per_cycle = options.ports,
H A DMI_example.py79 # number of cpu ports connected to the tester object, which
93 transitions_per_cycle=options.ports,
159 transitions_per_cycle = options.ports,
H A DMOESI_hammer.py94 # number of cpu ports connected to the tester object, which
110 transitions_per_cycle=options.ports,
224 transitions_per_cycle = options.ports,
H A DMESI_Three_Level.py101 # number of cpu ports connected to the tester object, which
176 transitions_per_cycle = options.ports,
227 transitions_per_cycle = options.ports,
H A DRuby.py70 parser.add_option("--ports", action="store", type="int", default=4,
72 for the number of ports.")
/gem5/src/sim/
H A Dcxx_config.hh91 /** Similar to ParamDesc to describe ports */
113 std::map<std::string, PortDesc *> ports; member in class:CxxConfigDirectoryEntry
205 /** Get the peer (connected) ports of the named ports */
H A Dcxx_manager.cc343 /* Find the number of ports that will need binding and set the
345 for (auto i = entry.ports.begin(); i != entry.ports.end(); ++i) {
531 DPRINTF(CxxConfig, "Binding ports of object: %s (%s)\n",
534 for (auto i = entry.ports.begin(); i != entry.ports.end(); ++i) {
543 /* Only handle master ports as binding only needs to happen once
544 * for each observed pair of ports */
/gem5/src/gpu-compute/
H A Dtlb_coalescer.cc57 // create the slave ports based on the number of connected ports
63 // create the master ports based on the number of connected ports
204 SlavePort *return_port = sender_state->ports.back();
205 sender_state->ports.pop_back();
243 sender_state->ports.push_back(this);
H A Dgpu_tlb.hh306 // TLB ports on the cpu Side
308 // TLB ports on the memory side
348 std::vector<SlavePort*>ports; member in struct:X86ISA::GpuTLB::TranslationState
H A Dcompute_unit.cc1101 assert(!translation_state->ports.size());
1329 assert(!translation_state->ports.size());
/gem5/src/mem/
H A Dsnoop_filter.hh65 * sharers/ports. The snoop filter ties into the flows of requests
91 // Change for systems with more than 256 ports tracked by this object
104 * Init a new snoop filter and tell it about all the slave ports
107 * @param slave_ports Slave ports that the bus is attached to.
121 // make sure we can deal with this many ports
123 "Snoop filter only supports %d snooping ports, got %d\n",
129 * return a list of other slave ports that need forwarding of the
137 * @return Pair of a vector of snoop target ports and lookup latency.
206 * limits the number of snooping ports supported per crossbar.
249 * Converts a bitmask of ports int
[all...]
/gem5/src/python/m5/
H A DSimObject.py195 code('ports["%s"] = new PortDesc("%s", %s, %s);' %
524 # new (or overriding existing) parameters or ports, setting
694 ports = cls._ports.local
738 for port in ports.values()
791 ports = cls._ports.local
895 for port in ports.values():
928 for port in ports.values():
1218 # since we will be creating new references for all ports.
1502 # Unproxy ports in sorted order so that 'append' operations on
1503 # vector ports ar
[all...]
/gem5/src/mem/slicc/symbols/
H A DStateMachine.py1136 for buf_name, ports in in_msg_bufs.items():
1137 if len(ports) > 1:
1138 # only produce checks when a buffer is shared by multiple ports
1140 if (${{buf_name}}->isReady(clockEdge()) && rejected[${{port_to_buf_map[ports[0]]}}] == ${{len(ports)}})
1144 "All ports rejected a message. "

Completed in 41 milliseconds