1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/directedtest/RubyDirectedTester.hh"
43
44#include "base/trace.hh"
45#include "cpu/testers/directedtest/DirectedGenerator.hh"
46#include "debug/DirectedTest.hh"
47#include "sim/sim_exit.hh"
48
49RubyDirectedTester::RubyDirectedTester(const Params *p)
50  : ClockedObject(p),
51    directedStartEvent([this]{ wakeup(); }, "Directed tick",
52                       false, Event::CPU_Tick_Pri),
53    m_requests_to_complete(p->requests_to_complete),
54    generator(p->generator)
55{
56    m_requests_completed = 0;
57
58    // create the ports
59    for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
60        ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
61                                    this, i));
62    }
63
64    // add the check start event to the event queue
65    schedule(directedStartEvent, 1);
66}
67
68RubyDirectedTester::~RubyDirectedTester()
69{
70    for (int i = 0; i < ports.size(); i++)
71        delete ports[i];
72}
73
74void
75RubyDirectedTester::init()
76{
77    assert(ports.size() > 0);
78    generator->setDirectedTester(this);
79}
80
81Port &
82RubyDirectedTester::getPort(const std::string &if_name, PortID idx)
83{
84    if (if_name != "cpuPort") {
85        // pass it along to our super class
86        return ClockedObject::getPort(if_name, idx);
87    } else {
88        if (idx >= static_cast<int>(ports.size())) {
89            panic("RubyDirectedTester::getPort: unknown index %d\n", idx);
90        }
91
92        return *ports[idx];
93    }
94}
95
96bool
97RubyDirectedTester::CpuPort::recvTimingResp(PacketPtr pkt)
98{
99    tester->hitCallback(id, pkt->getAddr());
100
101    //
102    // Now that the tester has completed, delete the packet, then return
103    //
104    delete pkt;
105    return true;
106}
107
108MasterPort*
109RubyDirectedTester::getCpuPort(int idx)
110{
111    assert(idx >= 0 && idx < ports.size());
112
113    return ports[idx];
114}
115
116void
117RubyDirectedTester::hitCallback(NodeID proc, Addr addr)
118{
119    DPRINTF(DirectedTest,
120            "completed request for proc: %d addr: 0x%x\n",
121            proc,
122            addr);
123
124    generator->performCallback(proc, addr);
125    schedule(directedStartEvent, curTick());
126}
127
128void
129RubyDirectedTester::wakeup()
130{
131    if (m_requests_completed < m_requests_to_complete) {
132        if (!generator->initiate()) {
133            schedule(directedStartEvent, curTick() + 1);
134        }
135    } else {
136        exitSimLoop("Ruby DirectedTester completed");
137    }
138}
139
140RubyDirectedTester *
141RubyDirectedTesterParams::create()
142{
143    return new RubyDirectedTester(this);
144}
145