/gem5/src/arch/hsail/insts/ |
H A D | gpu_static_inst.cc | 43 const std::string &opcode) 44 : GPUStaticInst(opcode), hsailCode(obj->currentCode) 51 disassembly = opcode; 42 HsailGPUStaticInst(const BrigObject *obj, const std::string &opcode) argument
|
H A D | gpu_static_inst.hh | 56 HsailGPUStaticInst(const BrigObject *obj, const std::string &opcode);
|
H A D | decl.hh | 112 disassembly = csprintf("%s%s %s", opcode, opcode_suffix(), 125 const char *opcode) 126 : HsailGPUStaticInst(obj, opcode) 213 const char *opcode) 216 NumSrcOperands>(ib, obj, opcode) 234 disassembly = csprintf("%s %s,%s,%s,%s", opcode, dest.disassemble(), 242 const char *opcode) 243 : HsailGPUStaticInst(obj, opcode) 365 const BrigObject *obj, const char *opcode) 370 obj, opcode) 124 CommonInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 212 ArithInst(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 240 ThreeNonUniformSourceInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 364 ThreeNonUniformSourceInst(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 380 CmovInst(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 394 ExtractInsertInst(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 420 TwoNonUniformSourceInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 524 TwoNonUniformSourceInst(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 571 ClassInst(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument 582 ShiftInst(const Brig::BrigInstBase *ib, const BrigObject *obj, const char *opcode) argument [all...] |
H A D | mem_impl.hh | 48 this->disassembly = csprintf("%s_%s %s,%s", this->opcode, 81 this->disassembly = csprintf("%s_%s_%s %s,%s", this->opcode, 88 this->disassembly = csprintf("%s_%s_%s (%s,%s), %s", this->opcode, 96 this->disassembly = csprintf("%s_%s_%s (%s,%s,%s), %s", this->opcode, 106 this->opcode, 510 this->disassembly = csprintf("%s_%s_%s %s,%s", this->opcode, 517 this->disassembly = csprintf("%s_%s_%s (%s,%s), %s", this->opcode, 526 this->opcode, 630 csprintf("%s_%s_%s_%s %s,%s", this->opcode, 637 csprintf("%s_%s_%s_%s %s", this->opcode, [all...] |
H A D | branch.hh | 122 disassembly = csprintf("%s%s %s", opcode, widthClause, 254 disassembly = csprintf("%s%s %s,%s", opcode, widthClause, 396 disassembly = csprintf("%s%s %s", opcode, widthClause,
|
H A D | mem.hh | 230 if (ib->opcode == BRIG_OPCODE_LD) { 800 if (ib->opcode == BRIG_OPCODE_ST) { 1182 if (ib->opcode == Brig::BRIG_OPCODE_ATOMIC || 1183 ib->opcode == Brig::BRIG_OPCODE_ATOMICNORET) { 1224 Brig::BrigOpcode opcode; member in class:HsailISA::AtomicInstBase 1238 opcode = (BrigOpcode)ib->opcode; 1240 assert(opcode == Brig::BRIG_OPCODE_ATOMICNORET || 1241 opcode == Brig::BRIG_OPCODE_ATOMIC); 1245 if (opcode [all...] |
/gem5/src/gpu-compute/ |
H A D | gpu_static_inst.cc | 38 GPUStaticInst::GPUStaticInst(const std::string &opcode) argument 39 : executed_as(Enums::SC_NONE), opcode(opcode),
|
H A D | gpu_static_inst.hh | 63 GPUStaticInst(const std::string &opcode); 249 const std::string opcode; member in class:GPUStaticInst 282 disassembly = opcode;
|
H A D | hsail_code.cc | 184 inst_idx, instPtr->opcode);
|
/gem5/src/arch/x86/ |
H A D | decoder.cc | 54 emi.opcode.type = BadOpcode; 55 emi.opcode.op = 0; 176 //state machine on to get the opcode(s). 269 emi.opcode.type = TwoByteOpcode; 280 emi.opcode.type = OneByteOpcode; 281 emi.opcode.op = 0xC4; 295 emi.opcode.type = TwoByteOpcode; 298 emi.opcode.type = ThreeByte0F38Opcode; 301 emi.opcode.type = ThreeByte0F3AOpcode; 307 emi.opcode 454 const uint8_t opcode = emi.opcode.op; local [all...] |
H A D | types.cc | 48 paramOut(cp, name + ".opcode.type", (uint8_t)machInst.opcode.type); 49 paramOut(cp, name + ".opcode.op", (uint8_t)machInst.opcode.op); 85 paramIn(cp, name + ".opcode.type", temp8); 86 machInst.opcode.type = (OpcodeType)temp8; 87 paramIn(cp, name + ".opcode.op", temp8); 88 machInst.opcode.op = temp8;
|
H A D | types.hh | 114 // Selector for what would be two or three byte opcode types. 125 // Implied 66, F2, or F3 opcode prefix. 136 // Implied 66, F2, or F3 opcode prefix. 211 //This holds all of the bytes of the opcode 215 //The main opcode byte. The highest addressed byte in the opcode. 217 } opcode; member in struct:X86ISA::ExtMachInst 249 opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op, 264 if (emi1.opcode [all...] |
/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
H A D | cycle_model.cpp | 217 //void cycle_model::decode(int opcode, instr* i) 219 // take an opcode as an input and output the instruction with the 223 void cycle_model::decode(int opcode, instr* i) { argument 235 switch(opcode) { 249 i->src1.val = opcode&0x07; 271 i->src1.val = opcode&1; 299 i->src1.val = opcode&0x07; 321 i->src1.val = opcode&1; 358 i->src1.val = opcode&0x07; 360 i->dst.val = opcode 1284 int opcode = instr_mem[ad]; local 1752 int opcode = fetch_instr(my_stack->address); local [all...] |
H A D | cycle_model.h | 104 int val; /* value encoded with the opcode (i.e. register number) */ 153 void decode(int opcode, instr* i);
|
/gem5/src/mem/slicc/ast/ |
H A D | OperatorExprAST.py | 108 opcode = self.slicc.codeFormatter() 109 optype = self.operand.generate(opcode) 126 code("(${{self.op}} $opcode)")
|
/gem5/src/systemc/tests/systemc/misc/sim_tests/simple_cpu/ |
H A D | simple_cpu.cpp | 97 unsigned opcode; local 104 opcode = (instr & 0xe0000000) >> 29; // Extract opcode 105 switch(opcode) { 180 default: // Bad opcode 181 printf("Bad opcode 0x%x\n", opcode);
|
/gem5/src/arch/arm/tracers/ |
H A D | tarmac_base.hh | 94 ArmISA::MachInst opcode; member in struct:Trace::TarmacBaseRecord::InstEntry
|
H A D | tarmac_base.cc | 69 opcode(staticInst->machInst & 0xffffffff),
|
H A D | tarmac_record.cc | 133 // Mask the opcode using the instruction size: the 134 // opcode field will otherwise be 32 bit wide even 136 opcode = arm_inst->encoding(); 408 // Pad the opcode 409 std::string opcode_str = csprintf("%0*x", instSize >> 2, opcode); 418 opcode_str, /* Instruction opcode */
|
H A D | tarmac_record_v8.cc | 192 // Pad the opcode. 193 std::string opcode_str = csprintf("%0*x", instSize >> 2, opcode); 204 opcode_str, /* Instruction opcode */
|
H A D | tarmac_parser.cc | 731 "on PC or opcode", 1); 752 << ", opcode: 0x" << hex << (staticInst->machInst & 0xffffffff) 812 if (arm_inst->encoding() != instRecord.opcode) { 815 outs << "diff> [opcode] gem5: 0x" << hex 817 << ", TARMAC: 0x" << instRecord.opcode << endl; 874 "on PC or opcode", 1); 915 trace >> instRecord.opcode;
|
/gem5/src/arch/hsail/ |
H A D | gen.py | 88 switch(ib->opcode) { 116 : Base(ib, obj, "$opcode") 133 : Base(ib, obj, "$opcode") 153 : Base(ib, obj, "$opcode") 171 : Base(ib, obj, "$opcode") 192 : Base(ib, obj, "$opcode") 214 : Base(ib, obj, "$opcode") 471 # decode template for nodt-opcode case 493 # common prolog for 1dt- or 2dt-opcode case: switch on data type 570 opcode [all...] |
H A D | Brig_new.hpp | 564 //.opcodevis_arg="inst.opcode()" //.opcodevis_default="return RetType()" 1320 BrigOpcode16_t opcode; member in struct:BrigInstBase
|
/gem5/src/arch/arm/ |
H A D | types.hh | 99 // All the different types of opcode fields. 102 Bitfield<24, 21> opcode; member in namespace:ArmISA
|