History log of /gem5/src/arch/hsail/insts/decl.hh
Revision Date Author Comments
# 12032:d218c2fe9440 18-May-2017 Andreas Sandberg <andreas.sandberg@arm.com>

base, sim, arch: Fix clang 5.0 warnings

Compiling gem5 with recent version of clang (4 and 5) triggers
warnings that are treated as errors:

* Global templatized static functions result in a warning if they
are not used. These should either be declared as static inline or
without the static identifier to avoid the warning.

* Some templatized classes contain static variables. The
instantiated versions of these variables / templates need to be
explicitly declared to avoid a compiler warning.

Change-Id: Ie8261144836e94ebab7ea04ccccb90927672c257
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3420
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>


# 11738:ad7e8afa0dfe 02-Dec-2016 Brandon Potter <brandon.potter@amd.com>

hsail: add stub type and stub out several instructions


# 11737:50eceddc2286 02-Dec-2016 Brandon Potter <brandon.potter@amd.com>

hsail: add popcount type and generate popcount instructions


# 11700:7d4d424c9f17 26-Oct-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: support in-order data delivery in GM pipe

this patch adds an ordered response buffer to the GM pipeline
to ensure in-order data delivery. the buffer is implemented as
a stl ordered map, which sorts the request in program order by
using their sequence ID. when requests return to the GM pipeline
they are marked as done. only the oldest request may be serviced
from the ordered buffer, and only if is marked as done.

the FIFO response buffers are kept and used in OoO delivery mode


# 11699:c7453f485a5f 26-Oct-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()

for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file, or are
an immediate.

for machine ISA, however, an op selector may specify special registers, or
may specify special SGPRs with an alias op selector value. the location of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the relative
positions of the special register values.


# 11692:e772fdcd3809 26-Oct-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: remove inst enums and use bit flag for attributes

this patch removes the GPUStaticInst enums that were defined in GPU.py.
instead, a simple set of attribute flags that can be set in the base
instruction class are used. this will help unify the attributes of HSAIL
and machine ISA instructions within the model itself.

because the static instrution now carries the attributes, a GPUDynInst
must carry a pointer to a valid GPUStaticInst so a new static kernel launch
instruction is added, which carries the attributes needed to perform a
the kernel launch.


# 11639:2e8d4bd8108d 16-Sep-2016 Alexandru Dutu <alexandru.dutu@amd.com>

gpu-compute: Wavefront refactoring
Renaming members of the Wavefront class in accordance with the style guide.


# 11325:67cc559d513a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate explicit boolean comparisons

Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.

Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<


# 11308:7d8836fd043d 19-Jan-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: AMD's baseline GPU model