| /gem5/configs/common/cores/arm/ |
| H A D | ex5_LITTLE.py | 43 opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
47 opList = [ OpDesc(opClass='IntMult', opLat=7) ]
50 opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
54 opList = [ OpDesc(opClass='SimdAdd', opLat=6),
55 OpDesc(opClass='SimdAddAcc', opLat=4),
56 OpDesc(opClass='SimdAlu', opLat=4),
57 OpDesc(opClass='SimdCmp', opLat=1),
58 OpDesc(opClass='SimdCvt', opLat=3),
59 OpDesc(opClass='SimdMisc', opLat=3),
60 OpDesc(opClass='SimdMult',opLat
[all...] |
| H A D | O3_ARM_v7a.py | 36 opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
41 opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
42 OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
43 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
49 opList = [ OpDesc(opClass='SimdAdd', opLat=4),
50 OpDesc(opClass='SimdAddAcc', opLat=4),
51 OpDesc(opClass='SimdAlu', opLat=4),
52 OpDesc(opClass='SimdCmp', opLat=4),
53 OpDesc(opClass='SimdCvt', opLat=3),
54 OpDesc(opClass='SimdMisc', opLat
[all...] |
| H A D | ex5_big.py | 43 opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
48 opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True),
49 OpDesc(opClass='IntDiv', opLat=11, pipelined=False),
50 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
55 opList = [ OpDesc(opClass='SimdAdd', opLat=3),
56 OpDesc(opClass='SimdAddAcc', opLat=4),
57 OpDesc(opClass='SimdAlu', opLat=4),
58 OpDesc(opClass='SimdCmp', opLat=4),
59 OpDesc(opClass='SimdCvt', opLat=3),
60 OpDesc(opClass='SimdMisc', opLat
[all...] |
| H A D | HPI.py | 1166 opLat = 6 variable in class:HPI_FloatSimdFU
1223 opLat = 3 variable in class:HPI_IntFU
1287 opLat = 3 variable in class:HPI_Int2FU
1306 opLat = 3 variable in class:HPI_IntMulFU
1314 opLat = 3 variable in class:HPI_IntDivFU
1320 opLat = 1 variable in class:HPI_MemFU
1325 opLat = 1 variable in class:HPI_MiscFU
|
| /gem5/src/cpu/o3/ |
| H A D | FuncUnitConfig.py | 52 opList = [ OpDesc(opClass='IntMult', opLat=3),
53 OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ]
60 opList[1].opLat=1
65 opList = [ OpDesc(opClass='FloatAdd', opLat=2),
66 OpDesc(opClass='FloatCmp', opLat=2),
67 OpDesc(opClass='FloatCvt', opLat=2) ]
71 opList = [ OpDesc(opClass='FloatMult', opLat=4),
72 OpDesc(opClass='FloatMultAcc', opLat=5),
73 OpDesc(opClass='FloatMisc', opLat=3),
74 OpDesc(opClass='FloatDiv', opLat
[all...] |
| H A D | fu_pool.cc | 125 fu->addCapability((*j)->opClass, (*j)->opLat, (*j)->pipelined);
127 if ((*j)->opLat > maxOpLatencies[(*j)->opClass])
128 maxOpLatencies[(*j)->opClass] = (*j)->opLat;
|
| /gem5/src/cpu/ |
| H A D | FuncUnit.py | 66 opLat = Param.Cycles(1, "cycles until result is available") variable in class:OpDesc
|
| H A D | func_unit.hh | 55 Cycles opLat; member in class:OpDesc
59 : SimObject(p), opClass(p->opClass), opLat(p->opLat),
|
| /gem5/src/cpu/minor/ |
| H A D | MinorCPU.py | 113 opLat = Param.Cycles(1, "latency in cycles") variable in class:MinorFU
132 opLat = 3 variable in class:MinorDefaultIntFU
138 opLat = 3 variable in class:MinorDefaultIntMulFU
143 opLat = 9 variable in class:MinorDefaultIntDivFU
161 opLat = 6 variable in class:MinorDefaultFloatSimdFU
167 opLat = 3 variable in class:MinorDefaultPredFU
174 opLat = 1 variable in class:MinorDefaultMemFU
178 opLat = 1 variable in class:MinorDefaultMiscFU
|
| H A D | func_unit.hh | 156 Cycles opLat; member in class:MinorFU
173 opLat(params->opLat),
|
| H A D | func_unit.cc | 115 FUPipelineBase(name, "insts", description_.opLat),
125 addCapability(No_OpClass, description.opLat, 1);
132 description.opLat, 1);
|
| H A D | execute.cc | 139 total_slots += fu_description->opLat;
756 fu->description.opLat +
|