Searched refs:misses (Results 1 - 16 of 16) sorted by relevance

/gem5/src/mem/cache/tags/
H A Dfa_lru.cc405 misses[i]++;
413 misses[numTrackedCaches]++;
439 misses
442 .desc("The number of misses in each cache size.")
454 misses.subname(i, size_str.str());
455 misses.subdesc(i, "Misses in a " + size_str.str() + " cache");
H A Dfa_lru.hh377 * statistics track the hits and misses for different cache sizes.
384 Stats::Vector misses; member in class:FALRU::CacheTracking
/gem5/src/mem/ruby/profiler/
H A DAddressProfiler.cc71 uint64_t misses = 0; local
78 misses += record->getTotal();
86 out << "Total_Instructions_" << description << ": " << misses << endl;
88 out << "Total_data_misses_" << description << ": " << misses << endl;
112 double percent = 100.0 * (record->getTotal() / double(misses));
/gem5/src/arch/mips/
H A Dtlb.hh79 Stats::Formula misses; member in class:MipsISA::TLB
H A Dtlb.cc239 .desc("DTB read misses")
255 .desc("DTB write misses")
269 misses
270 .name(name() + ".misses")
271 .desc("DTB misses")
280 misses = read_misses + write_misses;
/gem5/src/arch/riscv/
H A Dtlb.hh78 Stats::Formula misses; member in class:RiscvISA::TLB
H A Dtlb.cc241 .desc("DTB read misses")
257 .desc("DTB write misses")
271 misses
272 .name(name() + ".misses")
273 .desc("DTB misses")
282 misses = read_misses + write_misses;
/gem5/src/learning_gem5/part2/
H A Dsimple_cache.hh298 Stats::Scalar misses; member in class:SimpleCache
H A Dsimple_cache.cc296 misses++; // update stats
436 misses.name(name() + ".misses")
437 .desc("Number of misses")
441 .desc("Ticks for misses to the cache")
449 hitRatio = hits / (hits + misses);
/gem5/src/arch/power/
H A Dtlb.hh128 Stats::Formula misses; member in class:PowerISA::TLB
H A Dtlb.cc236 .desc("DTB read misses")
252 .desc("DTB write misses")
266 misses
267 .name(name() + ".misses")
268 .desc("DTB misses")
277 misses = read_misses + write_misses;
/gem5/util/stats/
H A Dstats.py243 all = [ 'bps', 'misses', 'mpkb', 'ipkb', 'pps', 'bpt' ]
372 misses = system.l2.overall_mshr_misses
374 if command == 'misses':
375 output.stat = misses
381 output.stat = misses / (bytes / 1024)
/gem5/src/mem/cache/
H A Dbase.hh903 /** The number of misses to trigger an exit event. */
929 /** Number of misses per thread for each type of command.
931 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; member in class:BaseCache
932 /** Number of misses for demand accesses. */
934 /** Number of misses for all accesses. */
942 /** Total number of cycles spent waiting for demand misses. */
944 /** Total number of cycles spent waiting for all misses. */
963 /** The average miss latency for demand misses. */
965 /** The average miss latency for all misses. */
982 /** Number of misses tha
[all...]
H A Dbase.cc736 // Service misses in order until conflict is cleared.
1218 // a writeback that misses needs to allocate a new block
1935 misses[access_idx]
1938 .desc("number of " + cstr + " misses")
1942 misses[access_idx].subname(i, system->getMasterName(i));
1948 .desc("number of demand (read+write) misses")
1951 demandMisses = SUM_DEMAND(misses);
1958 .desc("number of overall misses")
1961 overallMisses = demandMisses + SUM_NON_DEMAND(misses);
2009 .desc("number of " + cstr + " accesses(hits+misses)")
[all...]
/gem5/src/arch/arm/
H A Dtlb.hh191 Stats::Formula misses; member in class:ArmISA::TLB
H A Dtlb.cc452 .desc("ITB inst misses")
467 .desc("DTB read misses")
482 .desc("DTB write misses")
495 misses
496 .name(name() + ".misses")
497 .desc("DTB misses")
554 misses = readMisses + writeMisses + instMisses;

Completed in 52 milliseconds