| /gem5/src/mem/cache/tags/ |
| H A D | super_blk.cc | 83 CompressionBlk::setDecompressionLatency(const Cycles lat) argument
85 _decompressionLatency = lat;
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| H A D | super_blk.hh | 113 void setDecompressionLatency(const Cycles lat);
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| H A D | base_set_assoc.hh | 124 * @param lat The latency of the tag lookup.
127 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override
153 lat = lookupLatency;
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| H A D | sector_tags.hh | 126 * @param lat The latency of the tag lookup.
129 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override;
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| H A D | fa_lru.hh | 186 * @param lat The latency of the tag lookup.
190 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
196 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override;
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| H A D | fa_lru.cc | 141 FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat) argument
143 return accessBlock(addr, is_secure, lat, 0);
147 FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, argument
167 lat = lookupLatency;
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| H A D | base.hh | 296 * @param lat The latency of the tag lookup.
299 virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0;
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| H A D | sector_tags.cc | 136 SectorTags::accessBlock(Addr addr, bool is_secure, Cycles &lat)
167 lat = lookupLatency;
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| /gem5/ext/mcpat/cacti/ |
| H A D | nuca.h | 83 int calc_cycles(double lat, double oper_freq);
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| H A D | nuca.cc | 106 Nuca::calc_cycles(double lat, double oper_freq) { argument
112 return (int)ceil(lat / cycle_time);
322 /* avg access lat of nuca */
510 printf("NUCA___stats %d \tbankcount: lat = %g \tdynP = %g \twt = %d\t "
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| /gem5/src/mem/cache/compressors/ |
| H A D | base.hh | 141 * @param lat The decompression latency.
143 static void setDecompressionLatency(CacheBlk* blk, const Cycles lat);
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| H A D | base.cc | 131 BaseCacheCompressor::setDecompressionLatency(CacheBlk* blk, const Cycles lat) argument
137 static_cast<CompressionBlk*>(blk)->setDecompressionLatency(lat);
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| /gem5/ext/sst/tests/ |
| H A D | test6_arm_4c.py | 42 lat="1 ns" variable
114 link.connect((m5, connector, lat), (cache, "high_network_0", lat))
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| /gem5/src/mem/cache/ |
| H A D | noncoherent_cache.hh | 74 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
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| H A D | cache.hh | 90 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
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| H A D | base.cc | 224 // lat, neglecting responseLatency, modelling hit latency
225 // just as the value of lat overriden by access(), which calls
342 Cycles lat; local
347 // Note that lat is passed by reference here. The function
348 // access() will set the lat value.
349 satisfied = access(pkt, blk, lat, writebacks);
354 doWritebacks(writebacks, clockEdge(lat + forwardLatency));
362 Tick request_time = clockEdge(lat);
552 Cycles lat = lookupLatency; local
556 bool satisfied = access(pkt, blk, lat, writeback
1024 access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks) argument
[all...] |
| H A D | noncoherent_cache.cc | 83 NoncoherentCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, argument
86 bool success = BaseCache::access(pkt, blk, lat, writebacks);
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| H A D | cache.cc | 164 Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, argument
185 lat = lookupLatency;
189 return BaseCache::access(pkt, blk, lat, writebacks);
393 // request_time is used here, taking into account lat and the delay
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| H A D | base.hh | 454 * @param lat The latency of the access.
458 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
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| /gem5/src/dev/ |
| H A D | dma_device.cc | 273 Tick lat = sendAtomic(pkt); local
275 handleResp(pkt, lat);
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