Searched refs:emi (Results 1 - 11 of 11) sorted by relevance

/gem5/src/arch/riscv/
H A Ddecoder.cc48 emi = 0;
60 emi = inst;
61 if (compressed(emi))
62 emi &= LowerBitMask;
63 more = !compressed(emi);
67 assert((emi & UpperBitMask) == 0);
68 emi |= (inst & LowerBitMask) << sizeof(MachInst)*4;
73 emi = (inst & UpperBitMask) >> sizeof(MachInst)*4;
74 mid = !compressed(emi);
76 instDone = compressed(emi);
[all...]
H A Ddecoder.hh58 ExtMachInst emi; member in class:RiscvISA::Decoder
/gem5/src/arch/arm/
H A Ddecoder.cc72 emi = 0;
81 // emi is typically ready, with some caveats below...
84 if (!emi.thumb) {
85 emi.instBits = data;
86 if (!emi.aarch64) {
87 emi.sevenAndFour = bits(data, 7) && bits(data, 4);
88 emi.isMisc = (bits(data, 24, 23) == 0x2 &&
92 DPRINTF(Decoder, "Arm inst: %#x.\n", (uint64_t)emi);
97 emi.instBits = emi
[all...]
H A Ddecoder.hh63 ExtMachInst emi; member in class:ArmISA::Decoder
/gem5/src/arch/x86/
H A Ddecoder.cc50 emi.rex = 0;
51 emi.legacy = 0;
52 emi.vex = 0;
54 emi.opcode.type = BadOpcode;
55 emi.opcode.op = 0;
58 emi.immediate = 0;
59 emi.displacement = 0;
60 emi.dispSize = 0;
62 emi.modRM = 0;
63 emi
[all...]
H A Dtypes.hh239 operator << (std::ostream & os, const ExtMachInst & emi) argument
247 (uint8_t)emi.legacy, (uint8_t)emi.rex,
248 (uint8_t)emi.vex,
249 opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op,
250 (uint8_t)emi.modRM, (uint8_t)emi.sib,
251 emi.immediate, emi
[all...]
H A Ddecoder.hh96 ExtMachInst emi; member in class:X86ISA::Decoder
242 emi.reset();
245 emi.mode.mode = mode;
246 emi.mode.submode = submode;
261 emi.mode.mode = mode;
262 emi.mode.submode = submode;
290 emi.mode.mode = mode;
291 emi.mode.submode = submode;
/gem5/src/arch/sparc/
H A Ddecoder.hh47 ExtMachInst emi; member in class:SparcISA::Decoder
68 emi = inst;
74 emi |= (static_cast<ExtMachInst>(
77 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
125 return decode(emi, nextPC.instAddr());
/gem5/src/arch/power/
H A Ddecoder.hh46 ExtMachInst emi; member in class:PowerISA::Decoder
70 emi = inst;
118 return decode(emi, nextPC.instAddr());
H A Dtypes.hh95 size_t operator()(const PowerISA::ExtMachInst &emi) const {
96 return hash<uint32_t>::operator()((uint32_t)emi);
/gem5/src/arch/mips/
H A Ddecoder.hh48 ExtMachInst emi; member in class:MipsISA::Decoder
71 emi = inst;
111 return decode(emi, nextPC.instAddr());

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