/gem5/ext/nomali/lib/ |
H A D | mmu.cc | 48 for (auto &as : spaces) 49 as.reset(); 75 AddrSpace &as(spaces[getAddrSpaceNo(addr)]); 76 as.writeReg(getAddrSpaceAddr(addr), value);
|
/gem5/util/m5/ |
H A D | Makefile.alpha | 35 AS=$(CROSS_COMPILE)as
|
H A D | Makefile.sparc | 35 AS=$(CROSS_COMPILE)as
|
H A D | Makefile.thumb | 5 # not be construed as granting a license to any other intellectual 48 AS=$(CROSS_COMPILE)as
|
H A D | Makefile.x86 | 31 AS=as
|
H A D | Makefile.arm | 5 # not be construed as granting a license to any other intellectual 47 AS=$(CROSS_COMPILE)as
|
H A D | Makefile.aarch64 | 5 # not be construed as granting a license to any other intellectual 47 AS=$(CROSS_COMPILE)as
|
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | csr.S | 94 # Don't run in supervisor, as we don't delegate illegal instruction traps. 100 # Don't run in supervisor, as we don't delegate illegal instruction traps.
|
/gem5/system/alpha/console/ |
H A D | Makefile | 38 AS=$(CROSS_COMPILE)as
|
H A D | dbmentry.S | 50 Processor 0, then they can progress as normal. 56 # This must be changed as well!
|
/gem5/src/arch/generic/ |
H A D | vec_reg.hh | 6 * not be construed as granting a license to any other intellectual 52 * constant, it is defined as a template parameter. 59 * calculated as sizeof(VecElem) * NumElems must match the size of the 62 * references to particular bytes understood as a VecElem. 72 * member 'as' for VecRegT and the member 'laneView' for VecLaneT. Kindly 84 * // Request source vector register to the execution context (const as it 87 * // View it as a vector of floats (we could just specify the first 90 * VecRegT<float, 8, true>& vsrc1 = vsrc1raw->as<float, 8>(); 94 * VecRegT<float, 8, true>& vsrc2 = vsrc2raw->as<float, 8>(); 98 * VecRegT<float, 8, false>& vdst = vdstraw->as<floa 384 VecRegT<VecElem, NumElems, true> as() const function in class:VecRegContainer 394 VecRegT<VecElem, NumElems, false> as() function in class:VecRegContainer [all...] |
H A D | vec_pred_reg.hh | 5 // not be construed as granting a license to any other intellectual 124 /// Return an element of the predicate register as it appears 355 VecPredRegT<VecElem, NumElems, Packed, true> as() const function in class:VecPredRegContainer 367 VecPredRegT<VecElem, NumElems, Packed, false> as() function in class:VecPredRegContainer
|
/gem5/src/cpu/ |
H A D | exetrace.cc | 6 * not be construed as granting a license to any other intellectual 137 auto dv = data.as_vec->as<uint32_t>(); 151 auto pv = data.as_pred->as<uint8_t>();
|
H A D | simple_thread.hh | 7 * not be construed as granting a license to any other intellectual 290 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 301 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 312 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 323 DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 338 DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 413 DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 424 DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 436 "Reading predicate reg %d (%d) as %s for modify.\n", 449 DPRINTF(CCRegs, "Reading CC reg %d (%d) as [all...] |
/gem5/system/alpha/palcode/ |
H A D | Makefile | 9 # so long as the copyright notice above, this grant of permission, and 10 # the disclaimer below appear in all copies made; and so long as the 37 AS=$(CROSS_COMPILE)as
|
/gem5/src/cpu/o3/ |
H A D | regfile.hh | 6 * not be construed as granting a license to any other intellectual 201 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 263 auto ret = vectorRegFile[phys_reg->index()].as<VecElem>(); 349 vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
|
H A D | rename_map.cc | 6 * not be construed as granting a license to any other intellectual 203 * 3.- Set the remaining registers as free 207 VecReg dst = new_RF[i].as<TheISA::VecElem>();
|
/gem5/src/arch/arm/ |
H A D | remote_gdb.cc | 8 * not be construed as granting a license to any other intellectual 214 auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>(); 243 RegId(VecRegClass, i))).as<VecElem>();
|
H A D | nativetrace.cc | 6 * not be construed as granting a license to any other intellectual 130 .as<uint64_t, MaxSveVecLenInDWords>());
|
H A D | miscregs_types.hh | 6 * not be construed as granting a license to any other intellectual 338 Bitfield<18> rao2; // Read as one 341 Bitfield<16> rao3; // Read as one 358 Bitfield<6, 3> rao4; // Read as one 481 Bitfield<36> as; member in namespace:ArmISA 513 Bitfield<36> as; // EL1 member in namespace:ArmISA
|
/gem5/ext/systemc/src/sysc/qt/md/ |
H A D | ksr1.s | 8 * appear in all copies. This software is provided as a 41 # Note, by the way, that a pointer to a function is passed as a 154 # Switch to the stack passed in as fourth argument to the block 155 # routine (%i5) and call the helper routine passed in as the first 254 # the new stack is passed in as an argument, we don't load the EFP 333 # A new thread is set up to "appear" as if it were executing code at 382 finop ; ld8 8(%sp),%i2 # load `t' as arg to 398 finop ; ld8 8(%sp),%i2 # load `t' as arg to 399 finop ; ld8 8(%sp),%i2 # load `t' as arg to 400 finop ; ld8 8(%sp),%i2 # load `t' as ar [all...] |
H A D | hppa.s | 9 ; appear in all copies. This software is provided as a 69 copy %sp,%arg0 ; pass current sp as arg0 to helper
|
H A D | hppa_b.s | 7 ; appear in all copies. This software is provided as a
|
/gem5/src/systemc/dt/int/ |
H A D | sc_nbcommon.inc | 26 as sc_signed before including this file. This file like 2271 // Create a signed number with (s, nb, nd, d) as its attributes (as 2380 // will be used as a temporary store. The following code tries to 2519 // will be used as a temporary store. The following code tries to
|
/gem5/util/ |
H A D | compile | 31 from os.path import isdir, isfile, join as joinpath
|