/gem5/src/systemc/tests/systemc/kernel/kind_string/test01/ |
H A D | main.cpp | 44 #define WRITE(a) \ macro 67 WRITE( *sc_get_current_process_handle().get_process_object() ); 69 WRITE( *sc_get_current_process_handle().get_process_object() ); 71 WRITE( *sc_get_current_process_handle().get_process_object() ); 81 WRITE( a ); 84 WRITE( clk ); 87 WRITE( fifo ); 90 WRITE( mutex ); 93 WRITE( signal ); 96 WRITE( signal_boo [all...] |
/gem5/src/systemc/tests/systemc/datatypes/fx/copy_ctors/ |
H A D | copy_ctors.cpp | 43 #define WRITE(a) \ macro 59 WRITE( fxd ); 60 WRITE( fxdf ); 61 WRITE( ufxd ); 62 WRITE( ufxdf ); 64 WRITE( fx ); 65 WRITE( fxf ); 66 WRITE( ufx ); 67 WRITE( ufxf ); 80 WRITE( fx0 [all...] |
/gem5/src/systemc/tests/systemc/communication/sc_signal_resolved_port/test01/ |
H A D | test01.cpp | 44 #define WRITE(a) \ macro 75 WRITE(in_1); 76 WRITE(in_2); 77 WRITE(in_3); 78 WRITE(in_4); 79 WRITE(in_5); 80 WRITE(in_6); 81 WRITE(in_out1); 82 WRITE(in_out2); 83 WRITE(in_out [all...] |
/gem5/src/systemc/tests/systemc/communication/ports/test01/ |
H A D | test01.cpp | 85 #define WRITE(a) \ macro 93 WRITE( a.in_clk ); 94 WRITE( a.inout_clk ); 95 WRITE( a.out_clk ); 97 WRITE( a.fifo_in ); 98 WRITE( a.fifo_out ); 100 WRITE( a.port ); 102 WRITE( a.in_int ); 103 WRITE( a.in_bool ); 104 WRITE( [all...] |
/gem5/src/systemc/tests/systemc/datatypes/int/concat/test03/ |
H A D | test03.cpp | 42 #define WRITE(a) \ macro 60 WRITE( ui4 ); 62 WRITE( ui4 ); 66 WRITE( ui4 ); 68 WRITE( ui4 ); 76 WRITE( ui2 ); 78 WRITE( ui2 ); 82 WRITE( ui2 ); 84 WRITE( ui2 ); 92 WRITE( ui [all...] |
/gem5/src/systemc/tests/systemc/datatypes/int/concat/test06/ |
H A D | test06.cpp | 42 #define WRITE(a) \ macro 60 WRITE( ui4 ); 62 WRITE( ui4 ); 66 WRITE( ui4 ); 68 WRITE( ui4 ); 76 WRITE( ui2 ); 78 WRITE( ui2 ); 82 WRITE( ui2 ); 84 WRITE( ui2 ); 92 WRITE( ui [all...] |
/gem5/src/systemc/tests/systemc/datatypes/bit/sc_proxy/test01/ |
H A D | test01.cpp | 40 #define WRITE(a) \ macro 52 WRITE( a ); 58 WRITE( a ); 64 WRITE( a ); 70 WRITE( a ); 76 WRITE( a ); 78 WRITE( b ); 80 WRITE( c ); 82 WRITE( d ); 88 WRITE( a [all...] |
/gem5/src/systemc/tests/systemc/communication/ports/test03/ |
H A D | test03.cpp | 97 #define WRITE(a) \ macro 104 WRITE(c.sig1); 105 WRITE(c.sig2); 106 WRITE(c.sig3); 107 WRITE(c.sig4); 108 WRITE(c.in1); 109 WRITE(c.in2); 110 WRITE(c.in3); 111 WRITE(c.in4); 112 WRITE( [all...] |
/gem5/src/systemc/tests/systemc/communication/ports/test04/ |
H A D | test04.cpp | 44 #define WRITE(a) \ macro 57 WRITE(in_1); 58 WRITE(in_2); 59 WRITE(inout_1); 60 WRITE(inout_2); 73 WRITE(in_1); 74 WRITE(in_2); 75 WRITE(inout_1); 76 WRITE(inout_2); 119 WRITE(input_ [all...] |
/gem5/src/mem/qos/ |
H A D | turnaround_policy_ideal.cc | 77 bus_state = MemCtrl::WRITE; 83 MemCtrl::WRITE : MemCtrl::READ); 92 (bus_state == MemCtrl::READ)? "READ" : "WRITE");
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H A D | mem_ctrl.cc | 105 } else if (dir == WRITE) { 161 } else if (dir == WRITE) { 258 (!getTotalWriteQueueSize() && bus_state == MemCtrl::WRITE)) { 259 // READ/WRITE turnaround 260 bus_state = (bus_state == MemCtrl::READ) ? MemCtrl::WRITE : 311 .desc("Number of turnarounds from READ to WRITE"); 314 .desc("Number of turnarounds from WRITE to READ"); 320 .desc("Number of times bus staying in WRITE state"); 340 } else if (busState == WRITE) { 346 } else if (busState == WRITE) { [all...] |
H A D | mem_sink.cc | 180 logRequest(pkt->isRead()? READ : WRITE, 218 (busState == WRITE ? "WRITE" : "READ")); 223 for (auto& e : (busState == WRITE ? writeQueue[i]: readQueue[i])) { 229 busState == WRITE ? writeQueueSizes[i] : 244 __func__, (busState == READ? "READ" : "WRITE"), 285 logResponse(pkt->isRead()? READ : WRITE, 302 } else if (busState == WRITE && retryWrReq) {
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H A D | mem_ctrl.hh | 65 enum BusState { READ, WRITE }; enumerator in enum:QoS::MemCtrl::BusState 71 /** QoS Bus Turnaround Policy: selects the bus direction (READ/WRITE) */ 135 /** Count the number of turnarounds READ to WRITE */ 137 /** Count the number of turnarounds WRITE to READ */ 141 /** Count the number of times bus staying in WRITE state */ 200 * Returns next bus direction (READ or WRITE) 206 * Set current bus direction (READ or WRITE) 305 * Gets a WRITE queue size 321 * Gets the total combined WRITE queues size 388 "QoSMemCtrl::escalate master %s negative WRITE " [all...] |
/gem5/src/gpu-compute/ |
H A D | vector_register_file.hh | 59 WRITE = 0x02, member in class:VrfAccessType 60 RD_WR = READ | WRITE
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H A D | local_memory_pipeline.cc | 73 VrfAccessType::WRITE);
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H A D | global_memory_pipeline.cc | 78 vrfOperandAccessReady(m->seqNum(), w, m, VrfAccessType::WRITE);
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/gem5/ext/drampower/src/ |
H A D | CmdScheduler.h | 53 #define WRITE 1 macro 99 commandItem PreRDWR; // the latest scheduled READ or WRITE command. 104 // the scheduled READ or WRITE commands are stored in RDWR.
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H A D | CmdScheduler.cc | 119 cmd.Type = WRITE; 120 cmd.name = "WRITE"; 162 if (item == "write" || item == "WRITE") { 163 transType = WRITE; 359 case WRITE: 382 case WRITE: 529 } else if (transType == WRITE) { 563 if ((PreType == WRITE) && (CurrentType == READ)) { 593 } else if (PreType == WRITE && CurrentType == READ) { 599 if ((PreType == READ) && (CurrentType == WRITE)) { [all...] |
/gem5/src/systemc/tests/systemc/misc/sim_tests/simple_cpu/ |
H A D | simple_cpu.cpp | 41 #define WRITE 1 macro
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/gem5/src/dev/virtio/ |
H A D | fs9p.cc | 108 P9MSG(118, WRITE),
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/gem5/src/mem/ |
H A D | dram_ctrl.hh | 494 ((memory.busStateNext == WRITE) && (writeEntries != 0));
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H A D | dram_ctrl.cc | 553 logRequest(MemCtrl::WRITE, pkt->masterId(), pkt->qosValue(), 606 DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 1346 (busState==MemCtrl::READ)?"READ":"WRITE", 1523 busStateNext = WRITE; 1537 "DRAM controller checking WRITE queue [%d] priority [%d elements]\n", 1592 logResponse(MemCtrl::WRITE, dram_pkt->masterId(), 1787 || ((memory.busStateNext == WRITE) &&
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