110428Sandreas.hansson@arm.com/* 210428Sandreas.hansson@arm.com * Copyright (c) 2012-2014, TU Delft 310428Sandreas.hansson@arm.com * Copyright (c) 2012-2014, TU Eindhoven 410428Sandreas.hansson@arm.com * Copyright (c) 2012-2014, TU Kaiserslautern 510428Sandreas.hansson@arm.com * All rights reserved. 610428Sandreas.hansson@arm.com * 710428Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 810428Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 910428Sandreas.hansson@arm.com * met: 1010428Sandreas.hansson@arm.com * 1110428Sandreas.hansson@arm.com * 1. Redistributions of source code must retain the above copyright 1210428Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer. 1310428Sandreas.hansson@arm.com * 1410428Sandreas.hansson@arm.com * 2. Redistributions in binary form must reproduce the above copyright 1510428Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1610428Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution. 1710428Sandreas.hansson@arm.com * 1810428Sandreas.hansson@arm.com * 3. Neither the name of the copyright holder nor the names of its 1910428Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 2010428Sandreas.hansson@arm.com * this software without specific prior written permission. 2110428Sandreas.hansson@arm.com * 2210428Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 2310428Sandreas.hansson@arm.com * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2410428Sandreas.hansson@arm.com * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 2510428Sandreas.hansson@arm.com * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2610428Sandreas.hansson@arm.com * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2710428Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 2810428Sandreas.hansson@arm.com * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 2910428Sandreas.hansson@arm.com * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 3010428Sandreas.hansson@arm.com * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 3110428Sandreas.hansson@arm.com * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 3210428Sandreas.hansson@arm.com * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3310428Sandreas.hansson@arm.com * 3410428Sandreas.hansson@arm.com * Authors: Karthik Chandrasekar 3510428Sandreas.hansson@arm.com * 3610428Sandreas.hansson@arm.com */ 3710428Sandreas.hansson@arm.com 3810428Sandreas.hansson@arm.com#ifndef CMDSCHEDULER_H 3910428Sandreas.hansson@arm.com#define CMDSCHEDULER_H 4010428Sandreas.hansson@arm.com 4110428Sandreas.hansson@arm.com#include <string> 4210428Sandreas.hansson@arm.com#include <vector> 4310428Sandreas.hansson@arm.com#include <functional> // for binary_function<> 4410428Sandreas.hansson@arm.com#include <fstream> 4510428Sandreas.hansson@arm.com 4610428Sandreas.hansson@arm.com#include "MemorySpecification.h" 4710428Sandreas.hansson@arm.com#include "Utils.h" 4810428Sandreas.hansson@arm.com 4910428Sandreas.hansson@arm.comnamespace Data { 5010428Sandreas.hansson@arm.comclass cmdScheduler { 5110428Sandreas.hansson@arm.com public: 5210428Sandreas.hansson@arm.com #define READ 0 5310428Sandreas.hansson@arm.com #define WRITE 1 5410428Sandreas.hansson@arm.com #define ACTIVATE 2 5510428Sandreas.hansson@arm.com #define PRECHARGE 3 5610428Sandreas.hansson@arm.com #define POWER_DOWN 1 5710428Sandreas.hansson@arm.com #define SELF_REFRESH 2 5810428Sandreas.hansson@arm.com 5910428Sandreas.hansson@arm.com // the format of a transaction. 6010428Sandreas.hansson@arm.com class trans { 6110428Sandreas.hansson@arm.com public: 6211555Sjungma@eit.uni-kl.de int64_t type; 6311555Sjungma@eit.uni-kl.de int64_t timeStamp; 6411555Sjungma@eit.uni-kl.de uint64_t logicalAddress; 6510428Sandreas.hansson@arm.com }; 6610428Sandreas.hansson@arm.com 6710428Sandreas.hansson@arm.com std::vector<trans> transTrace; // to store the transactions. 6810428Sandreas.hansson@arm.com 6910428Sandreas.hansson@arm.com // the format of physical address. 7010428Sandreas.hansson@arm.com class physicalAddr { 7110428Sandreas.hansson@arm.com public: 7211555Sjungma@eit.uni-kl.de uint64_t rowAddr; 7311555Sjungma@eit.uni-kl.de uint64_t bankAddr; 7411555Sjungma@eit.uni-kl.de uint64_t bankGroupAddr; 7511555Sjungma@eit.uni-kl.de uint64_t colAddr; 7610428Sandreas.hansson@arm.com }; 7710428Sandreas.hansson@arm.com 7810428Sandreas.hansson@arm.com // the format of a command. 7910428Sandreas.hansson@arm.com class commandItem { 8010428Sandreas.hansson@arm.com public: 8111555Sjungma@eit.uni-kl.de int64_t Type; 8211555Sjungma@eit.uni-kl.de int64_t bank; 8311555Sjungma@eit.uni-kl.de int64_t time; 8410428Sandreas.hansson@arm.com std::string name; 8510428Sandreas.hansson@arm.com physicalAddr PhysicalAddr; 8610428Sandreas.hansson@arm.com // sorting the commands according to their scheduling time. 8710428Sandreas.hansson@arm.com struct commandItemSorter : public std::binary_function<commandItem&, 8810428Sandreas.hansson@arm.com commandItem&, bool>{ 8910428Sandreas.hansson@arm.com bool operator()(const commandItem& lhs, 9010428Sandreas.hansson@arm.com const commandItem& rhs) const 9110428Sandreas.hansson@arm.com { 9210428Sandreas.hansson@arm.com return lhs.time < rhs.time; 9310428Sandreas.hansson@arm.com } 9410428Sandreas.hansson@arm.com }; 9510428Sandreas.hansson@arm.com }; 9610428Sandreas.hansson@arm.com 9710428Sandreas.hansson@arm.com commandItem cmd; 9810428Sandreas.hansson@arm.com commandItem transFinish; // the last scheduled command for a transaction. 9910428Sandreas.hansson@arm.com commandItem PreRDWR; // the latest scheduled READ or WRITE command. 10010428Sandreas.hansson@arm.com // the scheduled ACTIVATE commands are stored in ACT. 10110428Sandreas.hansson@arm.com std::vector<commandItem> ACT; 10210428Sandreas.hansson@arm.com // PRE is sued to keep recording the time when a precharge occurs. 10310428Sandreas.hansson@arm.com std::vector<commandItem> PRE; 10410428Sandreas.hansson@arm.com // the scheduled READ or WRITE commands are stored in RDWR. 10510428Sandreas.hansson@arm.com std::vector<std::vector<commandItem> > RDWR; 10610428Sandreas.hansson@arm.com // all the scheduled commands for a transaction is stored by cmdScheduling. 10710428Sandreas.hansson@arm.com std::vector<commandItem> cmdScheduling; 10810428Sandreas.hansson@arm.com std::vector<commandItem> cmdList; 10910428Sandreas.hansson@arm.com unsigned elements; 11011555Sjungma@eit.uni-kl.de int64_t BI, BC, BGI; 11110428Sandreas.hansson@arm.com 11210428Sandreas.hansson@arm.com // the function used to translate a transaction into a sequence of 11310428Sandreas.hansson@arm.com // commands which are scheduled to the memory. 11411555Sjungma@eit.uni-kl.de void transTranslation(const MemorySpecification& memSpec, 11510428Sandreas.hansson@arm.com std::ifstream& trans_trace, 11610428Sandreas.hansson@arm.com int grouping, 11710428Sandreas.hansson@arm.com int interleaving, 11810428Sandreas.hansson@arm.com int burst, 11910428Sandreas.hansson@arm.com int powerdown); 12010428Sandreas.hansson@arm.com // get the transactions by reading the traces. 12110428Sandreas.hansson@arm.com void getTrans(std::ifstream& pwr_trace, 12211555Sjungma@eit.uni-kl.de const MemorySpecification& memSpec); 12310428Sandreas.hansson@arm.com // the initialization function for scheduling. 12411555Sjungma@eit.uni-kl.de void schedulingInitialization(const MemorySpecification& memSpec); 12510428Sandreas.hansson@arm.com // the function used to schedule commands according to the timing constraints. 12611555Sjungma@eit.uni-kl.de void analyticalScheduling(const MemorySpecification& memSpec); 12710428Sandreas.hansson@arm.com // translate the logical address into physical address. 12810428Sandreas.hansson@arm.com physicalAddr memoryMap(trans Trans, 12911555Sjungma@eit.uni-kl.de const MemorySpecification& memSpec); 13010428Sandreas.hansson@arm.com // the power down and power up are scheduled by pdScheduling 13111555Sjungma@eit.uni-kl.de void pdScheduling(int64_t endTime, 13211555Sjungma@eit.uni-kl.de int64_t timer, 13311555Sjungma@eit.uni-kl.de const MemorySpecification& memSpec); 13410428Sandreas.hansson@arm.com // get the timings for scheduling a precharge since a read or write command 13510428Sandreas.hansson@arm.com // is scheduled. 13611555Sjungma@eit.uni-kl.de int64_t getRWTP(int64_t transType, 13711555Sjungma@eit.uni-kl.de const MemorySpecification& memSpec); 13810428Sandreas.hansson@arm.com // get different kind of timing constraints according to the used memory. 13910428Sandreas.hansson@arm.com void getTimingConstraints(bool BGSwitch, 14011555Sjungma@eit.uni-kl.de const MemorySpecification& memSpec, 14111555Sjungma@eit.uni-kl.de int64_t PreType, 14211555Sjungma@eit.uni-kl.de int64_t CurrentType); 14310428Sandreas.hansson@arm.com 14411555Sjungma@eit.uni-kl.de uint64_t uintLog2(uint64_t in); 14511555Sjungma@eit.uni-kl.de 14611555Sjungma@eit.uni-kl.de int64_t transTime; 14710428Sandreas.hansson@arm.com // the flag for power down. 14811555Sjungma@eit.uni-kl.de int64_t power_down; 14911555Sjungma@eit.uni-kl.de int64_t Inselfrefresh; 15011555Sjungma@eit.uni-kl.de int64_t tRRD_init; 15111555Sjungma@eit.uni-kl.de int64_t tCCD_init; 15211555Sjungma@eit.uni-kl.de int64_t tWTR_init; 15311555Sjungma@eit.uni-kl.de int64_t tREF; 15411555Sjungma@eit.uni-kl.de int64_t tSwitch_init; 15511555Sjungma@eit.uni-kl.de int64_t tRWTP; 15611555Sjungma@eit.uni-kl.de int64_t bankaccess; 15711555Sjungma@eit.uni-kl.de int64_t nBanks; 15811555Sjungma@eit.uni-kl.de int64_t nColumns; 15911555Sjungma@eit.uni-kl.de int64_t burstLength; 16011555Sjungma@eit.uni-kl.de int64_t nbrOfBankGroups; 16110428Sandreas.hansson@arm.com bool timingsGet; 16211555Sjungma@eit.uni-kl.de int64_t startTime; 16310428Sandreas.hansson@arm.com 16410428Sandreas.hansson@arm.com // the scheduling results for all the transactions are written into 16510428Sandreas.hansson@arm.com // commands which will be used by the power analysis part. 16610428Sandreas.hansson@arm.com std::ofstream commands; 16710428Sandreas.hansson@arm.com}; 16810428Sandreas.hansson@arm.com} 16910428Sandreas.hansson@arm.com 17010428Sandreas.hansson@arm.com#endif // ifndef CMDSCHEDULER_H 171