/gem5/src/arch/arm/ |
H A D | isa_device.hh | 75 virtual void setMiscReg(int misc_reg, RegVal val) = 0; 83 virtual RegVal readMiscReg(int misc_reg) = 0; 103 void setMiscReg(int misc_reg, RegVal val) override; 104 RegVal readMiscReg(int misc_reg) override;
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H A D | isa_device.cc | 61 DummyISADevice::setMiscReg(int misc_reg, RegVal val) 68 RegVal
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H A D | process.hh | 90 RegVal getSyscallArg(ThreadContext *tc, int &i, int width) override; 91 RegVal getSyscallArg(ThreadContext *tc, int &i) override; 92 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; 110 RegVal getSyscallArg(ThreadContext *tc, int &i, int width) override; 111 RegVal getSyscallArg(ThreadContext *tc, int &i) override; 112 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
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/gem5/src/arch/power/ |
H A D | isa.hh | 53 RegVal dummy; 54 RegVal miscRegs[NumMiscRegs]; 64 RegVal 71 RegVal 79 setMiscRegNoEffect(int misc_reg, RegVal val) 85 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
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H A D | process.hh | 53 RegVal getSyscallArg(ThreadContext *tc, int &i); 56 void setSyscallArg(ThreadContext *tc, int i, RegVal val);
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/gem5/src/arch/hsail/ |
H A D | gpu_isa.hh | 56 writeMiscReg(int opIdx, RegVal operandVal) 61 RegVal
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/gem5/src/arch/power/linux/ |
H A D | process.hh | 48 RegVal getSyscallArg(ThreadContext *tc, int &i); 51 void setSyscallArg(ThreadContext *tc, int i, RegVal val);
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/gem5/src/gpu-compute/ |
H A D | gpu_exec_context.hh | 53 RegVal readMiscReg(int opIdx) const; 54 void writeMiscReg(int opIdx, RegVal operandVal);
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H A D | gpu_exec_context.cc | 56 RegVal 64 GPUExecContext::writeMiscReg(int opIdx, RegVal operandVal)
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/gem5/src/arch/riscv/ |
H A D | isa.hh | 68 std::vector<RegVal> miscRegFile; 77 RegVal readMiscRegNoEffect(int misc_reg) const; 78 RegVal readMiscReg(int misc_reg, ThreadContext *tc); 79 void setMiscRegNoEffect(int misc_reg, RegVal val); 80 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
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H A D | registers.hh | 655 const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET; 656 const RegVal ISA_EXT_MASK = mask(26); 657 const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK; 659 const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1); 660 const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET; 661 const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET; 662 const RegVal STATUS_TSR_MASK = 1ULL << 22; 663 const RegVal STATUS_TW_MASK = 1ULL << 21; 664 const RegVal STATUS_TVM_MASK = 1ULL << 20; 665 const RegVal STATUS_MXR_MAS [all...] |
H A D | process.hh | 54 RegVal getSyscallArg(ThreadContext *tc, int &i) override; 57 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
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/gem5/src/arch/mips/ |
H A D | isa.hh | 71 std::vector<std::vector<RegVal> > miscRegFile; 72 std::vector<std::vector<RegVal> > miscRegFile_WriteMask; 91 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 94 RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 96 RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val); 97 void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0); 98 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0); 101 void setMiscReg(int misc_reg, RegVal val,
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H A D | process.hh | 54 RegVal getSyscallArg(ThreadContext *tc, int &i); 57 void setSyscallArg(ThreadContext *tc, int i, RegVal val);
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/gem5/src/arch/x86/linux/ |
H A D | process.hh | 58 RegVal flags); 67 RegVal flags);
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/gem5/src/arch/x86/ |
H A D | mmapped_ipr.hh | 65 pkt->getAddr() / sizeof(RegVal)); 66 RegVal data = htog(xc->readMiscReg(index)); 68 assert(offset + pkt->getSize() <= sizeof(RegVal)); 82 pkt->getAddr() / sizeof(RegVal)); 83 RegVal data = htog(xc->readMiscRegNoEffect(index)); 85 assert(offset + pkt->getSize() <= sizeof(RegVal));
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H A D | isa.hh | 54 RegVal regVal[NUM_MISCREGS]; 67 RegVal readMiscRegNoEffect(int miscReg) const; 68 RegVal readMiscReg(int miscReg, ThreadContext *tc); 70 void setMiscRegNoEffect(int miscReg, RegVal val); 71 void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
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H A D | process.hh | 88 Process *process, RegVal flags) override; 138 RegVal getSyscallArg(ThreadContext *tc, int &i) override; 141 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; 143 Process *process, RegVal flags) override; 182 RegVal getSyscallArg(ThreadContext *tc, int &i) override; 183 RegVal getSyscallArg(ThreadContext *tc, int &i, int width) override; 184 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; 186 Process *process, RegVal flags) override;
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/gem5/src/arch/alpha/ |
H A D | process.hh | 52 RegVal getSyscallArg(ThreadContext *tc, int &i) override; 55 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
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H A D | isa.hh | 77 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 78 RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 80 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0); 81 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc,
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H A D | idle_event.cc | 43 RegVal val = tc->readMiscRegNoEffect(IPR_PALtemp23);
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/gem5/src/cpu/ |
H A D | thread_context.hh | 209 virtual RegVal readIntReg(RegIndex reg_idx) const = 0; 211 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0; 251 virtual RegVal readCCReg(RegIndex reg_idx) const = 0; 253 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0; 255 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0; 264 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0; 286 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0; 288 virtual RegVal readMiscReg(RegIndex misc_reg) = 0; 290 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0; 292 virtual void setMiscReg(RegIndex misc_reg, RegVal va [all...] |
H A D | exec_context.hh | 89 virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0; 93 int idx, RegVal val) = 0; 105 virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0; 110 int idx, RegVal val) = 0; 191 virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0; 193 const StaticInst *si, int idx, RegVal val) = 0; 200 virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0; 202 int idx, RegVal val) = 0; 208 virtual RegVal readMiscReg(int misc_reg) = 0; 214 virtual void setMiscReg(int misc_reg, RegVal va [all...] |
H A D | thread_context.cc | 65 RegVal t1 = one->readIntReg(i); 66 RegVal t2 = two->readIntReg(i); 74 RegVal t1 = one->readFloatReg(i); 75 RegVal t2 = two->readFloatReg(i); 102 RegVal t1 = one->readMiscRegNoEffect(i); 103 RegVal t2 = two->readMiscRegNoEffect(i); 111 RegVal t1 = one->readCCReg(i); 112 RegVal t2 = two->readCCReg(i); 170 RegVal floatRegs[NumFloatRegs]; 189 RegVal intReg [all...] |
/gem5/src/cpu/o3/ |
H A D | thread_context.hh | 190 RegVal 196 RegVal 203 RegVal 304 RegVal 313 setIntReg(RegIndex reg_idx, RegVal val) override 319 setFloatReg(RegIndex reg_idx, RegVal val) override 345 setCCReg(RegIndex reg_idx, RegVal val) override 384 RegVal 392 RegVal 399 void setMiscRegNoEffect(RegIndex misc_reg, RegVal va [all...] |