History log of /gem5/src/arch/mips/process.hh
Revision Date Author Comments
# 13615:5cc9363f5ab7 19-Nov-2018 Gabe Black <gabeblack@google.com>

mips: Stop using architecture specific register types.

Change-Id: I764f6eea214ba4e03cc0fe19a21abcb0ebd04408
Reviewed-on: https://gem5-review.googlesource.com/c/14462
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 12431:000549e1f497 22-Dec-2017 Gabe Black <gabeblack@google.com>

arch,mem: Move page table construction into the arch classes.

This gets rid of an awkward NoArchPageTable class, and also gives the
arch a place to inject ISA specific parameters (specifically page size)
without having to have TheISA:: in the generic version of these types.

Change-Id: I1412f303460d5c43dafdb9b3cd07af81c908a441
Reviewed-on: https://gem5-review.googlesource.com/6981
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 11851:824055fe6b30 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.


# 11800:54436a1784dc 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.


# 10299:bec0c5ffc323 28-Aug-2014 Alexandru <alexandru.dutu@amd.com>

mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.


# 9552:460cf901acba 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Add warning for overloaded virtual functions

A derived function with a different signature than a base class
function will result in the base class function of the same name being
hidden. The parameter list and return type for the member function in
the derived class must match those of the member function in the base
class, otherwise the function in the derived class will hide the
function in the base class and no polymorphic behaviour will occur.

This patch addresses these warnings by ensuring a unique function name
to avoid (unintentionally) hiding any functions.


# 8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


# 7532:3f6413fc37a2 17-Aug-2010 Steve Reinhardt <steve.reinhardt@amd.com>

sim: revamp unserialization procedure

Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.

If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject. The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects. However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found. (Note that the default warning for a missing
checkpoint section is now gone.)

If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead. This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.

Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().


# 6811:f130ea67e453 31-Dec-2009 Matt DeVuyst

MIPS: Beef up process initialization.


# 6701:4842482e1bd1 30-Oct-2009 Gabe Black <gblack@eecs.umich.edu>

Syscalls: Make system calls access arguments like a stack, not an array.

When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.


# 6650:f23a18fec0ef 17-Sep-2009 Korey Sewell <ksewell@umich.edu>

mips: fix command line arguments
arguments were not being saved correctly into M5 memory


# 5958:2d9737bf3c2f 27-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

Processes: Make getting and setting system call arguments part of a process object.


# 5268:5bfc53fe60e7 16-Nov-2007 Korey Sewell <ksewell@umich.edu>

go back and fix up MIPS copyright headers


# 5222:bb733a878f85 13-Nov-2007 Korey Sewell <ksewell@umich.edu>

Add in files from merge-bare-iron, get them compiling in FS and SE mode


# 5154:7e6431213487 16-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.


# 4661:44458219add1 22-Jun-2007 Korey Sewell <ksewell@umich.edu>

mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".


# 3669:3607aaed36b6 16-Nov-2006 Nathan Binkert <binkertn@umich.edu>

Implement current working directory for LiveProcesses


# 3114:7a4771b9b720 17-Sep-2006 Gabe Black <gblack@eecs.umich.edu>

Finished changing how stat structures are translated, fixed the handling of various ids as LiveProcess parameters.

src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.


# 2935:d1223a6c9156 23-Jul-2006 Korey Sewell <ksewell@umich.edu>

This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!

Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )

src/arch/alpha/isa/mem.isa:
spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
Gabe really authored this
src/arch/mips/isa/decoder.isa:
add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
Steven really did this file
src/arch/mips/isa/formats/branch.isa:
fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
update LoadStoreBase template
src/arch/mips/isa_traits.cc:
update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
add in nextNPC variable and supporting functions.

add isCondDelaySlot function

Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
init nextNPC
src/cpu/o3/SConscript:
add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
add some extra communication variables to aid in handling the
delay slots
src/cpu/o3/commit.hh:
minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
Update function interface ...

adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
update removeInstsNotInROB
src/cpu/o3/decode.hh:
declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
no need for my name here
src/cpu/o3/isa_specific.hh:
add in MIPS files
src/cpu/o3/scoreboard.hh:
dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
MIPS file for O3CPU...mirrors ALPHA definition


# 2909:4f5e7d6fab54 14-Jul-2006 Korey Sewell <ksewell@umich.edu>

MIPS specific fixes ... the main thing is that SMT threads get their own stack space instead of all stacks start to space

src/arch/mips/isa_traits.hh:
MaxAddr is defined in config.py now
src/arch/mips/process.cc:
adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
add stack_start static variable


# 2715:4032e02b525e 11-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Move LiveProcess::create() from arch-specific files
bcak to main LiveProcess, then automatically select
ISA based on object file type. Now simulation scripts
no longer need to care about the ISA, as they can just
call LiveProcess().

configs/test/test.py:
Script no longer cares about ISA.
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/sim/process.cc:
src/sim/process.hh:
Move create() from arch-specific files back to
main LiveProcess, then automatically select ISA
based on object file type.


# 2686:f0d591379ac3 09-Jun-2006 Korey Sewell <ksewell@umich.edu>

Merging in a month of changes

src/arch/isa_parser.py:
Sign extend bit if you read int reg that is greater than default size
src/arch/mips/SConscript:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/formats.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/isa_traits.cc:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/utility.hh:
1 month of changes!
src/arch/mips/isa/formats/control.isa:
control formats
src/arch/mips/isa/formats/mt.isa:
mips mt format
src/arch/mips/utility.cc:
utility functions


# 2665:a124942bacb8 31-May-2006 Ali Saidi <saidi@eecs.umich.edu>

Updated Authors from bk prs info


# 2632:1bb2f91485ea 22-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.