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13581:b6dcd0183747 |
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13-Oct-2018 |
Gabe Black <gabeblack@google.com> |
arm: Get rid of some register type definitions.
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal.
Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435 Reviewed-on: https://gem5-review.googlesource.com/c/13625 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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13166:88ad31e419ed |
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02-Oct-2018 |
Matteo Andreozzi <Matteo.Andreozzi@arm.com> |
arch-arm: Mark ArmProcess method as override
Allows compilation on clang3.5+ by fixing Winconsistent-missing-override
Change-Id: Ic0ebf3869fc2d9a29fcf7cf5a6535952f41714d0 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13227 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13121:4741df518ab8 |
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19-Sep-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
sim-se: Different HWCAP for ArmProcess32/64
AArch32 and AArch64 have different HWCAP flags in Linux, but we are currently using AArch32 HWCAP flags to initialize the aux vector of both AArch32 and AArch64 binaries.
This patch also fixes a bug that was introduced by running in SE mode a target binary compiled with glibc > 2.18. Using AArch32 flags resulted on CPUID flag being set for AArch64. This incorrectly tells libc that emulation of the midr_el1 is supported. In FullSystem this might work, but since we are in Syscall Emulation there is no OS behind emulating the mrs midr_el1 instruction.
By separating AArch32 flags from AArch64 flags we are turning off the CPUID hwcap flag in SE mode.
Change-Id: I9f651957ba9d19dc2bc06606de070c6586f0f9fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12884 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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12431:000549e1f497 |
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22-Dec-2017 |
Gabe Black <gabeblack@google.com> |
arch,mem: Move page table construction into the arch classes.
This gets rid of an awkward NoArchPageTable class, and also gives the arch a place to inject ISA specific parameters (specifically page size) without having to have TheISA:: in the generic version of these types.
Change-Id: I1412f303460d5c43dafdb9b3cd07af81c908a441 Reviewed-on: https://gem5-review.googlesource.com/6981 Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
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11851:824055fe6b30 |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process.
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11800:54436a1784dc |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 3/22] reduce include dependencies in some headers
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
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10537:47fe87b0cf97 |
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14-Nov-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arm: Fixes based on UBSan and static analysis
Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base.
Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code.
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10299:bec0c5ffc323 |
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28-Aug-2014 |
Alexandru <alexandru.dutu@amd.com> |
mem: adding architectural page table support for SE mode This patch enables the use of page tables that are stored in system memory and respect x86 specification, in SE mode. It defines an architectural page table for x86 as a MultiLevelPageTable class and puts a placeholder class for other ISAs page tables, giving the possibility for future implementation.
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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9552:460cf901acba |
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19-Feb-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Add warning for overloaded virtual functions
A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur.
This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions.
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8229:78bf55f23338 |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes
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8216:70e61aa65759 |
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10-Apr-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Fix checkpoint restoration in ARM_SE.
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8177:a983c62ef6d0 |
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24-Mar-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Arm: Get rid of the unused copyStringArray32 method from Arm process classes.
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7441:be2acdfb8bdc |
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02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all Spec2k benchmarks seem to run with atomic or timing mode simple CPUs. Fixed up some constants, handling of 64 bit arguments, and marked a few more syscalls ignoreFunc.
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7096:e81026b9dfe0 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Allow ARM processes to start in Thumb mode.
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6701:4842482e1bd1 |
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30-Oct-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Syscalls: Make system calls access arguments like a stack, not an array.
When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly.
All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job.
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6020:0647c8b31a99 |
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06-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Merge ARM into the head. ARM will compile but may not actually work.
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6019:76890d8b28f5 |
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05-Apr-2009 |
Stephen Hines <hines@cs.fsu.edu> |
arm: add ARM support to M5
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