process.hh revision 11800:54436a1784dc
12497SN/A/* 214006Stiago.muck@arm.com* Copyright (c) 2012 ARM Limited 38711SN/A * All rights reserved 48711SN/A * 58711SN/A * The license below extends only to copyright in the software and shall 68711SN/A * not be construed as granting a license to any other intellectual 78711SN/A * property including but not limited to intellectual property relating 88711SN/A * to a hardware implementation of the functionality of the software 98711SN/A * licensed hereunder. You may use the software subject to the license 108711SN/A * terms below provided that you ensure that this notice is replicated 118711SN/A * unmodified and in its entirety in all distributions of the software, 128711SN/A * modified or unmodified, in source code or in binary form. 138711SN/A * 142497SN/A * Copyright (c) 2007-2008 The Florida State University 152497SN/A * All rights reserved. 162497SN/A * 172497SN/A * Redistribution and use in source and binary forms, with or without 182497SN/A * modification, are permitted provided that the following conditions are 192497SN/A * met: redistributions of source code must retain the above copyright 202497SN/A * notice, this list of conditions and the following disclaimer; 212497SN/A * redistributions in binary form must reproduce the above copyright 222497SN/A * notice, this list of conditions and the following disclaimer in the 232497SN/A * documentation and/or other materials provided with the distribution; 242497SN/A * neither the name of the copyright holders nor the names of its 252497SN/A * contributors may be used to endorse or promote products derived from 262497SN/A * this software without specific prior written permission. 272497SN/A * 282497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Stephen Hines 418715SN/A */ 428922SN/A 4312351Snikos.nikoleris@arm.com#ifndef __ARM_PROCESS_HH__ 442497SN/A#define __ARM_PROCESS_HH__ 452497SN/A 462497SN/A#include <string> 472982SN/A#include <vector> 4810405Sandreas.hansson@arm.com 492497SN/A#include "arch/arm/intregs.hh" 502497SN/A#include "base/loader/object_file.hh" 5111793Sbrandon.potter@amd.com#include "mem/page_table.hh" 5211793Sbrandon.potter@amd.com#include "sim/process.hh" 5312334Sgabeblack@google.com 542548SN/Aclass LiveProcess; 5510405Sandreas.hansson@arm.comclass ObjectFile; 5610405Sandreas.hansson@arm.comclass System; 579524SN/A 582497SN/Aclass ArmLiveProcess : public LiveProcess 5910405Sandreas.hansson@arm.com{ 6010719SMarco.Balboni@ARM.com protected: 6111334Sandreas.hansson@arm.com ObjectFile::Arch arch; 6214006Stiago.muck@arm.com ArmLiveProcess(LiveProcessParams * params, ObjectFile *objFile, 6314006Stiago.muck@arm.com ObjectFile::Arch _arch); 6412341Snikos.nikoleris@arm.com template<class IntType> 6512341Snikos.nikoleris@arm.com void argsInit(int pageSize, ArmISA::IntRegIndex spIndex); 667523SN/A}; 678851SN/A 688948SN/Aclass ArmLiveProcess32 : public ArmLiveProcess 698948SN/A{ 708851SN/A protected: 719095SN/A ArmLiveProcess32(LiveProcessParams * params, ObjectFile *objFile, 7210405Sandreas.hansson@arm.com ObjectFile::Arch _arch); 738922SN/A 749715SN/A void initState(); 759715SN/A 7613808Sgabeblack@google.com public: 7713808Sgabeblack@google.com 788851SN/A ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width); 798851SN/A ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i); 808948SN/A void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val); 818948SN/A void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); 828915SN/A}; 839031SN/A 849095SN/Aclass ArmLiveProcess64 : public ArmLiveProcess 8510405Sandreas.hansson@arm.com{ 8613808Sgabeblack@google.com protected: 878922SN/A ArmLiveProcess64(LiveProcessParams * params, ObjectFile *objFile, 889715SN/A ObjectFile::Arch _arch); 8913808Sgabeblack@google.com 9010713Sandreas.hansson@arm.com void initState(); 9110713Sandreas.hansson@arm.com 9210713Sandreas.hansson@arm.com public: 938915SN/A 948915SN/A ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width); 958948SN/A ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i); 968851SN/A void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val); 979095SN/A void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); 9810888Sandreas.hansson@arm.com}; 998922SN/A 1009715SN/A/* No architectural page table defined for this ISA */ 1019715SN/Atypedef NoArchPageTable ArchPageTable; 1029716SN/A 1038851SN/A#endif // __ARM_PROCESS_HH__ 1047523SN/A 1057523SN/A