Searched refs:QueuedMasterPort (Results 1 - 11 of 11) sorted by relevance
| /gem5/src/mem/ |
| H A D | qport.hh | 102 * The QueuedMasterPort combines two queues, a request queue and a
108 class QueuedMasterPort : public MasterPort class in inherits:MasterPort
132 QueuedMasterPort(const std::string& name, SimObject* owner, function in class:QueuedMasterPort
140 virtual ~QueuedMasterPort() { }
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| H A D | mem_delay.hh | 76 class MasterPort : public QueuedMasterPort
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| H A D | mem_delay.cc | 83 : QueuedMasterPort(_name, &_parent,
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| /gem5/src/dev/x86/ |
| H A D | intdev.hh | 90 class IntMasterPort : public QueuedMasterPort
101 QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
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| /gem5/src/mem/ruby/system/ |
| H A D | RubyPort.hh | 61 class MemMasterPort : public QueuedMasterPort
105 class PioMasterPort : public QueuedMasterPort
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| H A D | RubyPort.cc | 125 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
140 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
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| /gem5/src/dev/arm/ |
| H A D | smmu_v3_ports.hh | 111 class SMMUATSMasterPort : public QueuedMasterPort
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| H A D | smmu_v3_ports.cc | 143 QueuedMasterPort(_name, &_ifc, reqQueue, snoopRespQueue),
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | AbstractController.hh | 233 class MemoryPort : public QueuedMasterPort
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| H A D | AbstractController.cc | 383 : QueuedMasterPort(_name, _controller, reqQueue, snoopRespQueue),
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| /gem5/src/mem/cache/ |
| H A D | base.hh | 126 class CacheMasterPort : public QueuedMasterPort
146 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
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