1/*
2 * Copyright (c) 2017,2019 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
42#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
43
44#include <exception>
45#include <iostream>
46#include <string>
47
48#include "base/addr_range.hh"
49#include "base/callback.hh"
50#include "mem/packet.hh"
51#include "mem/qport.hh"
52#include "mem/ruby/common/Address.hh"
53#include "mem/ruby/common/Consumer.hh"
54#include "mem/ruby/common/DataBlock.hh"
55#include "mem/ruby/common/Histogram.hh"
56#include "mem/ruby/common/MachineID.hh"
57#include "mem/ruby/network/MessageBuffer.hh"
58#include "mem/ruby/protocol/AccessPermission.hh"
59#include "mem/ruby/system/CacheRecorder.hh"
60#include "params/RubyController.hh"
61#include "sim/clocked_object.hh"
62
63class Network;
64class GPUCoalescer;
65
66// used to communicate that an in_port peeked the wrong message type
67class RejectException: public std::exception
68{
69    virtual const char* what() const throw()
70    { return "Port rejected message based on type"; }
71};
72
73class AbstractController : public ClockedObject, public Consumer
74{
75  public:
76    typedef RubyControllerParams Params;
77    AbstractController(const Params *p);
78    void init();
79    const Params *params() const { return (const Params *)_params; }
80
81    NodeID getVersion() const { return m_machineID.getNum(); }
82    MachineType getType() const { return m_machineID.getType(); }
83
84    void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
85
86    // return instance name
87    void blockOnQueue(Addr, MessageBuffer*);
88    bool isBlocked(Addr) const;
89    void unblock(Addr);
90    bool isBlocked(Addr);
91
92    virtual MessageBuffer* getMandatoryQueue() const = 0;
93    virtual MessageBuffer* getMemoryQueue() const = 0;
94    virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
95
96    virtual void print(std::ostream & out) const = 0;
97    virtual void wakeup() = 0;
98    virtual void resetStats() = 0;
99    virtual void regStats();
100
101    virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
102    virtual Sequencer* getCPUSequencer() const = 0;
103    virtual GPUCoalescer* getGPUCoalescer() const = 0;
104
105    // This latency is used by the sequencer when enqueueing requests.
106    // Different latencies may be used depending on the request type.
107    // This is the hit latency unless the top-level cache controller
108    // introduces additional cycles in the response path.
109    virtual Cycles mandatoryQueueLatency(const RubyRequestType& param_type)
110    { return m_mandatory_queue_latency; }
111
112    //! These functions are used by ruby system to read/write the data blocks
113    //! that exist with in the controller.
114    virtual void functionalRead(const Addr &addr, PacketPtr) = 0;
115    void functionalMemoryRead(PacketPtr);
116    //! The return value indicates the number of messages written with the
117    //! data from the packet.
118    virtual int functionalWriteBuffers(PacketPtr&) = 0;
119    virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
120    int functionalMemoryWrite(PacketPtr);
121
122    //! Function for enqueuing a prefetch request
123    virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
124    { fatal("Prefetches not implemented!");}
125
126    //! Function for collating statistics from all the controllers of this
127    //! particular type. This function should only be called from the
128    //! version 0 of this controller type.
129    virtual void collateStats()
130    {fatal("collateStats() should be overridden!");}
131
132    //! Initialize the message buffers.
133    virtual void initNetQueues() = 0;
134
135    /** A function used to return the port associated with this bus object. */
136    Port &getPort(const std::string &if_name,
137                  PortID idx=InvalidPortID);
138
139    void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
140    void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
141                          const DataBlock &block);
142    void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
143                                 const DataBlock &block, int size);
144    void recvTimingResp(PacketPtr pkt);
145    Tick recvAtomic(PacketPtr pkt);
146
147    const AddrRangeList &getAddrRanges() const { return addrRanges; }
148
149  public:
150    MachineID getMachineID() const { return m_machineID; }
151
152    Stats::Histogram& getDelayHist() { return m_delayHistogram; }
153    Stats::Histogram& getDelayVCHist(uint32_t index)
154    { return *(m_delayVCHistogram[index]); }
155
156    /**
157     * Map an address to the correct MachineID
158     *
159     * This function querries the network for the NodeID of the
160     * destination for a given request using its address and the type
161     * of the destination. For example for a request with a given
162     * address to a directory it will return the MachineID of the
163     * authorative directory.
164     *
165     * @param the destination address
166     * @param the type of the destination
167     * @return the MachineID of the destination
168     */
169    MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
170
171  protected:
172    //! Profiles original cache requests including PUTs
173    void profileRequest(const std::string &request);
174    //! Profiles the delay associated with messages.
175    void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
176
177    void stallBuffer(MessageBuffer* buf, Addr addr);
178    void wakeUpBuffers(Addr addr);
179    void wakeUpAllBuffers(Addr addr);
180    void wakeUpAllBuffers();
181
182  protected:
183    const NodeID m_version;
184    MachineID m_machineID;
185    const NodeID m_clusterID;
186
187    // MasterID used by some components of gem5.
188    const MasterID m_masterId;
189
190    Network *m_net_ptr;
191    bool m_is_blocking;
192    std::map<Addr, MessageBuffer*> m_block_map;
193
194    typedef std::vector<MessageBuffer*> MsgVecType;
195    typedef std::set<MessageBuffer*> MsgBufType;
196    typedef std::map<Addr, MsgVecType* > WaitingBufType;
197    WaitingBufType m_waiting_buffers;
198
199    unsigned int m_in_ports;
200    unsigned int m_cur_in_port;
201    const int m_number_of_TBEs;
202    const int m_transitions_per_cycle;
203    const unsigned int m_buffer_size;
204    Cycles m_recycle_latency;
205    const Cycles m_mandatory_queue_latency;
206
207    //! Counter for the number of cycles when the transitions carried out
208    //! were equal to the maximum allowed
209    Stats::Scalar m_fully_busy_cycles;
210
211    //! Histogram for profiling delay for the messages this controller
212    //! cares for
213    Stats::Histogram m_delayHistogram;
214    std::vector<Stats::Histogram *> m_delayVCHistogram;
215
216    //! Callback class used for collating statistics from all the
217    //! controller of this type.
218    class StatsCallback : public Callback
219    {
220      private:
221        AbstractController *ctr;
222
223      public:
224        virtual ~StatsCallback() {}
225        StatsCallback(AbstractController *_ctr) : ctr(_ctr) {}
226        void process() {ctr->collateStats();}
227    };
228
229    /**
230     * Port that forwards requests and receives responses from the
231     * memory controller.  It has a queue of packets not yet sent.
232     */
233    class MemoryPort : public QueuedMasterPort
234    {
235      private:
236        // Packet queues used to store outgoing requests and snoop responses.
237        ReqPacketQueue reqQueue;
238        SnoopRespPacketQueue snoopRespQueue;
239
240        // Controller that operates this port.
241        AbstractController *controller;
242
243      public:
244        MemoryPort(const std::string &_name, AbstractController *_controller,
245                   const std::string &_label);
246
247        // Function for receiving a timing response from the peer port.
248        // Currently the pkt is handed to the coherence controller
249        // associated with this port.
250        bool recvTimingResp(PacketPtr pkt);
251    };
252
253    /* Master port to the memory controller. */
254    MemoryPort memoryPort;
255
256    // State that is stored in packets sent to the memory controller.
257    struct SenderState : public Packet::SenderState
258    {
259        // Id of the machine from which the request originated.
260        MachineID id;
261
262        SenderState(MachineID _id) : id(_id)
263        {}
264    };
265
266  private:
267    /** The address range to which the controller responds on the CPU side. */
268    const AddrRangeList addrRanges;
269};
270
271#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
272