1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Stan Czerniawski
38 */
39
40#ifndef __DEV_ARM_SMMU_V3_PORTS_HH__
41#define __DEV_ARM_SMMU_V3_PORTS_HH__
42
43#include "mem/qport.hh"
44#include "mem/tport.hh"
45
46class SMMUv3;
47class SMMUv3SlaveInterface;
48
49class SMMUMasterPort : public MasterPort
50{
51  protected:
52    SMMUv3 &smmu;
53
54    virtual bool recvTimingResp(PacketPtr pkt);
55    virtual void recvReqRetry();
56
57  public:
58    SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu);
59    virtual ~SMMUMasterPort() {}
60};
61
62// Separate master port to send MMU initiated requests on
63class SMMUMasterTableWalkPort : public MasterPort
64{
65  protected:
66    SMMUv3 &smmu;
67
68    virtual bool recvTimingResp(PacketPtr pkt);
69    virtual void recvReqRetry();
70
71  public:
72    SMMUMasterTableWalkPort(const std::string &_name, SMMUv3 &_smmu);
73    virtual ~SMMUMasterTableWalkPort() {}
74};
75
76class SMMUSlavePort : public QueuedSlavePort
77{
78  protected:
79    SMMUv3SlaveInterface &ifc;
80    RespPacketQueue respQueue;
81
82    virtual void recvFunctional(PacketPtr pkt);
83    virtual Tick recvAtomic(PacketPtr pkt);
84    virtual bool recvTimingReq(PacketPtr pkt);
85
86  public:
87    SMMUSlavePort(const std::string &_name,
88                  SMMUv3SlaveInterface &_ifc,
89                  PortID _id = InvalidPortID);
90    virtual ~SMMUSlavePort() {}
91
92    virtual AddrRangeList getAddrRanges() const
93    { return AddrRangeList { AddrRange(0, UINT64_MAX) }; }
94};
95
96class SMMUControlPort : public SimpleTimingPort
97{
98  protected:
99    SMMUv3 &smmu;
100    AddrRange addrRange;
101
102    virtual Tick recvAtomic(PacketPtr pkt);
103    virtual AddrRangeList getAddrRanges() const;
104
105  public:
106    SMMUControlPort(const std::string &_name, SMMUv3 &_smmu,
107                    AddrRange _addrRange);
108    virtual ~SMMUControlPort() {}
109};
110
111class SMMUATSMasterPort : public QueuedMasterPort
112{
113  protected:
114    SMMUv3SlaveInterface &ifc;
115    ReqPacketQueue reqQueue;
116    SnoopRespPacketQueue snoopRespQueue;
117
118    virtual bool recvTimingResp(PacketPtr pkt);
119
120  public:
121    SMMUATSMasterPort(const std::string &_name, SMMUv3SlaveInterface &_ifc);
122    virtual ~SMMUATSMasterPort() {}
123};
124
125class SMMUATSSlavePort : public QueuedSlavePort
126{
127  protected:
128    SMMUv3SlaveInterface &ifc;
129    RespPacketQueue respQueue;
130
131    virtual void recvFunctional(PacketPtr pkt);
132    virtual Tick recvAtomic(PacketPtr pkt);
133    virtual bool recvTimingReq(PacketPtr pkt);
134
135    virtual AddrRangeList getAddrRanges() const
136    { return AddrRangeList(); }
137
138  public:
139    SMMUATSSlavePort(const std::string &_name, SMMUv3SlaveInterface &_ifc);
140    virtual ~SMMUATSSlavePort() {}
141};
142
143#endif /* __DEV_ARM_SMMU_V3_PORTS_HH__ */
144