Searched refs:PTE (Results 1 - 18 of 18) sorted by relevance

/gem5/src/arch/mips/
H A Dtlb.hh63 MipsISA::PTE *table; // the Page Table
68 MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
87 MipsISA::PTE *getEntry(unsigned) const;
95 MipsISA::PTE &index(bool advance = true);
96 void insert(Addr vaddr, MipsISA::PTE &pte);
97 void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
H A Dpagetable.cc42 PTE::serialize(CheckpointOut &cp) const
61 PTE::unserialize(CheckpointIn &cp)
H A Dtlb.cc66 table = new PTE[size];
67 memset(table, 0, sizeof(PTE[size]));
78 MipsISA::PTE *
82 PTE *retval = NULL;
87 PTE *pte = &table[index];
108 MipsISA::PTE*
125 PTE *pte = &table[index];
158 TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
186 TLB::insert(Addr addr, PTE &pte)
195 memset(table, 0, sizeof(PTE[siz
[all...]
H A Dpagetable.hh48 struct PTE struct in namespace:MipsISA
/gem5/src/arch/riscv/
H A Dtlb.hh62 RiscvISA::PTE *table; // the Page Table
67 RiscvISA::PTE *lookup(Addr vpn, uint8_t asn) const;
86 RiscvISA::PTE *getEntry(unsigned) const;
94 RiscvISA::PTE &index(bool advance = true);
95 void insert(Addr vaddr, RiscvISA::PTE &pte);
96 void insertAt(RiscvISA::PTE &pte, unsigned Index, int _smallPages);
H A Dpagetable.cc42 PTE::serialize(CheckpointOut &cp) const
61 PTE::unserialize(CheckpointIn &cp)
H A Dtlb.cc68 table = new PTE[size];
69 memset(table, 0, sizeof(PTE[size]));
80 RiscvISA::PTE *
84 PTE *retval = nullptr;
89 PTE *pte = &table[index];
110 RiscvISA::PTE*
127 PTE *pte = &table[index];
160 TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
188 TLB::insert(Addr addr, PTE &pte)
197 memset(table, 0, sizeof(PTE[siz
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H A Dpagetable.hh48 struct PTE struct in namespace:RiscvISA
/gem5/src/arch/power/
H A Dtlb.hh105 PowerISA::PTE *table; // the Page Table
117 PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const;
139 PowerISA::PTE *getEntry(unsigned) const;
149 PowerISA::PTE &index(bool advance = true);
150 void insert(Addr vaddr, PowerISA::PTE &pte);
151 void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
H A Dpagetable.cc46 PTE::serialize(CheckpointOut &cp) const
65 PTE::unserialize(CheckpointIn &cp)
H A Dtlb.cc70 table = new PowerISA::PTE[size];
71 memset(table, 0, sizeof(PowerISA::PTE[size]));
82 PowerISA::PTE *
86 PowerISA::PTE *retval = NULL;
91 PowerISA::PTE *pte = &table[index];
111 PowerISA::PTE*
128 PowerISA::PTE *pte = &table[index];
160 TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
184 TLB::insert(Addr addr, PowerISA::PTE &pte)
193 memset(table, 0, sizeof(PowerISA::PTE[siz
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H A Dpagetable.hh109 struct PTE struct in namespace:PowerISA
/gem5/src/arch/sparc/
H A Dtlb.hh126 /** Insert a PTE into the TLB. */
128 const PageTableEntry& PTE, int entry = -1);
H A Dtlb.cc98 const PageTableEntry& PTE, int entry)
106 va &= ~(PTE.size()-1);
108 tr.size = PTE.size() - 1;
116 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
122 tlb[x].range.va < va + PTE.size() - 1 &&
173 assert(PTE.valid());
175 new_entry->range.size = PTE.size() - 1;
179 new_entry->pte = PTE;
1378 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1411 ScopedCheckpointSection sec(cp, csprintf("PTE
97 insert(Addr va, int partition_id, int context_id, bool real, const PageTableEntry& PTE, int entry) argument
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/gem5/src/arch/x86/
H A Dpagetable_walker.hh92 PSEPD, PD, PTE enumerator in enum:X86ISA::Walker::WalkerState::State
H A Dpagetable_walker.cc363 "Got long mode PTE entry %#016x.\n", (uint64_t)pte);
424 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte);
459 nextState = PTE;
488 nextState = PTE;
490 case PTE:
492 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte);
/gem5/src/arch/arm/
H A Dpagetable.hh62 struct PTE struct in namespace:ArmISA
66 panic("Need to implement PTE serialization\n");
71 panic("Need to implement PTE serialization\n");
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h159 // page table entry (PTE) fields
172 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)

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