Searched refs:NumVecRegs (Results 1 - 14 of 14) sorted by relevance

/gem5/src/cpu/o3/
H A Drename_map.cc125 vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1);
127 vecElemMap.init(TheISA::NumVecRegs * NVecElems,
145 regFile->numVecPhysRegs() - TheISA::NumVecRegs,
162 TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg,
166 freeList->addRegs(range.first + TheISA::NumVecRegs, range.second);
205 TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
206 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
215 for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
H A Dcpu.cc214 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
264 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
272 for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
/gem5/src/arch/sparc/
H A Dregisters.hh77 const int NumVecRegs = 1; // Not applicable to SPARC member in namespace:SparcISA
/gem5/src/arch/arm/
H A Dregisters.hh94 const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs; member in namespace:ArmISA
108 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
H A Dutility.cc156 for (auto idx = 0; idx < NumVecRegs; idx++)
159 for (auto idx = 0; idx < NumVecRegs; idx++)
/gem5/src/arch/power/
H A Dregisters.hh76 const int NumVecRegs = 1; // Not applicable to Power member in namespace:PowerISA
/gem5/src/arch/x86/
H A Dregisters.hh81 const int NumVecRegs = 1; // Not applicable to x86 member in namespace:X86ISA
/gem5/src/cpu/
H A Dthread_context.cc82 for (int i = 0; i < TheISA::NumVecRegs; ++i) {
177 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
178 for (int i = 0; i < NumVecRegs; ++i) {
218 std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs);
220 for (int i = 0; i < NumVecRegs; ++i) {
H A Dsimple_thread.hh108 VecRegContainer vecRegs[TheISA::NumVecRegs];
269 for (int i = 0; i < TheISA::NumVecRegs; i++) {
310 assert(flatIndex < TheISA::NumVecRegs);
321 assert(flatIndex < TheISA::NumVecRegs);
336 assert(flatIndex < TheISA::NumVecRegs);
377 assert(flatIndex < TheISA::NumVecRegs);
411 assert(flatIndex < TheISA::NumVecRegs);
485 assert(flatIndex < TheISA::NumVecRegs);
495 assert(flatIndex < TheISA::NumVecRegs);
/gem5/src/arch/alpha/
H A Dregisters.hh95 const int NumVecRegs = 1; // Not applicable to Alpha member in namespace:AlphaISA
/gem5/src/cpu/minor/
H A Dscoreboard.hh98 (TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) +
H A Dscoreboard.cc82 TheISA::NumFloatRegs + TheISA::NumVecRegs + reg.index();
/gem5/src/arch/mips/
H A Dregisters.hh59 const int NumVecRegs = 1; // Not applicable to MIPS member in namespace:MipsISA
/gem5/src/arch/riscv/
H A Dregisters.hh92 const unsigned NumVecRegs = 1; // Not applicable to RISC-V member in namespace:RiscvISA

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