Searched refs:NumVecPredRegs (Results 1 - 12 of 12) sorted by relevance

/gem5/src/arch/sparc/
H A Dregisters.hh79 const int NumVecPredRegs = 1; // Not applicable to SPARC member in namespace:SparcISA
/gem5/src/arch/arm/
H A Dregisters.hh96 const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0 member in namespace:ArmISA
109 NumVecPredRegs + NumMiscRegs;
/gem5/src/arch/power/
H A Dregisters.hh78 const int NumVecPredRegs = 1; // Not applicable to Power member in namespace:PowerISA
/gem5/src/arch/x86/
H A Dregisters.hh83 const int NumVecPredRegs = 1; // Not applicable to x86 member in namespace:X86ISA
/gem5/src/cpu/
H A Dthread_context.cc92 for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
183 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
184 for (int i = 0; i < NumVecPredRegs; ++i) {
224 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
226 for (int i = 0; i < NumVecPredRegs; ++i) {
H A Dsimple_thread.hh109 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
272 for (int i = 0; i < TheISA::NumVecPredRegs; i++) {
422 assert(flatIndex < TheISA::NumVecPredRegs);
433 assert(flatIndex < TheISA::NumVecPredRegs);
505 assert(flatIndex < TheISA::NumVecPredRegs);
/gem5/src/arch/alpha/
H A Dregisters.hh97 const int NumVecPredRegs = 1; // Not applicable to Alpha member in namespace:AlphaISA
/gem5/src/cpu/minor/
H A Dscoreboard.hh99 TheISA::NumVecPredRegs),
/gem5/src/arch/mips/
H A Dregisters.hh61 const int NumVecPredRegs = 1; // Not applicable to MIPS member in namespace:MipsISA
/gem5/src/cpu/o3/
H A Drename_map.cc130 predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1);
H A Dcpu.cc215 assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
283 for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) {
/gem5/src/arch/riscv/
H A Dregisters.hh94 const int NumVecPredRegs = 1; // Not applicable to RISC-V member in namespace:RiscvISA

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