Searched refs:MiscRegClass (Results 1 - 15 of 15) sorted by relevance
| /gem5/src/arch/x86/ |
| H A D | isa.hh | 83 case MiscRegClass:
84 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
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| /gem5/src/arch/mips/ |
| H A D | mt.hh | 72 case MiscRegClass:
96 case MiscRegClass:
179 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_BIND), tid);
185 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS),
189 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_HALT),
195 setRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_RESTART),
216 setRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS),
252 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS),
255 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_HALT),
258 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_BIN
[all...] |
| /gem5/src/cpu/ |
| H A D | reg_class.hh | 65 MiscRegClass ///< Control (misc) register enumerator in enum:RegClass
72 const int NumRegClasses = MiscRegClass + 1;
132 return regClass != MiscRegClass;
167 bool isMiscReg() const { return regClass == MiscRegClass; }
174 return regClass != MiscRegClass;
193 case MiscRegClass:
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| /gem5/src/arch/sparc/ |
| H A D | isa.hh | 202 case MiscRegClass:
203 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_record.hh | 232 return (reg->regClass == MiscRegClass) &&
243 RegId reg(MiscRegClass, ArmISA::MISCREG_CPSR);
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| H A D | tarmac_record.cc | 178 case MiscRegClass:
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| /gem5/src/cpu/o3/ |
| H A D | rename_map.hh | 246 case MiscRegClass:
291 case MiscRegClass:
339 case MiscRegClass:
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| H A D | regfile.cc | 129 miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
215 case MiscRegClass:
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| H A D | dyn_inst.hh | 242 case MiscRegClass:
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| H A D | rename_impl.hh | 1094 case MiscRegClass:
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| /gem5/src/arch/x86/insts/ |
| H A D | static_inst.hh | 72 return MiscRegClass;
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| /gem5/src/cpu/minor/ |
| H A D | dyn_inst.cc | 144 case MiscRegClass:
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| H A D | scoreboard.cc | 89 case MiscRegClass:
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| /gem5/src/cpu/checker/ |
| H A D | cpu_impl.hh | 627 case MiscRegClass:
661 case MiscRegClass:
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| /gem5/src/arch/arm/ |
| H A D | isa.hh | 466 case MiscRegClass:
467 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
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