Searched refs:MISCREG_SCR_EL3 (Results 1 - 11 of 11) sorted by relevance

/gem5/src/arch/arm/
H A Dinterrupts.cc67 scr = tc->readMiscReg(MISCREG_SCR_EL3);
H A Dutility.cc198 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
207 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
329 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
H A Dfaults.cc1012 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1272 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1333 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1436 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1475 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1534 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1561 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1571 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
H A Disa.cc303 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
311 miscRegs[MISCREG_SCR_EL3] = 1;
683 readMiscRegNoEffect(MISCREG_SCR_EL3));
1846 case MISCREG_SCR_EL3:
H A Dmiscregs.hh478 MISCREG_SCR_EL3, enumerator in enum:ArmISA::MiscRegIndex
H A Dtlb.cc1342 scr = tc->readMiscReg(MISCREG_SCR_EL3);
H A Dmiscregs.cc1892 return MISCREG_SCR_EL3;
4029 InitReg(MISCREG_SCR_EL3)
/gem5/src/arch/arm/insts/
H A Dmisc64.cc148 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
H A Dstatic_inst.cc782 SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
1060 SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc227 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
363 (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
965 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
1287 SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
2384 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc439 { "scr_el3", MISCREG_SCR_EL3 },

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