Searched refs:Link (Results 1 - 9 of 9) sorted by relevance

/gem5/src/dev/net/
H A Detherlink.hh72 class Link class in class:EtherLink
109 Link(const std::string &name, EtherLink *p, int num,
111 ~Link() {}
131 Link *txlink;
134 Interface(const std::string &name, Link *txlink, Link *rxlink);
140 Link *link[2];
H A Ddist_etherlink.hh75 class Link : public Serializable class in class:DistEtherLink
87 Link(const std::string &name, DistEtherLink *p, function in class:DistEtherLink::Link
92 ~Link() {}
105 class TxLink : public Link
126 Link(name, p, d, &doneEvent), ticksPerByte(invBW),
147 class RxLink : public Link
166 Link(name, p, d, &_doneEvent), linkDelay(delay),
H A Detherlink.cc72 link[0] = new Link(name() + ".link0", this, 0, p->speed,
74 link[1] = new Link(name() + ".link1", this, 1, p->speed,
102 EtherLink::Interface::Interface(const string &name, Link *tx, Link *rx)
109 EtherLink::Link::Link(const string &name, EtherLink *p, int num, function in class:EtherLink::Link
132 EtherLink::Link::txComplete(EthPacketPtr packet)
140 EtherLink::Link::txDone()
162 EtherLink::Link::processTxQueue()
179 EtherLink::Link
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H A Ddist_etherlink.cc212 DistEtherLink::Link::serialize(CheckpointOut &cp) const
228 DistEtherLink::Link::unserialize(CheckpointIn &cp)
/gem5/ext/sst/tests/
H A Dtest6_arm_4c.py113 link = sst.Link("cpu_%s_link"%name)
119 link = sst.Link("sysbus_bus_link")
130 link = sst.Link("ioCache_bus_link")
145 link = sst.Link("cpu%u.l1iCache_bus_link" % num) ; bus_port = bus_port + 1
147 link = sst.Link("cpu%u.l1dCache_bus_link" % num) ; bus_port = bus_port + 1
149 link = sst.Link("cpu%u.itlbCache_bus_link" % num) ; bus_port = bus_port + 1
151 link = sst.Link("cpu%u.dtlbCache_bus_link" % num) ; bus_port = bus_port + 1
166 link = sst.Link("l2cache_bus_link")
201 sst.Link("link_cache_net_0").connect((l2cache, "directory", "10ns"), (comp_chiprtr, "port2", "2ns"))
202 sst.Link("link_dir_net_
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/gem5/ext/sst/
H A DExtSlave.hh56 class Link;
93 Link* link;
H A DExtMaster.hh62 class Link;
/gem5/src/systemc/tests/systemc/compliance_1666/test001/
H A Dtest001.cpp234 struct Link struct
236 Link *link;
265 Link* link;
285 link = new Link;
288 link->link = new Link;
/gem5/configs/common/
H A DHMC.py46 # [3] Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level
88 # | | Link Aggregator | opt |
91 # | | Serial Link + Ser | * 4 |
242 crossbar between port and Link Controller")
358 # Connect membus/traffic gen to Serial Link Controller for differrent HMC

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